Re: Information regarding C3 cpu state and bus mastering activity

From: Phillip Susi <psusi-3tLf1voIkJTQT0dZR+AlfA@public.gmane.org>
To: acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Subject: Re: Information regarding C3 cpu state and bus mastering activity
Date: Sun, 11 Dec 2005 22:42:15 -0500	[thread overview]
Message-ID: <439CF197.3090902@cfl.rr.com> (raw)
In-Reply-To: <439CC549.5060500-cGBD8117FJM@public.gmane.org>

I'm kind of confused as to why this is a problem myself.  Yes, the CPU 
cache does not snoop the busmaster activity and so the cache can become 
out of sync with ram, but isn't it the job of the driver that initiates 
the dma transfer to invalidate those cache lines once the transfer is 
complete to bring the cache back into sync?

Janosch Machowinski wrote:
> 
> No this is not Possibe. In C3 the processor disables his cache. If you 
> have busmaster activity, there are direct writes into the cache (if I 
> remeber right). So if you allow C3 and Busmaster, you will get into some 
> serious truble and loose data.
> 

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