Re: Information regarding C3 cpu state and bus mastering activity

[Marco Calviani <marco.calviani-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Hi list,

2005/12/12, Janosch Machowinski <scotch-cGBD8117FJM@public.gmane.org>:

> No this is not Possibe. In C3 the processor disables his cache. If you
> have busmaster activity, there are direct writes into the cache (if I
> remeber right). So if you allow C3 and Busmaster, you will get into some
> serious truble and loose data.

Is this an hardware limitation or a software one?
If i understood well this occur because the active bus polling that is
required to maintain communication with usb devices deny the CPU from
switching to C3, and even if there are no usb device connected but the
modules are loaded the polling prevent the switch.
Will it be possible to increase the polling time, so that maybe the
CPU can enter that state?

Regards,
Marco Calviani


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