Re: Information regarding C3 cpu state and bus mastering activity

[Marco Calviani <marco.calviani-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Hi Janosh,
  first of all thanks for your interest in this issue

> Okay, I read through this stuff once again. I would say, that busmaster
> activity is a direct write into memory. While the processor is in C3, it
> can not keep it's cache in sync with the memory. So there are two
> solutions to this problem for uniprocessor systems:
> 1. Either you flush the cache before entering C3. This takes a relative
> long period of time (according to ACPI 3.0 spec) so it should not be the
> prefered method.
> 2. Disable the busmaster. The kernel looks at the current busmaster
> activity and then chooses if it wants to disable busmaster and enter C3.

What are the possible consequences of disabling the busmaster? Does
this affects also other box component (i.d. i've read somewhere that
the busmaster is related to DMA access)?

And how is it possible to do so?



Many thanks in advance,
Marco Calviani


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