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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
Date: Sat, 24 Apr 2021 10:14:12 -0700	[thread overview]
Message-ID: <43dfcf5d-26b0-759d-296b-416d3566b2ea@linaro.org> (raw)
In-Reply-To: <024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com>

On 4/23/21 8:34 PM, Alistair Francis wrote:
> BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6

The issue got renumbered to 47, fwiw.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/insn32.decode | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index fecf0f15d5..8901ba1e1b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -288,7 +288,7 @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
>   hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
>   hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
>   
> -# *** RV32H Base Instruction Set ***
> +# *** RV64H Base Instruction Set ***
>   hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
>   hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
>   hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
> 



WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: Re: [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
Date: Sat, 24 Apr 2021 10:14:12 -0700	[thread overview]
Message-ID: <43dfcf5d-26b0-759d-296b-416d3566b2ea@linaro.org> (raw)
In-Reply-To: <024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com>

On 4/23/21 8:34 PM, Alistair Francis wrote:
> BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6

The issue got renumbered to 47, fwiw.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/insn32.decode | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index fecf0f15d5..8901ba1e1b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -288,7 +288,7 @@ hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
>   hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
>   hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
>   
> -# *** RV32H Base Instruction Set ***
> +# *** RV64H Base Instruction Set ***
>   hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
>   hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
>   hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
> 



  reply	other threads:[~2021-04-24 17:17 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-24  3:28 [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-24  3:28 ` Alistair Francis
2021-04-24  3:28 ` [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-24  3:28   ` Alistair Francis
2021-04-24  3:29 ` [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-24  3:29   ` Alistair Francis
2021-04-24  3:31 ` [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-24  3:31   ` Alistair Francis
2021-04-24  3:33 ` [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-24  3:33   ` Alistair Francis
2021-04-24  3:33 ` [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-24  3:33   ` Alistair Francis
2021-04-24  3:33 ` [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-24  3:33   ` Alistair Francis
2021-04-24  3:34 ` [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-24  3:34   ` Alistair Francis
2021-04-24  3:34 ` [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-04-24  3:34   ` Alistair Francis
2021-04-24 17:08   ` Richard Henderson
2021-04-24 17:08     ` Richard Henderson
2021-04-25 22:58     ` Alistair Francis
2021-04-25 22:58       ` Alistair Francis
2021-04-25 23:53       ` Richard Henderson
2021-04-25 23:53         ` Richard Henderson
2021-04-26  5:33         ` Alistair Francis
2021-04-26  5:33           ` Alistair Francis
2021-04-24  3:34 ` [PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-04-24  3:34   ` Alistair Francis
2021-04-24  3:34 ` [PATCH v3 10/10] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-04-24  3:34   ` Alistair Francis
2021-04-24 17:14   ` Richard Henderson [this message]
2021-04-24 17:14     ` Richard Henderson
2021-04-25 22:58     ` Alistair Francis
2021-04-25 22:58       ` Alistair Francis
2021-04-25 22:58 ` [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-25 22:58   ` Alistair Francis

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