[RFC 3/3] zImage: Exception vector support

* [RFC 3/3] zImage: Exception vector support
@ 2007-02-18  1:17 Geoff Levand
  2007-02-18  1:40 ` Josh Boyer
                   ` (2 more replies)
  0 siblings, 3 replies; 19+ messages in thread
From: Geoff Levand @ 2007-02-18  1:17 UTC (permalink / raw)
  To: linuxppc-dev

Add SMP exception vector support to the powerpc zImage bootwrapper.  For
platforms which have entry points in the vector table.  This implements
SMP entry via the system reset vector.

Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>

---
 arch/powerpc/boot/head.S       |   96 +++++++++++++++++++++++++++++++++++++++++
 arch/powerpc/boot/zImage.lds.S |    2 
 2 files changed, 98 insertions(+)

--- /dev/null
+++ ps3-linux-dev/arch/powerpc/boot/head.S
@@ -0,0 +1,96 @@
+/*
+ *  zImage exception vector entry.
+ *
+ *  Copyright (C) 2007 Sony Computer Entertainment Inc.
+ *  Copyright 2007 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "ppc_asm.h"
+
+/*
+ * __system_reset_entry - For platforms entering at the reset vector.
+ *
+ * __system_reset_entry runs the bootwrapper code on cpu 0 to prepare the
+ * wrapped kernel image.  Cpu 0 then enters the kernel at the end of the
+ * bootwrapper code.  .secondary_start sends secondary cpus to
+ * smp_secondary_hold() to wait until the bootwrapper code is finished
+ * running.  When signled, secondary cpus enter the kernel directly from
+ * smp_secondary_hold().
+ *
+ * This implementation supports only one secondary cpu.
+ *
+ * For the PS3 first stage entry the MMU is off and the bootwrapper image
+ * has been loaded to lpar address zero.  The bootwrapper is entered at
+ * 0x100 (system reset) by both proceesor threads.
+ */
+
+	.section .vectors,"ax"
+	. = 0x100
+	.globl __system_reset_entry
+__system_reset_entry:
+
+	/* switch to 32-bit mode */
+
+	mfmsr	r9
+	clrldi	r9,r9,1
+	mtmsrd	r9
+	nop
+
+	/* test thread number and branch */
+
+	mfspr	r3, 0x88
+	cntlzw.	r3, r3
+	beq	__primary_start
+
+__secondary_start:
+
+	/* setup secondary's stack */
+
+	lis	r1, __wrapper_stack_1@ha
+	addi	r1, r1, __wrapper_stack_1@l
+	subi	r1, r1, 16
+
+	xor	r4, r4, r4
+	xor	r5, r5, r5
+	b	smp_secondary_hold
+
+__primary_start:
+
+	/* setup primary's stack */
+
+	lis	r1, __wrapper_stack_0@ha
+	addi	r1, r1, __wrapper_stack_0@l
+	subi	r1, r1, 16
+
+	xor	r3, r3, r3
+	xor	r4, r4, r4
+	xor	r5, r5, r5
+	b	_zimage_start
+
+	.section .bss
+	.align 16;
+	. = . + 4096
+__wrapper_stack_0:
+
+/*
+ * The bss is cleared in crt0, so put a tiny stack in the data
+ * section for the secondary cpu.
+ */
+
+	.section .data
+	.align 16;
+	. = . + 128
+__wrapper_stack_1:
--- ps3-linux-dev.orig/arch/powerpc/boot/zImage.lds.S
+++ ps3-linux-dev/arch/powerpc/boot/zImage.lds.S
@@ -2,6 +2,8 @@ OUTPUT_ARCH(powerpc:common)
 ENTRY(_zimage_start)
 SECTIONS
 {
+  .vectors 0 : { *(.vectors) }
+
   . = (4*1024*1024);
   _start = .;
   .text      :

^ permalink raw reply	[flat|nested] 19+ messages in thread