From: Ding Tianhong <dingtianhong@huawei.com> To: "Raj, Ashok" <ashok.raj@intel.com> Cc: <leedom@chelsio.com>, <bhelgaas@google.com>, <helgaas@kernel.org>, <werner@chelsio.com>, <ganeshgr@chelsio.com>, <asit.k.mallick@intel.com>, <patrick.j.cramer@intel.com>, <Suravee.Suthikulpanit@amd.com>, <Bob.Shaw@amd.com>, <l.stach@pengutronix.de>, <amira@mellanox.com>, <gabriele.paoloni@huawei.com>, <David.Laight@aculab.com>, <jeffrey.t.kirsher@intel.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>, <mark.rutland@arm.com>, <robin.murphy@arm.com>, <davem@davemloft.net>, <alexander.duyck@gmail.com>, <linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>, <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com> Subject: Re: [PATCH v7 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Thu, 3 Aug 2017 18:20:28 +0800 [thread overview] Message-ID: <4743d44a-f871-69b6-401c-39e5d567d995@huawei.com> (raw) In-Reply-To: <20170803085504.GC4883@otc-nc-03> On 2017/8/3 16:55, Raj, Ashok wrote: > Hi Ding > > Not sure if V7 is the last version. > > can you consider rewording this just to make it a little bit more > readable? My suggestion below, feel free to use/modify > > Otherwise its all good and you can add my Ack. > > Acked-by: Ashok Raj <ashok.raj@intel.com> > > On Thu, Jul 13, 2017 at 10:21:30PM +0800, Ding Tianhong wrote: >> From: Casey Leedom <leedom@chelsio.com> > Thanks, Ashok. :) Regards Ding > >> >> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed >> Ordering Attribute should not be used on Transaction Layer Packets destined >> for the PCIe End Node so flagged. Initially flagged this way are Intel >> E5-26xx Root Complex Ports which suffer from a Flow Control Credit >> Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which >> don't obey PCIe 3.0 ordering rules which can lead to Data Corruption. > > The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that > Relaxed Ordering (RO) attribute should not be used for Transaction Layer > Packets (TLP) targetted towards these affected root complexes. Current list > of affected parts include Intel E5-26xx root complex which suffers from > flow control credits that result in performance issues. On these affected > parts RO can still be used for peer-2-peer traffic. AMD A1100 ARM ("SEATTLE") > Root complexes don't obey PCIe 3.0 ordering rules, hence could lead to > data-corruption. >> >> Signed-off-by: Casey Leedom <leedom@chelsio.com> >> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >> --- >> drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ >> include/linux/pci.h | 2 ++ >> 2 files changed, 40 insertions(+) >> >> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >> index 6967c6b..1e1cdbe 100644 >> --- a/drivers/pci/quirks.c >> +++ b/drivers/pci/quirks.c >> @@ -4016,6 +4016,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) >> quirk_tw686x_class); >> >> /* >> + * Some devices have problems with Transaction Layer Packets with the Relaxed >> + * Ordering Attribute set. Such devices should mark themselves and other >> + * Device Drivers should check before sending TLPs with RO set. >> + */ >> +static void quirk_relaxedordering_disable(struct pci_dev *dev) >> +{ >> + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; >> +} >> + >> +/* >> + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can >> + * cause performance problems with Upstream Transaction Layer Packets with >> + * Relaxed Ordering set. >> + */ >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> + >> +/* >> + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex >> + * where Upstream Transaction Layer Packets with the Relaxed Ordering >> + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering >> + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules >> + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 >> + * November 10, 2010). As a result, on this platform we can't use Relaxed >> + * Ordering for Upstream TLPs. >> + */ >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> + >> +/* >> * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same >> * values for the Attribute as were supplied in the header of the >> * corresponding Request, except as explicitly allowed when IDO is used." >> diff --git a/include/linux/pci.h b/include/linux/pci.h >> index 4869e66..412ec1c 100644 >> --- a/include/linux/pci.h >> +++ b/include/linux/pci.h >> @@ -188,6 +188,8 @@ enum pci_dev_flags { >> * the direct_complete optimization. >> */ >> PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), >> + /* Don't use Relaxed Ordering for TLPs directed at this device */ >> + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), >> }; >> >> enum pci_irq_reroute_variant { >> -- >> 1.8.3.1 >> >> > > . >
WARNING: multiple messages have this Message-ID (diff)
From: dingtianhong@huawei.com (Ding Tianhong) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Thu, 3 Aug 2017 18:20:28 +0800 [thread overview] Message-ID: <4743d44a-f871-69b6-401c-39e5d567d995@huawei.com> (raw) In-Reply-To: <20170803085504.GC4883@otc-nc-03> On 2017/8/3 16:55, Raj, Ashok wrote: > Hi Ding > > Not sure if V7 is the last version. > > can you consider rewording this just to make it a little bit more > readable? My suggestion below, feel free to use/modify > > Otherwise its all good and you can add my Ack. > > Acked-by: Ashok Raj <ashok.raj@intel.com> > > On Thu, Jul 13, 2017 at 10:21:30PM +0800, Ding Tianhong wrote: >> From: Casey Leedom <leedom@chelsio.com> > Thanks, Ashok. :) Regards Ding > >> >> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed >> Ordering Attribute should not be used on Transaction Layer Packets destined >> for the PCIe End Node so flagged. Initially flagged this way are Intel >> E5-26xx Root Complex Ports which suffer from a Flow Control Credit >> Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which >> don't obey PCIe 3.0 ordering rules which can lead to Data Corruption. > > The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that > Relaxed Ordering (RO) attribute should not be used for Transaction Layer > Packets (TLP) targetted towards these affected root complexes. Current list > of affected parts include Intel E5-26xx root complex which suffers from > flow control credits that result in performance issues. On these affected > parts RO can still be used for peer-2-peer traffic. AMD A1100 ARM ("SEATTLE") > Root complexes don't obey PCIe 3.0 ordering rules, hence could lead to > data-corruption. >> >> Signed-off-by: Casey Leedom <leedom@chelsio.com> >> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> >> --- >> drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ >> include/linux/pci.h | 2 ++ >> 2 files changed, 40 insertions(+) >> >> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >> index 6967c6b..1e1cdbe 100644 >> --- a/drivers/pci/quirks.c >> +++ b/drivers/pci/quirks.c >> @@ -4016,6 +4016,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) >> quirk_tw686x_class); >> >> /* >> + * Some devices have problems with Transaction Layer Packets with the Relaxed >> + * Ordering Attribute set. Such devices should mark themselves and other >> + * Device Drivers should check before sending TLPs with RO set. >> + */ >> +static void quirk_relaxedordering_disable(struct pci_dev *dev) >> +{ >> + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; >> +} >> + >> +/* >> + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can >> + * cause performance problems with Upstream Transaction Layer Packets with >> + * Relaxed Ordering set. >> + */ >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> + >> +/* >> + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex >> + * where Upstream Transaction Layer Packets with the Relaxed Ordering >> + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering >> + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules >> + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 >> + * November 10, 2010). As a result, on this platform we can't use Relaxed >> + * Ordering for Upstream TLPs. >> + */ >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, >> + quirk_relaxedordering_disable); >> + >> +/* >> * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same >> * values for the Attribute as were supplied in the header of the >> * corresponding Request, except as explicitly allowed when IDO is used." >> diff --git a/include/linux/pci.h b/include/linux/pci.h >> index 4869e66..412ec1c 100644 >> --- a/include/linux/pci.h >> +++ b/include/linux/pci.h >> @@ -188,6 +188,8 @@ enum pci_dev_flags { >> * the direct_complete optimization. >> */ >> PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), >> + /* Don't use Relaxed Ordering for TLPs directed at this device */ >> + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), >> }; >> >> enum pci_irq_reroute_variant { >> -- >> 1.8.3.1 >> >> > > . >
next prev parent reply other threads:[~2017-08-03 10:26 UTC|newest] Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-13 14:21 [PATCH v7 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-07-13 14:21 ` [PATCH v7 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-08-03 8:55 ` Raj, Ashok 2017-08-03 8:55 ` Raj, Ashok 2017-08-03 10:20 ` Ding Tianhong [this message] 2017-08-03 10:20 ` Ding Tianhong 2017-07-13 14:21 ` [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-07-13 21:09 ` Sinan Kaya 2017-07-13 21:09 ` Sinan Kaya 2017-07-14 1:26 ` Ding Tianhong 2017-07-14 1:26 ` Ding Tianhong 2017-07-14 13:54 ` Sinan Kaya 2017-07-14 13:54 ` Sinan Kaya 2017-07-22 4:19 ` Ding Tianhong 2017-07-22 4:19 ` Ding Tianhong 2017-07-24 15:05 ` Alex Williamson 2017-07-24 15:05 ` Alex Williamson 2017-07-26 18:26 ` Casey Leedom 2017-07-26 18:26 ` Casey Leedom 2017-07-26 18:26 ` Casey Leedom 2017-07-26 18:26 ` Casey Leedom [not found] ` <CAKgT0UeAad6WArvrE71MFJywDs1wOnCF-iJRnbNLrL+knqhXeA@mail.gmail.com> [not found] ` <CAKgT0Uf5hdXUXja_jUB6_kBg6pyX8zXuOMOGzCVNgeBFMUsWqQ@mail.gmail.com> 2017-07-26 18:44 ` Alexander Duyck 2017-07-26 19:05 ` Casey Leedom 2017-07-26 19:05 ` Casey Leedom 2017-07-26 19:05 ` Casey Leedom 2017-07-26 19:05 ` Casey Leedom 2017-07-27 1:01 ` Ding Tianhong 2017-07-27 1:01 ` Ding Tianhong 2017-07-27 1:01 ` Ding Tianhong 2017-07-27 1:01 ` Ding Tianhong 2017-07-27 17:44 ` Casey Leedom 2017-07-27 17:44 ` Casey Leedom 2017-07-27 17:44 ` Casey Leedom 2017-07-27 17:44 ` Casey Leedom 2017-07-27 18:42 ` Raj, Ashok 2017-07-27 18:42 ` Raj, Ashok 2017-07-27 18:42 ` Raj, Ashok 2017-07-27 18:42 ` Raj, Ashok 2017-07-28 2:57 ` Ding Tianhong 2017-07-28 2:57 ` Ding Tianhong 2017-07-28 2:57 ` Ding Tianhong 2017-07-28 2:57 ` Ding Tianhong 2017-07-28 2:48 ` Ding Tianhong 2017-07-28 2:48 ` Ding Tianhong 2017-07-28 2:48 ` Ding Tianhong 2017-07-28 2:48 ` Ding Tianhong 2017-07-27 1:08 ` Ding Tianhong 2017-07-27 1:08 ` Ding Tianhong 2017-07-27 1:08 ` Ding Tianhong 2017-07-27 1:08 ` Ding Tianhong 2017-07-27 17:49 ` Alexander Duyck 2017-07-27 17:49 ` Alexander Duyck 2017-07-27 17:49 ` Alexander Duyck 2017-07-27 17:49 ` Alexander Duyck 2017-07-28 3:00 ` Ding Tianhong 2017-07-28 3:00 ` Ding Tianhong 2017-07-28 3:00 ` Ding Tianhong 2017-07-28 3:00 ` Ding Tianhong 2017-08-02 17:53 ` Casey Leedom 2017-08-02 17:53 ` Casey Leedom 2017-08-02 17:53 ` Casey Leedom 2017-08-02 17:53 ` Casey Leedom 2017-08-03 8:31 ` Raj, Ashok 2017-08-03 8:31 ` Raj, Ashok 2017-08-03 8:31 ` Raj, Ashok 2017-08-03 8:31 ` Raj, Ashok 2017-08-04 20:20 ` Casey Leedom 2017-08-04 20:20 ` Casey Leedom 2017-08-04 20:20 ` Casey Leedom 2017-08-04 20:20 ` Casey Leedom 2017-08-04 20:21 ` Raj, Ashok 2017-08-04 20:21 ` Raj, Ashok 2017-08-04 20:21 ` Raj, Ashok 2017-08-04 20:21 ` Raj, Ashok 2017-08-04 20:48 ` Casey Leedom 2017-08-04 20:48 ` Casey Leedom 2017-08-04 20:48 ` Casey Leedom 2017-08-04 20:48 ` Casey Leedom 2017-08-07 9:04 ` David Laight 2017-08-07 9:04 ` David Laight 2017-08-07 9:04 ` David Laight 2017-08-07 9:04 ` David Laight 2017-08-03 9:13 ` Raj, Ashok 2017-08-03 9:13 ` Raj, Ashok 2017-08-03 10:22 ` Ding Tianhong 2017-08-03 10:22 ` Ding Tianhong 2017-07-13 14:21 ` [PATCH v7 3/3] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-07-13 14:21 ` Ding Tianhong 2017-07-13 18:14 ` Alexander Duyck 2017-07-13 18:14 ` Alexander Duyck 2017-07-13 18:14 ` Alexander Duyck 2017-07-13 18:14 ` Alexander Duyck 2017-07-13 18:17 ` Alexander Duyck 2017-07-13 18:17 ` Alexander Duyck 2017-07-13 18:17 ` Alexander Duyck 2017-07-13 18:17 ` Alexander Duyck 2017-07-13 18:44 ` Casey Leedom 2017-07-14 10:23 ` Ding Tianhong 2017-07-14 10:23 ` Ding Tianhong 2017-07-14 10:23 ` Ding Tianhong 2017-07-14 10:23 ` Ding Tianhong 2017-07-14 17:50 ` Casey Leedom 2017-07-14 17:50 ` Casey Leedom 2017-07-14 17:50 ` Casey Leedom 2017-07-14 17:50 ` Casey Leedom 2017-07-14 0:00 ` Casey Leedom 2017-07-14 0:00 ` Casey Leedom 2017-07-14 0:00 ` Casey Leedom 2017-07-14 0:00 ` Casey Leedom
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