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* [PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
@ 2022-05-17  2:19 Weiwei Li
  2022-05-17  2:19 ` [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default Weiwei Li
  0 siblings, 1 reply; 4+ messages in thread
From: Weiwei Li @ 2022-05-17  2:19 UTC (permalink / raw)
  To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
  Cc: wangjunqiang, lazyparser, Weiwei Li

 - setting ext_g will implicitly set ext_i

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee215..b12f69c584 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     if (env->misa_ext == 0) {
         uint32_t ext = 0;
 
+        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+                                cpu->cfg.ext_a & cpu->cfg.ext_f &
+                                cpu->cfg.ext_d)) {
+            warn_report("Setting G will also set IMAFD");
+            cpu->cfg.ext_i = true;
+            cpu->cfg.ext_m = true;
+            cpu->cfg.ext_a = true;
+            cpu->cfg.ext_f = true;
+            cpu->cfg.ext_d = true;
+        }
+
+
         /* Do some ISA extension error checking */
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
@@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
-        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
-                                cpu->cfg.ext_a & cpu->cfg.ext_f &
-                                cpu->cfg.ext_d)) {
-            warn_report("Setting G will also set IMAFD");
-            cpu->cfg.ext_i = true;
-            cpu->cfg.ext_m = true;
-            cpu->cfg.ext_a = true;
-            cpu->cfg.ext_f = true;
-            cpu->cfg.ext_d = true;
-        }
-
         if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
             cpu->cfg.ext_zhinxmin) {
             cpu->cfg.ext_zfinx = true;
-- 
2.17.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
  2022-05-17  2:19 [PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
@ 2022-05-17  2:19 ` Weiwei Li
  2022-05-17  4:16   ` Alistair Francis
  0 siblings, 1 reply; 4+ messages in thread
From: Weiwei Li @ 2022-05-17  2:19 UTC (permalink / raw)
  To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
  Cc: wangjunqiang, lazyparser, Weiwei Li

 - properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b12f69c584..e205be34e9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -176,6 +176,10 @@ static void rv64_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv64_sifive_e_cpu_init(Object *obj)
@@ -184,6 +188,10 @@ static void rv64_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv128_base_cpu_init(Object *obj)
@@ -211,6 +219,10 @@ static void rv32_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_sifive_e_cpu_init(Object *obj)
@@ -219,6 +231,10 @@ static void rv32_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_ibex_cpu_init(Object *obj)
@@ -228,6 +244,10 @@ static void rv32_ibex_cpu_init(Object *obj)
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -237,6 +257,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 #endif
 
-- 
2.17.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
  2022-05-17  2:19 ` [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default Weiwei Li
@ 2022-05-17  4:16   ` Alistair Francis
  2022-05-17  4:49     ` Weiwei Li
  0 siblings, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2022-05-17  4:16 UTC (permalink / raw)
  To: Weiwei Li
  Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
	qemu-devel@nongnu.org Developers, wangjunqiang,
	Wei Wu (吴伟)

On Tue, May 17, 2022 at 12:21 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>  - properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/cpu.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b12f69c584..e205be34e9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -176,6 +176,10 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);

This is very error prone. I think we should either disable the
extensions by default, then enable them for the rv32/rv64 CPUs, or
instead do something like this:
https://patchew.org/QEMU/20220517041100.93045-1-alistair.francis@opensource.wdc.com/

Alistair

>  }
>
>  static void rv64_sifive_e_cpu_init(Object *obj)
> @@ -184,6 +188,10 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>  }
>
>  static void rv128_base_cpu_init(Object *obj)
> @@ -211,6 +219,10 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>  }
>
>  static void rv32_sifive_e_cpu_init(Object *obj)
> @@ -219,6 +231,10 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>  }
>
>  static void rv32_ibex_cpu_init(Object *obj)
> @@ -228,6 +244,10 @@ static void rv32_ibex_cpu_init(Object *obj)
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>      qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>  }
>
>  static void rv32_imafcu_nommu_cpu_init(Object *obj)
> @@ -237,6 +257,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>      set_priv_version(env, PRIV_VERSION_1_10_0);
>      set_resetvec(env, DEFAULT_RSTVEC);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>  }
>  #endif
>
> --
> 2.17.1
>
>


^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
  2022-05-17  4:16   ` Alistair Francis
@ 2022-05-17  4:49     ` Weiwei Li
  0 siblings, 0 replies; 4+ messages in thread
From: Weiwei Li @ 2022-05-17  4:49 UTC (permalink / raw)
  To: Alistair Francis
  Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
	qemu-devel@nongnu.org Developers, wangjunqiang,
	Wei Wu (吴伟)


在 2022/5/17 下午12:16, Alistair Francis 写道:
> On Tue, May 17, 2022 at 12:21 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>>   - properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/cpu.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index b12f69c584..e205be34e9 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -176,6 +176,10 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>>       CPURISCVState *env = &RISCV_CPU(obj)->env;
>>       set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
> This is very error prone. I think we should either disable the
> extensions by default, then enable them for the rv32/rv64 CPUs, or
> instead do something like this:
> https://patchew.org/QEMU/20220517041100.93045-1-alistair.francis@opensource.wdc.com/
>
> Alistair

OK, I think the way from your patchset is better.

Regards,

Weiwei Li

>>   }
>>
>>   static void rv64_sifive_e_cpu_init(Object *obj)
>> @@ -184,6 +188,10 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>>       set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>>       qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>>   }
>>
>>   static void rv128_base_cpu_init(Object *obj)
>> @@ -211,6 +219,10 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>>       CPURISCVState *env = &RISCV_CPU(obj)->env;
>>       set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>>   }
>>
>>   static void rv32_sifive_e_cpu_init(Object *obj)
>> @@ -219,6 +231,10 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>>       set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>>       qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>>   }
>>
>>   static void rv32_ibex_cpu_init(Object *obj)
>> @@ -228,6 +244,10 @@ static void rv32_ibex_cpu_init(Object *obj)
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>>       qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>>       qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>>   }
>>
>>   static void rv32_imafcu_nommu_cpu_init(Object *obj)
>> @@ -237,6 +257,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>>       set_priv_version(env, PRIV_VERSION_1_10_0);
>>       set_resetvec(env, DEFAULT_RSTVEC);
>>       qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zba", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
>> +    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
>>   }
>>   #endif
>>
>> --
>> 2.17.1
>>
>>



^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-05-17  4:50 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-17  2:19 [PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
2022-05-17  2:19 ` [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default Weiwei Li
2022-05-17  4:16   ` Alistair Francis
2022-05-17  4:49     ` Weiwei Li

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