* [PATCH v2 RESEND 0/2] ARM: optimize copy_page() for systems with cache line != 32 @ 2009-09-12 15:59 Kirill A. Shutemov 2009-09-12 15:59 ` [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Kirill A. Shutemov 0 siblings, 1 reply; 10+ messages in thread From: Kirill A. Shutemov @ 2009-09-12 15:59 UTC (permalink / raw) To: linux-arm-kernel I can't find this changes in any git tree, so resend. Russell, please add these patches into your patch queue for 2.6.32. Thanks. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 15:59 [PATCH v2 RESEND 0/2] ARM: optimize copy_page() for systems with cache line != 32 Kirill A. Shutemov @ 2009-09-12 15:59 ` Kirill A. Shutemov 2009-09-12 13:36 ` Sergei Shtylyov 2009-09-12 15:59 ` [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line Kirill A. Shutemov 0 siblings, 2 replies; 10+ messages in thread From: Kirill A. Shutemov @ 2009-09-12 15:59 UTC (permalink / raw) To: linux-arm-kernel Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> --- arch/arm/include/asm/cache.h | 2 +- arch/arm/mm/Kconfig | 5 +++++ 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index feaa75f..2ee7743 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -4,7 +4,7 @@ #ifndef __ASMARM_CACHE_H #define __ASMARM_CACHE_H -#define L1_CACHE_SHIFT 5 +#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 83c025e..3c37d4c 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -771,3 +771,8 @@ config CACHE_XSC3L2 select OUTER_CACHE help This option enables the L2 cache on XScale3. + +config ARM_L1_CACHE_SHIFT + int + default 6 if ARCH_OMAP3 + default 5 -- 1.6.4.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 15:59 ` [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Kirill A. Shutemov @ 2009-09-12 13:36 ` Sergei Shtylyov 2009-09-12 14:12 ` Kirill A. Shutemov 2009-09-12 15:59 ` [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line Kirill A. Shutemov 1 sibling, 1 reply; 10+ messages in thread From: Sergei Shtylyov @ 2009-09-12 13:36 UTC (permalink / raw) To: linux-arm-kernel Hello. Kirill A. Shutemov wrote: > Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. > It's not true at least for CPUs based on Cortex-A8. > > List of CPUs with cache line size != 32 should be expanded later. > > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> > --- > arch/arm/include/asm/cache.h | 2 +- > arch/arm/mm/Kconfig | 5 +++++ > 2 files changed, 6 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h > index feaa75f..2ee7743 100644 > --- a/arch/arm/include/asm/cache.h > +++ b/arch/arm/include/asm/cache.h > @@ -4,7 +4,7 @@ > #ifndef __ASMARM_CACHE_H > #define __ASMARM_CACHE_H > > -#define L1_CACHE_SHIFT 5 > +#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT) > Parens not needed. WBR, Sergei ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 13:36 ` Sergei Shtylyov @ 2009-09-12 14:12 ` Kirill A. Shutemov 2009-09-12 14:21 ` Sergei Shtylyov 0 siblings, 1 reply; 10+ messages in thread From: Kirill A. Shutemov @ 2009-09-12 14:12 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 12, 2009 at 4:36 PM, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote: > Hello. > > Kirill A. Shutemov wrote: > >> Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. >> It's not true at least for CPUs based on Cortex-A8. >> >> List of CPUs with cache line size != 32 should be expanded later. >> >> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> >> --- >> ?arch/arm/include/asm/cache.h | ? ?2 +- >> ?arch/arm/mm/Kconfig ? ? ? ? ?| ? ?5 +++++ >> ?2 files changed, 6 insertions(+), 1 deletions(-) >> >> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h >> index feaa75f..2ee7743 100644 >> --- a/arch/arm/include/asm/cache.h >> +++ b/arch/arm/include/asm/cache.h >> @@ -4,7 +4,7 @@ >> ?#ifndef __ASMARM_CACHE_H >> ?#define __ASMARM_CACHE_H >> ?-#define L1_CACHE_SHIFT ? ? ? ? 5 >> +#define L1_CACHE_SHIFT ? ? ? ? (CONFIG_ARM_L1_CACHE_SHIFT) >> > > ?Parens not needed. You can write anything in your .config (like 2+3), so I think parens is needed. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 14:12 ` Kirill A. Shutemov @ 2009-09-12 14:21 ` Sergei Shtylyov 2009-09-12 14:38 ` Kirill A. Shutemov 0 siblings, 1 reply; 10+ messages in thread From: Sergei Shtylyov @ 2009-09-12 14:21 UTC (permalink / raw) To: linux-arm-kernel Hello. Kirill A. Shutemov wrote: >>> Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. >>> It's not true at least for CPUs based on Cortex-A8. >>> >>> List of CPUs with cache line size != 32 should be expanded later. >>> >>> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> >>> --- >>> arch/arm/include/asm/cache.h | 2 +- >>> arch/arm/mm/Kconfig | 5 +++++ >>> 2 files changed, 6 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h >>> index feaa75f..2ee7743 100644 >>> --- a/arch/arm/include/asm/cache.h >>> +++ b/arch/arm/include/asm/cache.h >>> @@ -4,7 +4,7 @@ >>> #ifndef __ASMARM_CACHE_H >>> #define __ASMARM_CACHE_H >>> -#define L1_CACHE_SHIFT 5 >>> +#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT) >>> >>> >> Parens not needed. >> > > You can write anything in your .config (like 2+3), so I think parens is needed. > You can -- but that won't be an integer option. WBR, Sergei ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 14:21 ` Sergei Shtylyov @ 2009-09-12 14:38 ` Kirill A. Shutemov 2009-09-12 14:53 ` Russell King - ARM Linux 0 siblings, 1 reply; 10+ messages in thread From: Kirill A. Shutemov @ 2009-09-12 14:38 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 12, 2009 at 5:21 PM, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote: > Hello. > > Kirill A. Shutemov wrote: > >>>> Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. >>>> It's not true at least for CPUs based on Cortex-A8. >>>> >>>> List of CPUs with cache line size != 32 should be expanded later. >>>> >>>> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> >>>> --- >>>> ?arch/arm/include/asm/cache.h | ? ?2 +- >>>> ?arch/arm/mm/Kconfig ? ? ? ? ?| ? ?5 +++++ >>>> ?2 files changed, 6 insertions(+), 1 deletions(-) >>>> >>>> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h >>>> index feaa75f..2ee7743 100644 >>>> --- a/arch/arm/include/asm/cache.h >>>> +++ b/arch/arm/include/asm/cache.h >>>> @@ -4,7 +4,7 @@ >>>> ?#ifndef __ASMARM_CACHE_H >>>> ?#define __ASMARM_CACHE_H >>>> ?-#define L1_CACHE_SHIFT ? ? ? ? 5 >>>> +#define L1_CACHE_SHIFT ? ? ? ? (CONFIG_ARM_L1_CACHE_SHIFT) >>>> >>>> >>> >>> ?Parens not needed. >>> >> >> You can write anything in your .config (like 2+3), so I think parens is >> needed. >> > > ?You can -- but that won't be an integer option. But kernel will be still compilable, but broken. I think parens for defines from .config is a good practice. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 2009-09-12 14:38 ` Kirill A. Shutemov @ 2009-09-12 14:53 ` Russell King - ARM Linux 0 siblings, 0 replies; 10+ messages in thread From: Russell King - ARM Linux @ 2009-09-12 14:53 UTC (permalink / raw) To: linux-arm-kernel On Sat, Sep 12, 2009 at 05:38:31PM +0300, Kirill A. Shutemov wrote: > On Sat, Sep 12, 2009 at 5:21 PM, Sergei Shtylyov > <sshtylyov@ru.mvista.com> wrote: > > Hello. > > > > Kirill A. Shutemov wrote: > >> You can write anything in your .config (like 2+3), so I think parens is > >> needed. > >> > > > > ?You can -- but that won't be an integer option. > > But kernel will be still compilable, but broken. > > I think parens for defines from .config is a good practice. However, defines are not taken from .config. The .config file is processed by the kernel configurator, which writes out the autoconf.h header. It does this by re-evaluating the contents of .config against all the Kconfig files. It does not merely copy .config to autoconf.h. In fact, if you try to write '2+3' into your .config, Kconfig will reject it. Eg: .config:210:warning: symbol value '127+1' invalid for OMAP_32K_TIMER_HZ and then it asks you to provide a valid value instead. So yes, as pointed out, the parens are not required since Kconfig will ensure that the symbol is a simple integer. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line 2009-09-12 15:59 ` [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Kirill A. Shutemov 2009-09-12 13:36 ` Sergei Shtylyov @ 2009-09-12 15:59 ` Kirill A. Shutemov 2009-09-12 13:48 ` Uwe Kleine-König 1 sibling, 1 reply; 10+ messages in thread From: Kirill A. Shutemov @ 2009-09-12 15:59 UTC (permalink / raw) To: linux-arm-kernel Optimized version of copy_page() was written with assumption that cache line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes. This patch tries to generalize copy_page() to work with any cache line size if cache line size is multiple of 16 and page size is multiple of two cache line size. After this optimization we've got ~25% speedup on OMAP3(tested in userspace). There is test for kernelspace which trigger copy-on-write after fork(): #include <stdlib.h> #include <string.h> #include <unistd.h> #define BUF_SIZE (10000*4096) #define NFORK 200 int main(int argc, char **argv) { char *buf = malloc(BUF_SIZE); int i; memset(buf, 0, BUF_SIZE); for(i = 0; i < NFORK; i++) { if (fork()) { wait(NULL); } else { int j; for(j = 0; j < BUF_SIZE; j+= 4096) buf[j] = (j & 0xFF) + 1; break; } } free(buf); return 0; } Before optimization this test takes ~66 seconds, after optimization takes ~56 seconds. V2: - include <asm/cahce.h> - remove unnecessary parens and fix style Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> --- arch/arm/lib/copy_page.S | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S index 6ae04db..6ee2f67 100644 --- a/arch/arm/lib/copy_page.S +++ b/arch/arm/lib/copy_page.S @@ -12,8 +12,9 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/cache.h> -#define COPY_COUNT (PAGE_SZ/64 PLD( -1 )) +#define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 )) .text .align 5 @@ -26,17 +27,16 @@ ENTRY(copy_page) stmfd sp!, {r4, lr} @ 2 PLD( pld [r1, #0] ) - PLD( pld [r1, #32] ) + PLD( pld [r1, #L1_CACHE_BYTES] ) mov r2, #COPY_COUNT @ 1 ldmia r1!, {r3, r4, ip, lr} @ 4+1 -1: PLD( pld [r1, #64] ) - PLD( pld [r1, #96] ) -2: stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 +1: PLD( pld [r1, #2 * L1_CACHE_BYTES]) + PLD( pld [r1, #3 * L1_CACHE_BYTES]) +2: + .rept (2 * L1_CACHE_BYTES / 16 - 1) stmia r0!, {r3, r4, ip, lr} @ 4 ldmia r1!, {r3, r4, ip, lr} @ 4 + .endr subs r2, r2, #1 @ 1 stmia r0!, {r3, r4, ip, lr} @ 4 ldmgtia r1!, {r3, r4, ip, lr} @ 4 -- 1.6.4.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line 2009-09-12 15:59 ` [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line Kirill A. Shutemov @ 2009-09-12 13:48 ` Uwe Kleine-König 2009-09-12 14:04 ` Sergei Shtylyov 0 siblings, 1 reply; 10+ messages in thread From: Uwe Kleine-König @ 2009-09-12 13:48 UTC (permalink / raw) To: linux-arm-kernel Hello, Just two minor nitpicks: > V2: > - include <asm/cahce.h> s/cahce/cache/ > - remove unnecessary parens and fix style s/parens/parenthesis/ Note I didn't look at the patch. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line 2009-09-12 13:48 ` Uwe Kleine-König @ 2009-09-12 14:04 ` Sergei Shtylyov 0 siblings, 0 replies; 10+ messages in thread From: Sergei Shtylyov @ 2009-09-12 14:04 UTC (permalink / raw) To: linux-arm-kernel Hello. Uwe Kleine-K?nig wrote: > s/cahce/cache/ > >> - remove unnecessary parens and fix style >> > s/parens/parenthesis/ > Isn't "parens" a common contraction for "parentheses"? WBR, Sergei ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2009-09-12 15:59 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2009-09-12 15:59 [PATCH v2 RESEND 0/2] ARM: optimize copy_page() for systems with cache line != 32 Kirill A. Shutemov 2009-09-12 15:59 ` [PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Kirill A. Shutemov 2009-09-12 13:36 ` Sergei Shtylyov 2009-09-12 14:12 ` Kirill A. Shutemov 2009-09-12 14:21 ` Sergei Shtylyov 2009-09-12 14:38 ` Kirill A. Shutemov 2009-09-12 14:53 ` Russell King - ARM Linux 2009-09-12 15:59 ` [PATCH v2 RESEND 2/2] ARM: copy_page.S: take into account the size of the cache line Kirill A. Shutemov 2009-09-12 13:48 ` Uwe Kleine-König 2009-09-12 14:04 ` Sergei Shtylyov
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