* [U-Boot] Adding support for MX35
@ 2011-01-20 8:46 Stefano Babic
2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic
` (11 more replies)
0 siblings, 12 replies; 46+ messages in thread
From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw)
To: u-boot
Patchset V2 contain patches for SPI sent previously independently to ML
and additional patches for I2C.
^ permalink raw reply [flat|nested] 46+ messages in thread* [U-Boot] [PATCH V2 01/11] Add support for MX35 processor 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:25 ` Wolfgang Denk 2011-01-20 17:49 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 02/11] serial_mxc: add support for Freescale's i.MX35 processor Stefano Babic ` (10 subsequent siblings) 11 siblings, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot The patch adds basic support for the Freescale's i.MX35 (arm1136 based) processor. Signed-off-by: Stefano Babic <sbabic@denx.de> --- Changes: Wolfgang Denk: - Drop __REG macros - sort lists - coding styles - iomux functions must return void - fix license headers arch/arm/cpu/arm1136/mx35/Makefile | 49 +++ arch/arm/cpu/arm1136/mx35/generic.c | 463 ++++++++++++++++++++++++++ arch/arm/cpu/arm1136/mx35/iomux.c | 116 +++++++ arch/arm/cpu/arm1136/mx35/timer.c | 120 +++++++ arch/arm/include/asm/arch-mx35/asm-offsets.h | 21 ++ arch/arm/include/asm/arch-mx35/clock.h | 45 +++ arch/arm/include/asm/arch-mx35/crm_regs.h | 270 +++++++++++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 336 +++++++++++++++++++ arch/arm/include/asm/arch-mx35/iomux.h | 303 +++++++++++++++++ arch/arm/include/asm/arch-mx35/mx35_pins.h | 355 ++++++++++++++++++++ arch/arm/include/asm/arch-mx35/sys_proto.h | 31 ++ 11 files changed, 2109 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm1136/mx35/Makefile create mode 100644 arch/arm/cpu/arm1136/mx35/generic.c create mode 100644 arch/arm/cpu/arm1136/mx35/iomux.c create mode 100644 arch/arm/cpu/arm1136/mx35/timer.c create mode 100644 arch/arm/include/asm/arch-mx35/asm-offsets.h create mode 100644 arch/arm/include/asm/arch-mx35/clock.h create mode 100644 arch/arm/include/asm/arch-mx35/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx35/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx35/iomux.h create mode 100644 arch/arm/include/asm/arch-mx35/mx35_pins.h create mode 100644 arch/arm/include/asm/arch-mx35/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile new file mode 100644 index 0000000..9b4cf76 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o +COBJS += iomux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c new file mode 100644 index 0000000..929dc95 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -0,0 +1,463 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +#define CLK_CODE_PATH(c) ((c) & 0xFF) + +#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +static int g_clk_mux_auto[8] = { + CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, + CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +}; + +static int g_clk_mux_consumer[16] = { + CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, + -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), + CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, + -1, -1, CLK_CODE(4, 2, 0), -1, +}; + +static int hsp_div_table[3][16] = { + {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, + {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, + {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +}; + +u32 get_cpu_rev(void) +{ + int reg; + struct iim_regs *iim = + (struct iim_regs *)IIM_BASE_ADDR; + reg = readl(&iim->iim_srev); + if (!reg) { + reg = readw(ROMPATCH_REV); + reg <<= 4; + } else + reg += CHIP_REV_1_0; + return 0x35000 + (reg & 0xFF); +} + +static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) +{ + int *pclk_mux; + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + } else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) + return -1; + + if (fi && fd) { + if (!CLK_CODE_PATH(*pclk_mux)) { + *fi = *fd = 1; + return CLK_CODE_ARM(*pclk_mux); + } + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + *fi = 3; + *fd = 4; + } else { + *fi = 2; + *fd = 3; + } + } + return CLK_CODE_ARM(*pclk_mux); +} + +static int get_ahb_div(u32 pdr0) +{ + int *pclk_mux; + + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + + if ((*pclk_mux) == -1) + return -1; + + return CLK_CODE_AHB(*pclk_mux); +} + +static u32 decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 get_mcu_main_clk(void) +{ + u32 arm_div = 0, fi = 0, fd = 0; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); + fi *= + decode_pll(readl(&ccm->mpctl), + CONFIG_MX35_HCLK_FREQ); + return fi / (arm_div * fd); +} + +static u32 get_ipg_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + + return freq / (get_ahb_div(pdr0) * 2); +} + +static u32 get_ipg_per_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + u32 pdr4 = readl(&ccm->pdr4); + u32 div; + if (pdr0 & MXC_CCM_PDR0_PER_SEL) { + div = (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PRDF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PODF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + } else { + div = CCM_GET_DIVIDER(pdr0, + MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; + freq /= get_ahb_div(pdr0); + } + return freq / div; +} + +u32 imx_get_uartclk(void) +{ + u32 freq; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr4 = readl(&ccm->pdr4); + + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) + freq = get_mcu_main_clk(); + else + freq = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + freq /= ((CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PRDF_MASK, + MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PODF_MASK, + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + return freq; +} + +unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +{ + u32 nfc_pdf, hsp_podf; + u32 pll, ret_val = 0, usb_prdf, usb_podf; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 reg = readl(&ccm->pdr0); + u32 reg4 = readl(&ccm->pdr4); + + reg |= 0x1; + + switch (clk) { + case CPU_CLK: + ret_val = get_mcu_main_clk(); + break; + case AHB_CLK: + ret_val = get_mcu_main_clk(); + break; + case HSP_CLK: + if (reg & CLKMODE_CONSUMER) { + hsp_podf = (reg >> 20) & 0x3; + pll = get_mcu_main_clk(); + hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; + if (hsp_podf > 0) { + ret_val = pll / hsp_podf; + } else { + puts("mismatch HSP with ARM clock setting\n"); + ret_val = 0; + } + } else { + ret_val = get_mcu_main_clk(); + } + break; + case IPG_CLK: + ret_val = get_ipg_clk();; + break; + case IPG_PER_CLK: + ret_val = get_ipg_per_clk(); + break; + case NFC_CLK: + nfc_pdf = (reg4 >> 28) & 0xF; + pll = get_mcu_main_clk(); + /* AHB/nfc_pdf */ + ret_val = pll / (nfc_pdf + 1); + break; + case USB_CLK: + usb_prdf = (reg4 >> 25) & 0x7; + usb_podf = (reg4 >> 22) & 0x7; + if (reg4 & 0x200) + pll = get_mcu_main_clk(); + else + pll = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + + ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + break; + default: + printf("Unknown clock: %d\n", clk); + break; + } + + return ret_val; +} +unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 mpdr2 = readl(&ccm->pdr2); + u32 mpdr3 = readl(&ccm->pdr3); + u32 mpdr4 = readl(&ccm->pdr4); + + switch (clk) { + case UART1_BAUD: + case UART2_BAUD: + case UART3_BAUD: + clk_sel = mpdr3 & (1 << 14); + pre_pdf = (mpdr4 >> 13) & 0x7; + pdf = (mpdr4 >> 10) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI1_BAUD: + pre_pdf = (mpdr2 >> 24) & 0x7; + pdf = mpdr2 & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI2_BAUD: + pre_pdf = (mpdr2 >> 27) & 0x7; + pdf = (mpdr2 >> 8) & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case CSI_BAUD: + clk_sel = mpdr2 & (1 << 7); + pre_pdf = (mpdr2 >> 16) & 0x7; + pdf = (mpdr2 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case MSHC_CLK: + pre_pdf = readl(&ccm->pdr1); + clk_sel = (pre_pdf & 0x80); + pdf = (pre_pdf >> 22) & 0x3F; + pre_pdf = (pre_pdf >> 28) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC1_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = mpdr3 & 0x7; + pdf = (mpdr3>>3) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC2_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 8) & 0x7; + pdf = (mpdr3 >> 11) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC3_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 16) & 0x7; + pdf = (mpdr3 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SPDIF_CLK: + clk_sel = mpdr3 & 0x400000; + pre_pdf = (mpdr3 >> 29) & 0x7; + pdf = (mpdr3 >> 23) & 0x3F; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + default: + printf("%s(): This clock: %d not supported yet\n", + __func__, clk); + break; + } + + return ret_val; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return imx_get_uartclk(); + case MXC_ESDHC_CLK: + return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_USB_CLK: + return mxc_get_main_clock(USB_CLK); + case MXC_FEC_CLK: + return get_ipg_clk(); + case MXC_CSPI_CLK: + return get_ipg_clk(); + } + return -1; +} + +#ifdef CONFIG_FEC_MXC +/* + * The MX35 has no fuse for MAC, return a NULL MAC + */ +void imx_get_mac_from_fuse(unsigned char *mac) +{ + int i; + + memset(mac, 0, 6); +} + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} +#endif + +int do_mx35_showclocks(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 cpufreq = get_mcu_main_clk(); + printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("ipg clock : %dHz\n", get_ipg_clk()); + printf("ipg per clock : %dHz\n", get_ipg_per_clk()); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + + return 0; +} + +U_BOOT_CMD( + clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, + "display clocks\n", + "" +); + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX35 at %d MHz\n", + get_mcu_main_clk() / 1000000); + /* mxc_dump_clocks(); */ + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +#if defined(CONFIG_FEC_MXC) +extern int fecmxc_initialize(bd_t *bis); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + +void reset_cpu(ulong addr) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + writew(4, &wdog->wcr); +} diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c new file mode 100644 index 0000000..f93191d --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/iomux.c @@ -0,0 +1,116 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> + +/* + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */ + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */ + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */ + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */ + IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */ + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */ + IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + writel(cfg, mux_reg); + } +} + +/* + * Release ownership for an IO pin + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in iomux_pin_name_t + * @param config the ORed value of elements defined in iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + writel(config, pad_reg); +} + +/* + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in iomux_gp_func_t + * @param en enable/disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) +{ + u32 l; + + l = readl(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + writel(l, IOMUXGPR); +} + +/* + * This function configures input path. + * + * @param input index of input select register as defined in + * iomux_input_select_t + * @param config the binary value of elements defined in + * iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c new file mode 100644 index 0000000..db1e2c9 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +int timer_init(void) +{ + int i; + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + /* setup GP Timer 1 */ + writel(GPTCR_SWR, &gpt->ctrl); + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + + writel(GPTPR_VAL, &gpt->pre); + /* Freerun Mode, PERCLK1 input */ + writel(readl(&gpt->ctrl) | + GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + writel(0, &gpt->ctrl); + /* Freerun Mode, PERCLK1 input */ + writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); +} + +inline ulong get_timer_masked(void) +{ + + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + ulong val = readl(&gpt->counter); + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* + * delay x useconds AND preserve advance timstamp value + * GPTCNT is now supposed to tick 1 by 1 us. + */ +void __udelay(unsigned long usec) +{ + ulong tmp; + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/arch/arm/include/asm/arch-mx35/asm-offsets.h b/arch/arm/include/asm/arch-mx35/asm-offsets.h new file mode 100644 index 0000000..c1dc62a --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/asm-offsets.h @@ -0,0 +1,21 @@ +/* + * needed for lowlevel_init.S + * + * These should be auto-generated + */ +/* CCM */ +#define CLKCTL_CCMR 0x00 +#define CLKCTL_PDR0 0x04 +#define CLKCTL_PDR1 0x08 +#define CLKCTL_PDR2 0x0C +#define CLKCTL_PDR3 0x10 +#define CLKCTL_PDR4 0x14 +#define CLKCTL_RCSR 0x18 +#define CLKCTL_MPCTL 0x1C +#define CLKCTL_PPCTL 0x20 +#define CLKCTL_ACMR 0x24 +#define CLKCTL_COSR 0x28 +#define CLKCTL_CGR0 0x2C +#define CLKCTL_CGR1 0x30 +#define CLKCTL_CGR2 0x34 +#define CLKCTL_CGR3 0x38 diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h new file mode 100644 index 0000000..4c0ddfd --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_USB_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h new file mode 100644 index 0000000..e903cf1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -0,0 +1,270 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +#define __CPU_ARM1136_MX35_CRM_REGS_H__ + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 21 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 +#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 +#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 15) +#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 +#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 +#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 +#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) +#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 +#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 +#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EDI0_OFFSET 16 +#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) +#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) +#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +#endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h new file mode 100644 index 0000000..e96a37d --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -0,0 +1,336 @@ +/* + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX35_H +#define __ASM_ARCH_MX35_H + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define IRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define I2C_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE_ADDR 0x43F90000 +#define UART2_BASE_ADDR 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define IOMUXC_BASE_ADDR 0x43FAC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define UART3_BASE_ADDR 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define FEC_BASE_ADDR 0x50038000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 +#define IIM_BASE_ADDR 0x53FF0000 + +#define IMX_CCM_BASE CCM_BASE_ADDR + +/* + * ROMPATCH and AVIC + */ +#define ROMPATCH_BASE_ADDR 0x60000000 +#define AVIC_BASE_ADDR 0x68000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +#define M3IF_BASE_ADDR 0xB8003000 +#define EMI_BASE_ADDR 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS5_BASE_ADDR 0xB6000000 + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_NIMASK 0x04 +#define AVIC_INTTYPEH 0x18 +#define AVIC_INTTYPEL 0x1C + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +#define L2_CACHE_DBG_CTL_REG 0xF40 + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) + +#define IIM_SREV 0x24 +#define ROMPATCH_REV 0x40 + +#define IPU_CONF IPU_CTRL_BASE_ADDR + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +#define NFC_BUF_SIZE 0x1000 +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) +#define NF_WR_PROT_REG_OFF (0 + 0x12) +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_BUF_NUM 8 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +#if 0 +enum plls { + MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL, + PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL, +}; +#endif + +enum mxc_main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 ccmr; /* Control */ + u32 pdr0; /* Post divider 0 */ + u32 pdr1; /* Post divider 1 */ + u32 pdr2; /* Post divider 2 */ + u32 pdr3; /* Post divider 3 */ + u32 pdr4; /* Post divider 4 */ + u32 rcsr; /* CCM Status */ + u32 mpctl; /* Core PLL Control */ + u32 ppctl; /* Peripheral PLL Control */ + u32 acmr; /* Audio clock mux */ + u32 cosr; /* Clock out source */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 cgr3; /* Clock Gating Control 3 */ + u32 reserved; + u32 dcvr0; /* DPTC Comparator 0 */ + u32 dcvr1; /* DPTC Comparator 0 */ + u32 dcvr2; /* DPTC Comparator 0 */ + u32 dcvr3; /* DPTC Comparator 0 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ +}; + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR + 0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) + +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern int sdhc_init(void); + +#endif +#endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h new file mode 100644 index 0000000..5c1039c --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/iomux.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_MX35_IOMUX_H__ +#define __MACH_MX35_IOMUX_H__ + +#include <asm/arch/imx-regs.h> + +/*! + * @file mach-mx35/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX35 + */ + +/*! + * various IOMUX functions + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, + MUX_TAMPER_DETECT_EN = 0x1 << 2, +} iomux_gp_func_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AMX_P5_RXCLK = 0, + MUX_IN_AMX_P5_RXFS, + MUX_IN_AMX_P6_DA, + MUX_IN_AMX_P6_DB, + MUX_IN_AMX_P6_RXCLK, + MUX_IN_AMX_P6_RXFS, + MUX_IN_AMX_P6_TXCLK, + MUX_IN_AMX_P6_TXFS, + MUX_IN_CAN1_CANRX, + MUX_IN_CAN2_CANRX, + MUX_IN_CCM_32K_MUXED, + MUX_IN_CCM_PMIC_RDY, + MUX_IN_CSPI1_SS2_B, + MUX_IN_CSPI1_SS3_B, + MUX_IN_CSPI2_CLK_IN, + MUX_IN_CSPI2_DATAREADY_B, + MUX_IN_CSPI2_MISO, + MUX_IN_CSPI2_MOSI, + MUX_IN_CSPI2_SS0_B, + MUX_IN_CSPI2_SS1_B, + MUX_IN_CSPI2_SS2_B, + MUX_IN_CSPI2_SS3_B, + MUX_IN_EMI_WEIM_DTACK_B, + MUX_IN_ESDHC1_DAT4_IN, + MUX_IN_ESDHC1_DAT5_IN, + MUX_IN_ESDHC1_DAT6_IN, + MUX_IN_ESDHC1_DAT7_IN, + MUX_IN_ESDHC3_CARD_CLK_IN, + MUX_IN_ESDHC3_CMD_IN, + MUX_IN_ESDHC3_DAT0, + MUX_IN_ESDHC3_DAT1, + MUX_IN_ESDHC3_DAT2, + MUX_IN_ESDHC3_DAT3, + MUX_IN_GPIO1_IN_0, + MUX_IN_GPIO1_IN_10, + MUX_IN_GPIO1_IN_11, + MUX_IN_GPIO1_IN_1, + MUX_IN_GPIO1_IN_20, + MUX_IN_GPIO1_IN_21, + MUX_IN_GPIO1_IN_22, + MUX_IN_GPIO1_IN_2, + MUX_IN_GPIO1_IN_3, + MUX_IN_GPIO1_IN_4, + MUX_IN_GPIO1_IN_5, + MUX_IN_GPIO1_IN_6, + MUX_IN_GPIO1_IN_7, + MUX_IN_GPIO1_IN_8, + MUX_IN_GPIO1_IN_9, + MUX_IN_GPIO2_IN_0, + MUX_IN_GPIO2_IN_10, + MUX_IN_GPIO2_IN_11, + MUX_IN_GPIO2_IN_12, + MUX_IN_GPIO2_IN_13, + MUX_IN_GPIO2_IN_14, + MUX_IN_GPIO2_IN_15, + MUX_IN_GPIO2_IN_16, + MUX_IN_GPIO2_IN_17, + MUX_IN_GPIO2_IN_18, + MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_20, + MUX_IN_GPIO2_IN_21, + MUX_IN_GPIO2_IN_22, + MUX_IN_GPIO2_IN_23, + MUX_IN_GPIO2_IN_24, + MUX_IN_GPIO2_IN_25, + MUX_IN_GPIO2_IN_26, + MUX_IN_GPIO2_IN_27, + MUX_IN_GPIO2_IN_28, + MUX_IN_GPIO2_IN_29, + MUX_IN_GPIO2_IN_2, + MUX_IN_GPIO2_IN_30, + MUX_IN_GPIO2_IN_31, + MUX_IN_GPIO2_IN_3, + MUX_IN_GPIO2_IN_4, + MUX_IN_GPIO2_IN_5, + MUX_IN_GPIO2_IN_6, + MUX_IN_GPIO2_IN_7, + MUX_IN_GPIO2_IN_8, + MUX_IN_GPIO2_IN_9, + MUX_IN_GPIO3_IN_0, + MUX_IN_GPIO3_IN_10, + MUX_IN_GPIO3_IN_11, + MUX_IN_GPIO3_IN_12, + MUX_IN_GPIO3_IN_13, + MUX_IN_GPIO3_IN_14, + MUX_IN_GPIO3_IN_15, + MUX_IN_GPIO3_IN_4, + MUX_IN_GPIO3_IN_5, + MUX_IN_GPIO3_IN_6, + MUX_IN_GPIO3_IN_7, + MUX_IN_GPIO3_IN_8, + MUX_IN_GPIO3_IN_9, + MUX_IN_I2C3_SCL_IN, + MUX_IN_I2C3_SDA_IN, + MUX_IN_IPU_DISPB_D0_VSYNC, + MUX_IN_IPU_DISPB_D12_VSYNC, + MUX_IN_IPU_DISPB_SD_D, + MUX_IN_IPU_SENSB_DATA_0, + MUX_IN_IPU_SENSB_DATA_1, + MUX_IN_IPU_SENSB_DATA_2, + MUX_IN_IPU_SENSB_DATA_3, + MUX_IN_IPU_SENSB_DATA_4, + MUX_IN_IPU_SENSB_DATA_5, + MUX_IN_IPU_SENSB_DATA_6, + MUX_IN_IPU_SENSB_DATA_7, + MUX_IN_KPP_COL_0, + MUX_IN_KPP_COL_1, + MUX_IN_KPP_COL_2, + MUX_IN_KPP_COL_3, + MUX_IN_KPP_COL_4, + MUX_IN_KPP_COL_5, + MUX_IN_KPP_COL_6, + MUX_IN_KPP_COL_7, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_OWIRE_BATTERY_LINE, + MUX_IN_SPDIF_HCKT_CLK2, + MUX_IN_SPDIF_SPDIF_IN1, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, + MUX_IN_USB_OTG_DATA_0, + MUX_IN_USB_OTG_DATA_1, + MUX_IN_USB_OTG_DATA_2, + MUX_IN_USB_OTG_DATA_3, + MUX_IN_USB_OTG_DATA_4, + MUX_IN_USB_OTG_DATA_5, + MUX_IN_USB_OTG_DATA_6, + MUX_IN_USB_OTG_DATA_7, + MUX_IN_USB_OTG_DIR, + MUX_IN_USB_OTG_NXT, + MUX_IN_USB_UH2_DATA_0, + MUX_IN_USB_UH2_DATA_1, + MUX_IN_USB_UH2_DATA_2, + MUX_IN_USB_UH2_DATA_3, + MUX_IN_USB_UH2_DATA_4, + MUX_IN_USB_UH2_DATA_5, + MUX_IN_USB_UH2_DATA_6, + MUX_IN_USB_UH2_DATA_7, + MUX_IN_USB_UH2_DIR, + MUX_IN_USB_UH2_NXT, + MUX_IN_USB_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h new file mode 100644 index 0000000..14669ff --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ +#define __ASM_ARCH_MXC_MX35_PINS_H__ + +/*! + * @file arch-mxc/mx35_pins.h + * + * @brief MX35 I/O Pin List + * + * @ingroup GPIO_MX35 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field + * definitions are used for the pad control register.the MX35_PIN_A0 is + * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x28. + * The pad control register offset is: 0x368. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +typedef enum iomux_pins { + MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), + MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), + MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), + MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), + MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), + MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), + MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), + MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), + + MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), + MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), + + MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), + MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), + MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), + MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), + MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), + MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), + MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), + MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), + MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), + MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), + + MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), + MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), + MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), + + MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), + MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), + MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), + MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), + MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), + MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), + + MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), + MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), + MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), + MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), + MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), + MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), + MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), + MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), + MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), + MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), + MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), + MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), + MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), + MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), + MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), + MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), + + MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), + MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), + MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), + MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), + MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), + MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), + MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), + MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), + MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), + MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), + MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), + MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), + + MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), + MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), + MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), + MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), + + MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), + MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), + MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), + MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), + MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), + MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), + MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), + MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), + + MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), + MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), + MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), + MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), + MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), + MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), + MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), + MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), + MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), + MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), + MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), + MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), + + MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), + MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), + MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), + MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), + MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), + MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), + + MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), + MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), + MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), + MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), + MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), + MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), + MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), + MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), + + MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), + MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), + + MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), + MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), + MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), + MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), + MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), + MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), + MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), + MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), + MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), + MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), + MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), + MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), + MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), + MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), + MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), + MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), + MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), + MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), + MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), + MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), + MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), + MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), + MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), + MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), + + MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), + MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), + MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), + MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), + MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), + MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), + MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), + MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), + + MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), + MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), + MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), + MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), + MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), + MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), + MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), + MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), + MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), + MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), + MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), + MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), + + MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), + MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), + MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), + MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), + MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), + MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), + MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), + MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), + MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), + MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), + MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), + MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), + MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), + MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), + MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), + MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), + MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), + MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), + MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), + MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), + MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), + MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), + MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), + MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), + MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), + MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), + MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), + MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), + MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), + + MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), + MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), + MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), + + MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), + MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), + MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), + MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), + MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), + MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), + MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), + MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), + MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), + MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), + MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), + MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), + MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), + MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), + MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), + MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), + MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), + MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), +} iomux_pin_name_t; + +#endif +#endif diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h new file mode 100644 index 0000000..422eb52 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/sys_proto.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); + +#endif -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 01/11] Add support for MX35 processor 2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic @ 2011-01-20 9:25 ` Wolfgang Denk 2011-01-20 10:19 ` Stefano Babic 2011-01-20 17:49 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:25 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-2-git-send-email-sbabic@denx.de> you wrote: > The patch adds basic support for the Freescale's i.MX35 > (arm1136 based) processor. > > Signed-off-by: Stefano Babic <sbabic@denx.de> checkpatch says: [U-Boot] [PATCH V2 01/11] Add support for MX35 processor total: 7 errors, 8 warnings, 2109 lines checked Please fix. > +u32 get_cpu_rev(void) > +{ > + int reg; > + struct iim_regs *iim = > + (struct iim_regs *)IIM_BASE_ADDR; > + reg = readl(&iim->iim_srev); > + if (!reg) { > + reg = readw(ROMPATCH_REV); > + reg <<= 4; > + } else > + reg += CHIP_REV_1_0; If there are braces for the "if", then there shall also be braces for the "else" ("Use braces in both branches.") > +u32 imx_get_uartclk(void) > +{ > + u32 freq; > + struct ccm_regs *ccm = > + (struct ccm_regs *)IMX_CCM_BASE; > + u32 pdr4 = readl(&ccm->pdr4); > + > + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) > + freq = get_mcu_main_clk(); > + else > + freq = decode_pll(readl(&ccm->ppctl), > + CONFIG_MX35_HCLK_FREQ); Braces needed. > + case USB_CLK: > + usb_prdf = (reg4 >> 25) & 0x7; > + usb_podf = (reg4 >> 22) & 0x7; > + if (reg4 & 0x200) > + pll = get_mcu_main_clk(); > + else > + pll = decode_pll(readl(&ccm->ppctl), > + CONFIG_MX35_HCLK_FREQ); Ditto. Please fix globally. > index 0000000..c1dc62a > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx35/asm-offsets.h > @@ -0,0 +1,21 @@ > +/* > + * needed for lowlevel_init.S > + * > + * These should be auto-generated > + */ > +/* CCM */ > +#define CLKCTL_CCMR 0x00 > +#define CLKCTL_PDR0 0x04 > +#define CLKCTL_PDR1 0x08 > +#define CLKCTL_PDR2 0x0C > +#define CLKCTL_PDR3 0x10 > +#define CLKCTL_PDR4 0x14 > +#define CLKCTL_RCSR 0x18 > +#define CLKCTL_MPCTL 0x1C > +#define CLKCTL_PPCTL 0x20 > +#define CLKCTL_ACMR 0x24 > +#define CLKCTL_COSR 0x28 > +#define CLKCTL_CGR0 0x2C > +#define CLKCTL_CGR1 0x30 > +#define CLKCTL_CGR2 0x34 > +#define CLKCTL_CGR3 0x38 Indeed they should. Why don't you autogenerate these, then? We have all the tools in place, use them. > +#define NFC_BUF_SIZE 0x1000 > +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) > +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) > +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) > +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) > +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) > +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) > +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) > +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) > +#define NF_WR_PROT_REG_OFF (0 + 0x12) > +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) > +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) > +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) > +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) > +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) Why has this not been converted into a C struct? ... > +typedef enum iomux_pin_config { > + MUX_CONFIG_FUNC = 0, /*!< used as function */ > + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ > + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ > + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ > + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ > + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ > + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ > + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ > + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ > + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ > +} iomux_pin_cfg_t; /*!< ??? > +/*! /*! ??? ... > +/*! > + * Request ownership for an IO pin. This function has to be the first one > + * being called before that pin is used. The caller has to check the > + * return value to make sure it returns 0. > + * > + * @param pin a name defined by \b iomux_pin_name_t > + * @param cfg an input function as defined in \b #iomux_pin_cfg_t \b ??? > + * @param pin a name defined by \b iomux_pin_name_t > + * @param cfg an input function as defined in \b #iomux_pin_cfg_t "iomux_pin_name_t", but "#iomux_pin_cfg_t" ??? ... > +typedef enum iomux_pins { ... > + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), > + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), > + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), > + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), > + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), > + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), > + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), > + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), > + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), > + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), > + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), > + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), > + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), > + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), > + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), > + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), > + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), > + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), > + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), > + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), > + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), > + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), > + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), > + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), > + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), > + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), > + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), Note: the following remark is a question, NOT a change request: Would it not be possible to reduce all these terrible lists? As far as I can tell, the list is built sequentially, with both arguments to _MXC_BUILD_NON_GPIO_PIN() being incremented by 4 for the next register. This begs for automatic code generation, doesn't it? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de The human race has one really effective weapon, and that is laughter. - Mark Twain ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 01/11] Add support for MX35 processor 2011-01-20 9:25 ` Wolfgang Denk @ 2011-01-20 10:19 ` Stefano Babic 2011-01-20 11:52 ` Wolfgang Denk 0 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:19 UTC (permalink / raw) To: u-boot On 01/20/2011 10:25 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-2-git-send-email-sbabic@denx.de> you wrote: >> The patch adds basic support for the Freescale's i.MX35 >> (arm1136 based) processor. >> >> Signed-off-by: Stefano Babic <sbabic@denx.de> > > checkpatch says: > > [U-Boot] [PATCH V2 01/11] Add support for MX35 processor > total: 7 errors, 8 warnings, 2109 lines checked Mmmhh...checkpatch says: total: 0 errors, 8 warnings, 2109 lines checked 0001-Add-support-for-MX35-processor.patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see Warnings are only related to typedef ("do not add typedef"), so I do not know where the errors are coming from. Do you use the --no-tree option as I usually set? > >> +u32 imx_get_uartclk(void) >> +{ >> + u32 freq; >> + struct ccm_regs *ccm = >> + (struct ccm_regs *)IMX_CCM_BASE; >> + u32 pdr4 = readl(&ccm->pdr4); >> + >> + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) >> + freq = get_mcu_main_clk(); >> + else >> + freq = decode_pll(readl(&ccm->ppctl), >> + CONFIG_MX35_HCLK_FREQ); > > Braces needed checkpatch (and generally accepted in linux, as I can see) requires that single statements must not be surrounded by braces. checkpatch returns a warning, explaining that braces are not needed. I see in the past some comments requiring to remove braces, but it you prefer to add them. IMHO it is better to follow the same codestyle as linux, using the same tools as checkpatch. I do not know why we have two different results from checkpatch, I try to investigate. I had prefer to use always braces in if statement, to avoid possible errors if some code is added, but since checkpatch complains about it I was convinced to remove them. > >> + case USB_CLK: >> + usb_prdf = (reg4 >> 25) & 0x7; >> + usb_podf = (reg4 >> 22) & 0x7; >> + if (reg4 & 0x200) >> + pll = get_mcu_main_clk(); >> + else >> + pll = decode_pll(readl(&ccm->ppctl), >> + CONFIG_MX35_HCLK_FREQ); > > Ditto. Please fix globally. See my previous comment. I would prefer to not have a different rule in u-boot, and not go against some provided tool (we use both checkpatch) if not strictly required. > > Indeed they should. Why don't you autogenerate these, then? > > We have all the tools in place, use them. I will see how to use them. > > >> +#define NFC_BUF_SIZE 0x1000 >> +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) >> +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) >> +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) >> +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) >> +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) >> +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) >> +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) >> +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) >> +#define NF_WR_PROT_REG_OFF (0 + 0x12) >> +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) >> +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) >> +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) >> +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) >> +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) > > Why has this not been converted into a C struct? I will check, I think I do not require anymore. NAND driver is in mainline and does not require them. Probably I can remove them. In the code I post now I do not use them at all, so probably I can remove them without problems. > > ... >> +typedef enum iomux_pin_config { >> + MUX_CONFIG_FUNC = 0, /*!< used as function */ >> + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ >> + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ >> + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ >> + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ >> + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ >> + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ >> + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ >> + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ >> + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ >> +} iomux_pin_cfg_t; > > /*!< ??? I forget to remove them, thanks. > ... >> +/*! >> + * Request ownership for an IO pin. This function has to be the first one >> + * being called before that pin is used. The caller has to check the >> + * return value to make sure it returns 0. >> + * >> + * @param pin a name defined by \b iomux_pin_name_t >> + * @param cfg an input function as defined in \b #iomux_pin_cfg_t > > \b ??? > >> + * @param pin a name defined by \b iomux_pin_name_t >> + * @param cfg an input function as defined in \b #iomux_pin_cfg_t > > "iomux_pin_name_t", but "#iomux_pin_cfg_t" ??? I'll fix them >> +typedef enum iomux_pins { > ... >> + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), >> + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), >> + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), >> + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), >> + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), >> + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), >> + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), >> + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), >> + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), >> + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), >> + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), >> + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), >> + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), >> + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), >> + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), >> + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), >> + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), >> + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), >> + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), >> + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), >> + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), >> + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), >> + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), >> + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), >> + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), >> + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), >> + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), > > Note: the following remark is a question, NOT a change request: > > Would it not be possible to reduce all these terrible lists? As far > as I can tell, the list is built sequentially, with both arguments to > _MXC_BUILD_NON_GPIO_PIN() being incremented by 4 for the next > register. This begs for automatic code generation, doesn't it? I do not know if it helps. The list follows exactly the description in user manual, and, if you can see a rule for MX35_PIN_A*, it is not so simply to find one for other pins, specially for the MXC_BUILD_GPIO_PIN. At least, the list is at the moment coherent for all i.MX processors (ok, ugly for all). The name of the pin cannot be generated, and it is the name found in manual. Miore as generated, the list is sorted.... Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 01/11] Add support for MX35 processor 2011-01-20 10:19 ` Stefano Babic @ 2011-01-20 11:52 ` Wolfgang Denk 0 siblings, 0 replies; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 11:52 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <4D380C25.20901@denx.de> you wrote: > > >> + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) > >> + freq = get_mcu_main_clk(); > >> + else > >> + freq = decode_pll(readl(&ccm->ppctl), > >> + CONFIG_MX35_HCLK_FREQ); > > > > Braces needed > > checkpatch (and generally accepted in linux, as I can see) requires that > single statements must not be surrounded by braces. checkpatch returns a > warning, explaining that braces are not needed. > I see in the past some comments requiring to remove braces, but it you > prefer to add them. IMHO it is better to follow the same codestyle as > linux, using the same tools as checkpatch. I do not know why we have two > different results from checkpatch, I try to investigate. I had prefer to I was running an older version of checkpatch... > >> + case USB_CLK: > >> + usb_prdf = (reg4 >> 25) & 0x7; > >> + usb_podf = (reg4 >> 22) & 0x7; > >> + if (reg4 & 0x200) > >> + pll = get_mcu_main_clk(); > >> + else > >> + pll = decode_pll(readl(&ccm->ppctl), > >> + CONFIG_MX35_HCLK_FREQ); > > > > Ditto. Please fix globally. > > See my previous comment. I would prefer to not have a different rule in > u-boot, and not go against some provided tool (we use both checkpatch) > if not strictly required. Did you try it? For me, both + if (reg4 & 0x200) + pll = get_mcu_main_clk(); + else + pll = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); and + if (reg4 & 0x200) { + pll = get_mcu_main_clk(); + } else { + pll = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + } generate _NO_ warnings with checkpatch. I feel that when the "single statement" is split across several lines, eventually even including blank lines (see yesterday's discussion here), then braces are needed. > > Indeed they should. Why don't you autogenerate these, then? > > > > We have all the tools in place, use them. > > I will see how to use them. See tools/scripts/make-asm-offsets > > Note: the following remark is a question, NOT a change request: > > > > Would it not be possible to reduce all these terrible lists? As far > > as I can tell, the list is built sequentially, with both arguments to > > _MXC_BUILD_NON_GPIO_PIN() being incremented by 4 for the next > > register. This begs for automatic code generation, doesn't it? > > I do not know if it helps. The list follows exactly the description in > user manual, and, if you can see a rule for MX35_PIN_A*, it is not so > simply to find one for other pins, specially for the MXC_BUILD_GPIO_PIN. > At least, the list is at the moment coherent for all i.MX processors > (ok, ugly for all). The name of the pin cannot be generated, and it is > the name found in manual. Miore as generated, the list is sorted.... OK, thanks for the explanation. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "You're just jealous." "What, of an overgrown puppy with a single- figure IQ?" - Terry Pratchett, _Moving Pictures_ ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 01/11] Add support for MX35 processor 2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic 2011-01-20 9:25 ` Wolfgang Denk @ 2011-01-20 17:49 ` Stefano Babic 2011-02-01 17:50 ` Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 17:49 UTC (permalink / raw) To: u-boot The patch adds basic support for the Freescale's i.MX35 (arm1136 based) processor. The patch adds also a prototype for the initialization of the FEC(ethernet controller) to netdev.h to avoid warnings. Signed-off-by: Stefano Babic <sbabic@denx.de> --- Changes: Wolfgang Denk: - fix code styling issues reported by checkpatch - fix missing braces (code styling) - generates asm-offsets.h. See arch/arm/cpu/arm1136/mx35/Makefile for rules - drop unnedded NAND defines arch/arm/cpu/arm1136/mx35/Makefile | 64 ++++ arch/arm/cpu/arm1136/mx35/asm-offsets.c | 43 +++ arch/arm/cpu/arm1136/mx35/generic.c | 462 ++++++++++++++++++++++++++++ arch/arm/cpu/arm1136/mx35/iomux.c | 116 +++++++ arch/arm/cpu/arm1136/mx35/timer.c | 120 +++++++ arch/arm/include/asm/arch-mx35/clock.h | 45 +++ arch/arm/include/asm/arch-mx35/crm_regs.h | 270 ++++++++++++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 291 +++++++++++++++++ arch/arm/include/asm/arch-mx35/iomux.h | 295 ++++++++++++++++++ arch/arm/include/asm/arch-mx35/mx35_pins.h | 355 +++++++++++++++++++++ arch/arm/include/asm/arch-mx35/sys_proto.h | 31 ++ include/netdev.h | 1 + 12 files changed, 2093 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm1136/mx35/Makefile create mode 100644 arch/arm/cpu/arm1136/mx35/asm-offsets.c create mode 100644 arch/arm/cpu/arm1136/mx35/generic.c create mode 100644 arch/arm/cpu/arm1136/mx35/iomux.c create mode 100644 arch/arm/cpu/arm1136/mx35/timer.c create mode 100644 arch/arm/include/asm/arch-mx35/clock.h create mode 100644 arch/arm/include/asm/arch-mx35/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx35/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx35/iomux.h create mode 100644 arch/arm/include/asm/arch-mx35/mx35_pins.h create mode 100644 arch/arm/include/asm/arch-mx35/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile new file mode 100644 index 0000000..82c7218 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -0,0 +1,64 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o +COBJS += iomux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + +$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \ + ./asm-offsets.s + @echo Generating $@ + $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@ + +asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \ + ./asm-offsets.c + $(CC) -DDO_DEPS_ONLY \ + $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ ./asm-offsets.c -c -S + diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c new file mode 100644 index 0000000..d2678e2 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/asm-offsets.c @@ -0,0 +1,43 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); + DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); + DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); + DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); + DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); + DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); + DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); + DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); + DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); + DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); + DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); + DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); + + return 0; +} diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c new file mode 100644 index 0000000..b93ed03 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -0,0 +1,462 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +#define CLK_CODE_PATH(c) ((c) & 0xFF) + +#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +static int g_clk_mux_auto[8] = { + CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, + CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +}; + +static int g_clk_mux_consumer[16] = { + CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, + -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), + CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, + -1, -1, CLK_CODE(4, 2, 0), -1, +}; + +static int hsp_div_table[3][16] = { + {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, + {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, + {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +}; + +u32 get_cpu_rev(void) +{ + int reg; + struct iim_regs *iim = + (struct iim_regs *)IIM_BASE_ADDR; + reg = readl(&iim->iim_srev); + if (!reg) { + reg = readw(ROMPATCH_REV); + reg <<= 4; + } else { + reg += CHIP_REV_1_0; + } + + return 0x35000 + (reg & 0xFF); +} + +static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) +{ + int *pclk_mux; + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + } else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) + return -1; + + if (fi && fd) { + if (!CLK_CODE_PATH(*pclk_mux)) { + *fi = *fd = 1; + return CLK_CODE_ARM(*pclk_mux); + } + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + *fi = 3; + *fd = 4; + } else { + *fi = 2; + *fd = 3; + } + } + return CLK_CODE_ARM(*pclk_mux); +} + +static int get_ahb_div(u32 pdr0) +{ + int *pclk_mux; + + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + + if ((*pclk_mux) == -1) + return -1; + + return CLK_CODE_AHB(*pclk_mux); +} + +static u32 decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 get_mcu_main_clk(void) +{ + u32 arm_div = 0, fi = 0, fd = 0; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); + fi *= + decode_pll(readl(&ccm->mpctl), + CONFIG_MX35_HCLK_FREQ); + return fi / (arm_div * fd); +} + +static u32 get_ipg_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + + return freq / (get_ahb_div(pdr0) * 2); +} + +static u32 get_ipg_per_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + u32 pdr4 = readl(&ccm->pdr4); + u32 div; + if (pdr0 & MXC_CCM_PDR0_PER_SEL) { + div = (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PRDF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PODF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + } else { + div = CCM_GET_DIVIDER(pdr0, + MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; + freq /= get_ahb_div(pdr0); + } + return freq / div; +} + +u32 imx_get_uartclk(void) +{ + u32 freq; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr4 = readl(&ccm->pdr4); + + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { + freq = get_mcu_main_clk(); + } else { + freq = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + } + freq /= ((CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PRDF_MASK, + MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PODF_MASK, + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + return freq; +} + +unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +{ + u32 nfc_pdf, hsp_podf; + u32 pll, ret_val = 0, usb_prdf, usb_podf; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 reg = readl(&ccm->pdr0); + u32 reg4 = readl(&ccm->pdr4); + + reg |= 0x1; + + switch (clk) { + case CPU_CLK: + ret_val = get_mcu_main_clk(); + break; + case AHB_CLK: + ret_val = get_mcu_main_clk(); + break; + case HSP_CLK: + if (reg & CLKMODE_CONSUMER) { + hsp_podf = (reg >> 20) & 0x3; + pll = get_mcu_main_clk(); + hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; + if (hsp_podf > 0) { + ret_val = pll / hsp_podf; + } else { + puts("mismatch HSP with ARM clock setting\n"); + ret_val = 0; + } + } else { + ret_val = get_mcu_main_clk(); + } + break; + case IPG_CLK: + ret_val = get_ipg_clk();; + break; + case IPG_PER_CLK: + ret_val = get_ipg_per_clk(); + break; + case NFC_CLK: + nfc_pdf = (reg4 >> 28) & 0xF; + pll = get_mcu_main_clk(); + /* AHB/nfc_pdf */ + ret_val = pll / (nfc_pdf + 1); + break; + case USB_CLK: + usb_prdf = (reg4 >> 25) & 0x7; + usb_podf = (reg4 >> 22) & 0x7; + if (reg4 & 0x200) { + pll = get_mcu_main_clk(); + } else { + pll = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + } + + ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + break; + default: + printf("Unknown clock: %d\n", clk); + break; + } + + return ret_val; +} +unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 mpdr2 = readl(&ccm->pdr2); + u32 mpdr3 = readl(&ccm->pdr3); + u32 mpdr4 = readl(&ccm->pdr4); + + switch (clk) { + case UART1_BAUD: + case UART2_BAUD: + case UART3_BAUD: + clk_sel = mpdr3 & (1 << 14); + pre_pdf = (mpdr4 >> 13) & 0x7; + pdf = (mpdr4 >> 10) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI1_BAUD: + pre_pdf = (mpdr2 >> 24) & 0x7; + pdf = mpdr2 & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI2_BAUD: + pre_pdf = (mpdr2 >> 27) & 0x7; + pdf = (mpdr2 >> 8) & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case CSI_BAUD: + clk_sel = mpdr2 & (1 << 7); + pre_pdf = (mpdr2 >> 16) & 0x7; + pdf = (mpdr2 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case MSHC_CLK: + pre_pdf = readl(&ccm->pdr1); + clk_sel = (pre_pdf & 0x80); + pdf = (pre_pdf >> 22) & 0x3F; + pre_pdf = (pre_pdf >> 28) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC1_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = mpdr3 & 0x7; + pdf = (mpdr3>>3) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC2_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 8) & 0x7; + pdf = (mpdr3 >> 11) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC3_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 16) & 0x7; + pdf = (mpdr3 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SPDIF_CLK: + clk_sel = mpdr3 & 0x400000; + pre_pdf = (mpdr3 >> 29) & 0x7; + pdf = (mpdr3 >> 23) & 0x3F; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + default: + printf("%s(): This clock: %d not supported yet\n", + __func__, clk); + break; + } + + return ret_val; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return imx_get_uartclk(); + case MXC_ESDHC_CLK: + return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_USB_CLK: + return mxc_get_main_clock(USB_CLK); + case MXC_FEC_CLK: + return get_ipg_clk(); + case MXC_CSPI_CLK: + return get_ipg_clk(); + } + return -1; +} + +#ifdef CONFIG_FEC_MXC +/* + * The MX35 has no fuse for MAC, return a NULL MAC + */ +void imx_get_mac_from_fuse(unsigned char *mac) +{ + memset(mac, 0, 6); +} + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} +#endif + +int do_mx35_showclocks(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 cpufreq = get_mcu_main_clk(); + printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("ipg clock : %dHz\n", get_ipg_clk()); + printf("ipg per clock : %dHz\n", get_ipg_per_clk()); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + + return 0; +} + +U_BOOT_CMD( + clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, + "display clocks\n", + "" +); + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX35 at %d MHz\n", + get_mcu_main_clk() / 1000000); + /* mxc_dump_clocks(); */ + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + +void reset_cpu(ulong addr) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + writew(4, &wdog->wcr); +} diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c new file mode 100644 index 0000000..f93191d --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/iomux.c @@ -0,0 +1,116 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> + +/* + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */ + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */ + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */ + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */ + IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */ + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */ + IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + writel(cfg, mux_reg); + } +} + +/* + * Release ownership for an IO pin + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in iomux_pin_name_t + * @param config the ORed value of elements defined in iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + writel(config, pad_reg); +} + +/* + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in iomux_gp_func_t + * @param en enable/disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) +{ + u32 l; + + l = readl(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + writel(l, IOMUXGPR); +} + +/* + * This function configures input path. + * + * @param input index of input select register as defined in + * iomux_input_select_t + * @param config the binary value of elements defined in + * iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c new file mode 100644 index 0000000..db1e2c9 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +int timer_init(void) +{ + int i; + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + /* setup GP Timer 1 */ + writel(GPTCR_SWR, &gpt->ctrl); + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + + writel(GPTPR_VAL, &gpt->pre); + /* Freerun Mode, PERCLK1 input */ + writel(readl(&gpt->ctrl) | + GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + writel(0, &gpt->ctrl); + /* Freerun Mode, PERCLK1 input */ + writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); +} + +inline ulong get_timer_masked(void) +{ + + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + ulong val = readl(&gpt->counter); + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* + * delay x useconds AND preserve advance timstamp value + * GPTCNT is now supposed to tick 1 by 1 us. + */ +void __udelay(unsigned long usec) +{ + ulong tmp; + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h new file mode 100644 index 0000000..4c0ddfd --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_USB_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h new file mode 100644 index 0000000..e903cf1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -0,0 +1,270 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +#define __CPU_ARM1136_MX35_CRM_REGS_H__ + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 21 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 +#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 +#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 15) +#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 +#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 +#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 +#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) +#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 +#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 +#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EDI0_OFFSET 16 +#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) +#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) +#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +#endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h new file mode 100644 index 0000000..7978444 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -0,0 +1,291 @@ +/* + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX35_H +#define __ASM_ARCH_MX35_H + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define IRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define I2C_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE_ADDR 0x43F90000 +#define UART2_BASE_ADDR 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define IOMUXC_BASE_ADDR 0x43FAC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define UART3_BASE_ADDR 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define FEC_BASE_ADDR 0x50038000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 +#define IIM_BASE_ADDR 0x53FF0000 + +#define IMX_CCM_BASE CCM_BASE_ADDR + +/* + * ROMPATCH and AVIC + */ +#define ROMPATCH_BASE_ADDR 0x60000000 +#define AVIC_BASE_ADDR 0x68000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +#define M3IF_BASE_ADDR 0xB8003000 +#define EMI_BASE_ADDR 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS5_BASE_ADDR 0xB6000000 + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_NIMASK 0x04 +#define AVIC_INTTYPEH 0x18 +#define AVIC_INTTYPEL 0x1C + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +#define L2_CACHE_DBG_CTL_REG 0xF40 + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) + +#define IIM_SREV 0x24 +#define ROMPATCH_REV 0x40 + +#define IPU_CONF IPU_CTRL_BASE_ADDR + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +extern void imx_get_mac_from_fuse(unsigned char *mac); + +enum mxc_main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 ccmr; /* Control */ + u32 pdr0; /* Post divider 0 */ + u32 pdr1; /* Post divider 1 */ + u32 pdr2; /* Post divider 2 */ + u32 pdr3; /* Post divider 3 */ + u32 pdr4; /* Post divider 4 */ + u32 rcsr; /* CCM Status */ + u32 mpctl; /* Core PLL Control */ + u32 ppctl; /* Peripheral PLL Control */ + u32 acmr; /* Audio clock mux */ + u32 cosr; /* Clock out source */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 cgr3; /* Clock Gating Control 3 */ + u32 reserved; + u32 dcvr0; /* DPTC Comparator 0 */ + u32 dcvr1; /* DPTC Comparator 0 */ + u32 dcvr2; /* DPTC Comparator 0 */ + u32 dcvr3; /* DPTC Comparator 0 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ +}; + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) + +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern int sdhc_init(void); + +#endif +#endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h new file mode 100644 index 0000000..52c15bc --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/iomux.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_MX35_IOMUX_H__ +#define __MACH_MX35_IOMUX_H__ + +#include <asm/arch/imx-regs.h> + +/* + * various IOMUX functions + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /* used as function */ + MUX_CONFIG_ALT1, /* used as alternate function 1 */ + MUX_CONFIG_ALT2, /* used as alternate function 2 */ + MUX_CONFIG_ALT3, /* used as alternate function 3 */ + MUX_CONFIG_ALT4, /* used as alternate function 4 */ + MUX_CONFIG_ALT5, /* used as alternate function 5 */ + MUX_CONFIG_ALT6, /* used as alternate function 6 */ + MUX_CONFIG_ALT7, /* used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */ +} iomux_pin_cfg_t; + +/* + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/* + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, + MUX_TAMPER_DETECT_EN = 0x1 << 2, +} iomux_gp_func_t; + +/* + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AMX_P5_RXCLK = 0, + MUX_IN_AMX_P5_RXFS, + MUX_IN_AMX_P6_DA, + MUX_IN_AMX_P6_DB, + MUX_IN_AMX_P6_RXCLK, + MUX_IN_AMX_P6_RXFS, + MUX_IN_AMX_P6_TXCLK, + MUX_IN_AMX_P6_TXFS, + MUX_IN_CAN1_CANRX, + MUX_IN_CAN2_CANRX, + MUX_IN_CCM_32K_MUXED, + MUX_IN_CCM_PMIC_RDY, + MUX_IN_CSPI1_SS2_B, + MUX_IN_CSPI1_SS3_B, + MUX_IN_CSPI2_CLK_IN, + MUX_IN_CSPI2_DATAREADY_B, + MUX_IN_CSPI2_MISO, + MUX_IN_CSPI2_MOSI, + MUX_IN_CSPI2_SS0_B, + MUX_IN_CSPI2_SS1_B, + MUX_IN_CSPI2_SS2_B, + MUX_IN_CSPI2_SS3_B, + MUX_IN_EMI_WEIM_DTACK_B, + MUX_IN_ESDHC1_DAT4_IN, + MUX_IN_ESDHC1_DAT5_IN, + MUX_IN_ESDHC1_DAT6_IN, + MUX_IN_ESDHC1_DAT7_IN, + MUX_IN_ESDHC3_CARD_CLK_IN, + MUX_IN_ESDHC3_CMD_IN, + MUX_IN_ESDHC3_DAT0, + MUX_IN_ESDHC3_DAT1, + MUX_IN_ESDHC3_DAT2, + MUX_IN_ESDHC3_DAT3, + MUX_IN_GPIO1_IN_0, + MUX_IN_GPIO1_IN_10, + MUX_IN_GPIO1_IN_11, + MUX_IN_GPIO1_IN_1, + MUX_IN_GPIO1_IN_20, + MUX_IN_GPIO1_IN_21, + MUX_IN_GPIO1_IN_22, + MUX_IN_GPIO1_IN_2, + MUX_IN_GPIO1_IN_3, + MUX_IN_GPIO1_IN_4, + MUX_IN_GPIO1_IN_5, + MUX_IN_GPIO1_IN_6, + MUX_IN_GPIO1_IN_7, + MUX_IN_GPIO1_IN_8, + MUX_IN_GPIO1_IN_9, + MUX_IN_GPIO2_IN_0, + MUX_IN_GPIO2_IN_10, + MUX_IN_GPIO2_IN_11, + MUX_IN_GPIO2_IN_12, + MUX_IN_GPIO2_IN_13, + MUX_IN_GPIO2_IN_14, + MUX_IN_GPIO2_IN_15, + MUX_IN_GPIO2_IN_16, + MUX_IN_GPIO2_IN_17, + MUX_IN_GPIO2_IN_18, + MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_20, + MUX_IN_GPIO2_IN_21, + MUX_IN_GPIO2_IN_22, + MUX_IN_GPIO2_IN_23, + MUX_IN_GPIO2_IN_24, + MUX_IN_GPIO2_IN_25, + MUX_IN_GPIO2_IN_26, + MUX_IN_GPIO2_IN_27, + MUX_IN_GPIO2_IN_28, + MUX_IN_GPIO2_IN_29, + MUX_IN_GPIO2_IN_2, + MUX_IN_GPIO2_IN_30, + MUX_IN_GPIO2_IN_31, + MUX_IN_GPIO2_IN_3, + MUX_IN_GPIO2_IN_4, + MUX_IN_GPIO2_IN_5, + MUX_IN_GPIO2_IN_6, + MUX_IN_GPIO2_IN_7, + MUX_IN_GPIO2_IN_8, + MUX_IN_GPIO2_IN_9, + MUX_IN_GPIO3_IN_0, + MUX_IN_GPIO3_IN_10, + MUX_IN_GPIO3_IN_11, + MUX_IN_GPIO3_IN_12, + MUX_IN_GPIO3_IN_13, + MUX_IN_GPIO3_IN_14, + MUX_IN_GPIO3_IN_15, + MUX_IN_GPIO3_IN_4, + MUX_IN_GPIO3_IN_5, + MUX_IN_GPIO3_IN_6, + MUX_IN_GPIO3_IN_7, + MUX_IN_GPIO3_IN_8, + MUX_IN_GPIO3_IN_9, + MUX_IN_I2C3_SCL_IN, + MUX_IN_I2C3_SDA_IN, + MUX_IN_IPU_DISPB_D0_VSYNC, + MUX_IN_IPU_DISPB_D12_VSYNC, + MUX_IN_IPU_DISPB_SD_D, + MUX_IN_IPU_SENSB_DATA_0, + MUX_IN_IPU_SENSB_DATA_1, + MUX_IN_IPU_SENSB_DATA_2, + MUX_IN_IPU_SENSB_DATA_3, + MUX_IN_IPU_SENSB_DATA_4, + MUX_IN_IPU_SENSB_DATA_5, + MUX_IN_IPU_SENSB_DATA_6, + MUX_IN_IPU_SENSB_DATA_7, + MUX_IN_KPP_COL_0, + MUX_IN_KPP_COL_1, + MUX_IN_KPP_COL_2, + MUX_IN_KPP_COL_3, + MUX_IN_KPP_COL_4, + MUX_IN_KPP_COL_5, + MUX_IN_KPP_COL_6, + MUX_IN_KPP_COL_7, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_OWIRE_BATTERY_LINE, + MUX_IN_SPDIF_HCKT_CLK2, + MUX_IN_SPDIF_SPDIF_IN1, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, + MUX_IN_USB_OTG_DATA_0, + MUX_IN_USB_OTG_DATA_1, + MUX_IN_USB_OTG_DATA_2, + MUX_IN_USB_OTG_DATA_3, + MUX_IN_USB_OTG_DATA_4, + MUX_IN_USB_OTG_DATA_5, + MUX_IN_USB_OTG_DATA_6, + MUX_IN_USB_OTG_DATA_7, + MUX_IN_USB_OTG_DIR, + MUX_IN_USB_OTG_NXT, + MUX_IN_USB_UH2_DATA_0, + MUX_IN_USB_UH2_DATA_1, + MUX_IN_USB_UH2_DATA_2, + MUX_IN_USB_UH2_DATA_3, + MUX_IN_USB_UH2_DATA_4, + MUX_IN_USB_UH2_DATA_5, + MUX_IN_USB_UH2_DATA_6, + MUX_IN_USB_UH2_DATA_7, + MUX_IN_USB_UH2_DIR, + MUX_IN_USB_UH2_NXT, + MUX_IN_USB_UH2_USB_OC, +} iomux_input_select_t; + +/* + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/* + * Release ownership for an IO pin + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/* + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in iomux_gp_func_t + * @param en 1 to enable; 0 to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in iomux_pin_name_t + * @param config the ORed value of elements defined in + * iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/* + * This function configures input path. + * + * @param input index of input select register as defined in + * iomux_input_select_t + * @param config the binary value of elements defined in + * iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h new file mode 100644 index 0000000..14669ff --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ +#define __ASM_ARCH_MXC_MX35_PINS_H__ + +/*! + * @file arch-mxc/mx35_pins.h + * + * @brief MX35 I/O Pin List + * + * @ingroup GPIO_MX35 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field + * definitions are used for the pad control register.the MX35_PIN_A0 is + * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x28. + * The pad control register offset is: 0x368. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +typedef enum iomux_pins { + MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), + MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), + MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), + MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), + MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), + MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), + MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), + MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), + + MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), + MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), + + MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), + MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), + MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), + MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), + MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), + MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), + MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), + MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), + MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), + MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), + + MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), + MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), + MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), + + MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), + MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), + MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), + MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), + MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), + MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), + + MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), + MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), + MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), + MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), + MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), + MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), + MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), + MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), + MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), + MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), + MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), + MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), + MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), + MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), + MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), + MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), + + MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), + MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), + MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), + MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), + MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), + MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), + MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), + MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), + MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), + MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), + MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), + MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), + + MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), + MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), + MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), + MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), + + MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), + MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), + MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), + MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), + MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), + MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), + MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), + MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), + + MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), + MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), + MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), + MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), + MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), + MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), + MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), + MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), + MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), + MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), + MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), + MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), + + MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), + MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), + MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), + MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), + MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), + MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), + + MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), + MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), + MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), + MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), + MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), + MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), + MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), + MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), + + MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), + MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), + + MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), + MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), + MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), + MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), + MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), + MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), + MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), + MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), + MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), + MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), + MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), + MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), + MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), + MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), + MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), + MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), + MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), + MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), + MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), + MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), + MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), + MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), + MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), + MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), + + MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), + MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), + MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), + MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), + MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), + MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), + MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), + MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), + + MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), + MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), + MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), + MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), + MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), + MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), + MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), + MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), + MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), + MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), + MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), + MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), + + MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), + MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), + MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), + MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), + MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), + MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), + MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), + MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), + MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), + MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), + MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), + MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), + MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), + MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), + MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), + MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), + MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), + MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), + MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), + MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), + MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), + MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), + MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), + MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), + MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), + MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), + MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), + MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), + MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), + + MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), + MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), + MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), + + MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), + MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), + MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), + MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), + MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), + MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), + MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), + MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), + MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), + MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), + MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), + MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), + MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), + MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), + MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), + MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), + MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), + MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), +} iomux_pin_name_t; + +#endif +#endif diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h new file mode 100644 index 0000000..422eb52 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/sys_proto.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); + +#endif diff --git a/include/netdev.h b/include/netdev.h index 1a542e8..6f0a971 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -93,6 +93,7 @@ int uli526x_initialize(bd_t *bis); int xilinx_emaclite_initialize (bd_t *bis, int base_addr); int sh_eth_initialize(bd_t *bis); int dm9000_initialize(bd_t *bis); +int fecmxc_initialize(bd_t *bis); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 01/11] Add support for MX35 processor 2011-01-20 17:49 ` [U-Boot] [PATCH V3 " Stefano Babic @ 2011-02-01 17:50 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-02-01 17:50 UTC (permalink / raw) To: u-boot On 01/20/2011 06:49 PM, Stefano Babic wrote: > The patch adds basic support for the Freescale's i.MX35 > (arm1136 based) processor. > > The patch adds also a prototype for the initialization > of the FEC(ethernet controller) to netdev.h to avoid > warnings. > > Signed-off-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-imx, thanks Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 02/11] serial_mxc: add support for Freescale's i.MX35 processor 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the " Stefano Babic ` (9 subsequent siblings) 11 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot The patch adds UART support for the i.MX35 processor. Signed-off-by: Stefano Babic <sbabic@denx.de> --- drivers/serial/serial_mxc.c | 15 ++++++--------- 1 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 805f4c5..b9cf9de 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -50,17 +50,14 @@ #define UART_PHYS 0x1001b000 #elif defined(CONFIG_SYS_MX27_UART6) #define UART_PHYS 0x1001c000 -#elif defined(CONFIG_SYS_MX51_UART1) +#elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \ + defined(CONFIG_SYS_MX53_UART1) #define UART_PHYS UART1_BASE_ADDR -#elif defined(CONFIG_SYS_MX51_UART2) +#elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \ + defined(CONFIG_SYS_MX53_UART2) #define UART_PHYS UART2_BASE_ADDR -#elif defined(CONFIG_SYS_MX51_UART3) -#define UART_PHYS UART3_BASE_ADDR -#elif defined(CONFIG_SYS_MX53_UART1) -#define UART_PHYS UART1_BASE_ADDR -#elif defined(CONFIG_SYS_MX53_UART2) -#define UART_PHYS UART2_BASE_ADDR -#elif defined(CONFIG_SYS_MX53_UART3) +#elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \ + defined(CONFIG_SYS_MX53_UART3) #define UART_PHYS UART3_BASE_ADDR #else #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the i.MX35 processor 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 02/11] serial_mxc: add support for Freescale's i.MX35 processor Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-21 6:28 ` Heiko Schocher 2011-01-20 8:46 ` [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access Stefano Babic ` (8 subsequent siblings) 11 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> --- Changes: Wolfgang Denk: - Do not use XXX in defines because are blocked by SPAM filters drivers/i2c/mxc_i2c.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 1ebec14..7f669ff 100755 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -29,9 +29,8 @@ #if defined(CONFIG_MX31) #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> -#endif - -#if defined(CONFIG_MX53) +#else +#include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #endif @@ -66,8 +65,10 @@ #define I2C_BASE I2C1_BASE_ADDR #elif defined(CONFIG_SYS_I2C_MX53_PORT2) #define I2C_BASE I2C2_BASE_ADDR +#elif defined(CONFIG_SYS_I2C_MX35_PORT1) +#define I2C_BASE I2C_BASE_ADDR #else -#error "define CONFIG_SYS_I2C_MXxx_PORTx to use the I2C driver" +#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" #endif #ifdef DEBUG -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the i.MX35 processor 2011-01-20 8:46 ` [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the " Stefano Babic @ 2011-01-21 6:28 ` Heiko Schocher 0 siblings, 0 replies; 46+ messages in thread From: Heiko Schocher @ 2011-01-21 6:28 UTC (permalink / raw) To: u-boot Hello Stefano, Stefano Babic wrote: > Signed-off-by: Stefano Babic <sbabic@denx.de> > CC: Heiko Schocher <hs@denx.de> > --- > Changes: > > Wolfgang Denk: > - Do not use XXX in defines because are blocked by SPAM filters > > drivers/i2c/mxc_i2c.c | 9 +++++---- > 1 files changed, 5 insertions(+), 4 deletions(-) Acked-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (2 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the " Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:27 ` Wolfgang Denk 2011-01-20 17:50 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor Stefano Babic ` (7 subsequent siblings) 11 siblings, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot This driver accesses to processor's register via __REG macros, that are removed (or are planned to be removed) and replaced by C structures. This patches replaces all occurrencies of __REG macros. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> --- drivers/i2c/mxc_i2c.c | 68 ++++++++++++++++++++++++++++++------------------ 1 files changed, 42 insertions(+), 26 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 7f669ff..eead502 100755 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/io.h> #if defined(CONFIG_HARD_I2C) @@ -81,15 +82,26 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; +static inline void i2c_reset(void) +{ + writew(0, I2C_BASE + I2CR); /* Reset module */ + writew(0, I2C_BASE + I2SR); + writew(I2CR_IEN, I2C_BASE + I2CR); +} + void i2c_init(int speed, int unused) { int freq; int i; #if defined(CONFIG_MX31) + struct clock_control_regs *sc_regs = + (struct clock_control_regs *)CCM_BASE; + freq = mx31_get_ipg_clk(); /* start the required I2C clock */ - __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET); + writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), + &sc_regs->cgr0); #else freq = mxc_get_clock(MXC_IPG_PERCLK); #endif @@ -100,28 +112,26 @@ void i2c_init(int speed, int unused) DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + IFDR) = i; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2SR) = 0; + writew(i, I2C_BASE + IFDR); + i2c_reset(); } static int wait_busy(void) { int timeout = 10000; - while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + while (!(readw(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) udelay(1); - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + writew(0, I2C_BASE + I2SR); /* clear interrupt */ return timeout; } static int tx_byte(u8 byte) { - __REG16(I2C_BASE + I2DR) = byte; + writew(byte, I2C_BASE + I2DR); - if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_busy() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) return -1; return 0; } @@ -131,27 +141,27 @@ static int rx_byte(void) if (!wait_busy()) return -1; - return __REG16(I2C_BASE + I2DR); + return readw(I2C_BASE + I2DR); } int i2c_probe(uchar chip) { int ret; - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(0, I2C_BASE + I2CR); /* Reset module */ + writew(I2CR_IEN, I2C_BASE + I2CR); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); ret = tx_byte(chip << 1); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR); return ret; } static int i2c_addr(uchar chip, uint addr, int alen) { - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + writew(0, I2C_BASE + I2SR); + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); if (tx_byte(chip << 1)) return -1; @@ -167,35 +177,40 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) int timeout = 10000; int ret; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __FUNCTION__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) { printf("i2c_addr failed\n"); return -1; } - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR); if (tx_byte(chip << 1 | 1)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); + writew(I2CR_IEN | I2CR_MSTA | + ((len == 1) ? I2CR_TX_NO_AK : 0), + I2C_BASE + I2CR); - ret = __REG16(I2C_BASE + I2DR); + ret = readw(I2C_BASE + I2DR); while (len--) { if ((ret = rx_byte()) < 0) return -1; *buf++ = ret; if (len <= 1) - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; + writew(I2CR_IEN | I2CR_MSTA | + I2CR_TX_NO_AK, + I2C_BASE + I2CR); } wait_busy(); - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(I2CR_IEN, I2C_BASE + I2CR); - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; @@ -204,7 +219,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) { int timeout = 10000; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __FUNCTION__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) return -1; @@ -213,9 +229,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) if (tx_byte(*buf++)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(I2CR_IEN, I2C_BASE + I2CR); - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access 2011-01-20 8:46 ` [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access Stefano Babic @ 2011-01-20 9:27 ` Wolfgang Denk 2011-01-20 10:23 ` Stefano Babic 2011-01-20 17:50 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:27 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-5-git-send-email-sbabic@denx.de> you wrote: > This driver accesses to processor's register > via __REG macros, that are removed (or are planned > to be removed) and replaced by C structures. > This patches replaces all occurrencies of __REG macros. Checkpatch says: total: 0 errors, 2 warnings, 169 lines checked Please have a look. ... > @@ -204,7 +219,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) > int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) > { > int timeout = 10000; > - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); > + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", > + __FUNCTION__, chip, addr, alen, len); While touching this anyway, can we please convert the DPRINTF() into debug() ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "Summit meetings tend to be like panda matings. The expectations are always high, and the results usually disappointing." - Robert Orben ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access 2011-01-20 9:27 ` Wolfgang Denk @ 2011-01-20 10:23 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:23 UTC (permalink / raw) To: u-boot On 01/20/2011 10:27 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-5-git-send-email-sbabic@denx.de> you wrote: >> This driver accesses to processor's register >> via __REG macros, that are removed (or are planned >> to be removed) and replaced by C structures. >> This patches replaces all occurrencies of __REG macros. > > Checkpatch says: > > total: 0 errors, 2 warnings, 169 lines checked I have seen, but because __FUNCTION__is generally used, I have not replaced the occurrencies with the suggested __func__. At least, not in this patch. I think it is should be done in a separate patch (I will do in next post). >> @@ -204,7 +219,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) >> int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) >> { >> int timeout = 10000; >> - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); >> + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", >> + __FUNCTION__, chip, addr, alen, len); > > While touching this anyway, can we please convert the DPRINTF() into > debug() ? You missed the following patch that removes the ugly private debug functions.. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 04/11] I2C: mxc_i2c: get rid of __REG access 2011-01-20 8:46 ` [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access Stefano Babic 2011-01-20 9:27 ` Wolfgang Denk @ 2011-01-20 17:50 ` Stefano Babic 2011-01-21 6:30 ` Heiko Schocher 1 sibling, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 17:50 UTC (permalink / raw) To: u-boot This driver accesses to processor's register via __REG macros, that are removed (or are planned to be removed) and replaced by C structures. This patches replaces all occurrencies of __REG macros. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> --- Changes: - fix code styling issues - replace __FUNCTION__ with __func__ drivers/i2c/mxc_i2c.c | 72 ++++++++++++++++++++++++++++++------------------- 1 files changed, 44 insertions(+), 28 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 7f669ff..fd6db18 100755 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/io.h> #if defined(CONFIG_HARD_I2C) @@ -81,15 +82,26 @@ static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; +static inline void i2c_reset(void) +{ + writew(0, I2C_BASE + I2CR); /* Reset module */ + writew(0, I2C_BASE + I2SR); + writew(I2CR_IEN, I2C_BASE + I2CR); +} + void i2c_init(int speed, int unused) { int freq; int i; #if defined(CONFIG_MX31) + struct clock_control_regs *sc_regs = + (struct clock_control_regs *)CCM_BASE; + freq = mx31_get_ipg_clk(); /* start the required I2C clock */ - __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET); + writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), + &sc_regs->cgr0); #else freq = mxc_get_clock(MXC_IPG_PERCLK); #endif @@ -98,30 +110,28 @@ void i2c_init(int speed, int unused) if (freq / div[i] <= speed) break; - DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); + debug("%s: speed: %d\n", __func__, speed); - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + IFDR) = i; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2SR) = 0; + writew(i, I2C_BASE + IFDR); + i2c_reset(); } static int wait_busy(void) { int timeout = 10000; - while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + while (!(readw(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) udelay(1); - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + writew(0, I2C_BASE + I2SR); /* clear interrupt */ return timeout; } static int tx_byte(u8 byte) { - __REG16(I2C_BASE + I2DR) = byte; + writew(byte, I2C_BASE + I2DR); - if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_busy() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) return -1; return 0; } @@ -131,27 +141,27 @@ static int rx_byte(void) if (!wait_busy()) return -1; - return __REG16(I2C_BASE + I2DR); + return readw(I2C_BASE + I2DR); } int i2c_probe(uchar chip) { int ret; - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(0, I2C_BASE + I2CR); /* Reset module */ + writew(I2CR_IEN, I2C_BASE + I2CR); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); ret = tx_byte(chip << 1); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR); return ret; } static int i2c_addr(uchar chip, uint addr, int alen) { - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + writew(0, I2C_BASE + I2SR); + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); if (tx_byte(chip << 1)) return -1; @@ -167,35 +177,40 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) int timeout = 10000; int ret; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __func__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) { printf("i2c_addr failed\n"); return -1; } - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR); if (tx_byte(chip << 1 | 1)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); + writew(I2CR_IEN | I2CR_MSTA | + ((len == 1) ? I2CR_TX_NO_AK : 0), + I2C_BASE + I2CR); - ret = __REG16(I2C_BASE + I2DR); + ret = readw(I2C_BASE + I2DR); while (len--) { if ((ret = rx_byte()) < 0) return -1; *buf++ = ret; if (len <= 1) - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; + writew(I2CR_IEN | I2CR_MSTA | + I2CR_TX_NO_AK, + I2C_BASE + I2CR); } wait_busy(); - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(I2CR_IEN, I2C_BASE + I2CR); - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; @@ -203,8 +218,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + int timeout = I2C_MAX_TIMEOUT; + debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __func__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) return -1; @@ -213,9 +229,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) if (tx_byte(*buf++)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + writew(I2CR_IEN, I2C_BASE + I2CR); - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 04/11] I2C: mxc_i2c: get rid of __REG access 2011-01-20 17:50 ` [U-Boot] [PATCH V3 " Stefano Babic @ 2011-01-21 6:30 ` Heiko Schocher 0 siblings, 0 replies; 46+ messages in thread From: Heiko Schocher @ 2011-01-21 6:30 UTC (permalink / raw) To: u-boot Hello Stefano, Stefano Babic wrote: > This driver accesses to processor's register > via __REG macros, that are removed (or are planned > to be removed) and replaced by C structures. > This patches replaces all occurrencies of __REG macros. > > Signed-off-by: Stefano Babic <sbabic@denx.de> > CC: Heiko Schocher <hs@denx.de> > --- > > Changes: > - fix code styling issues > - replace __FUNCTION__ with __func__ > > drivers/i2c/mxc_i2c.c | 72 ++++++++++++++++++++++++++++++------------------- > 1 files changed, 44 insertions(+), 28 deletions(-) Acked-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (3 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:30 ` Wolfgang Denk 2011-01-20 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 06/11] Add basic support for Freescale's mc9sdz60 Stefano Babic ` (6 subsequent siblings) 11 siblings, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot There is sporadic failures when more as one I2C slave is on the bus and the processor tries to communicate with more as one slave. The problem was seen on a mx35pdk (two I2C slaves, PMIC controller and CAN/RTC chip). Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> --- drivers/i2c/mxc_i2c.c | 93 +++++++++++++++++++++++++++++++++++++----------- 1 files changed, 71 insertions(+), 22 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index eead502..5667e68 100755 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -72,11 +72,8 @@ #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" #endif -#ifdef DEBUG -#define DPRINTF(args...) printf(args) -#else -#define DPRINTF(args...) -#endif +#define I2C_MAX_TIMEOUT 10000 +#define I2C_MAX_RETRIES 3 static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, @@ -110,37 +107,67 @@ void i2c_init(int speed, int unused) if (freq / div[i] <= speed) break; - DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); + debug("%s: speed: %d\n", __FUNCTION__, speed); writew(i, I2C_BASE + IFDR); i2c_reset(); } +static int wait_idle(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { + writew(0, I2C_BASE + I2SR); + udelay(1); + } + return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB)); +} + static int wait_busy(void) { - int timeout = 10000; + int timeout = I2C_MAX_TIMEOUT; - while (!(readw(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) udelay(1); writew(0, I2C_BASE + I2SR); /* clear interrupt */ return timeout; } +static int wait_complete(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { + writew(0, I2C_BASE + I2SR); + udelay(1); + } + udelay(200); + + writew(0, I2C_BASE + I2SR); /* clear interrupt */ + + return timeout; +} + + static int tx_byte(u8 byte) { writew(byte, I2C_BASE + I2DR); - if (!wait_busy() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) return -1; return 0; } -static int rx_byte(void) +static int rx_byte(int last) { - if (!wait_busy()) + if (!wait_complete()) return -1; + if (last) + writew(I2CR_IEN, I2C_BASE + I2CR); + return readw(I2C_BASE + I2DR); } @@ -160,24 +187,48 @@ int i2c_probe(uchar chip) static int i2c_addr(uchar chip, uint addr, int alen) { - writew(0, I2C_BASE + I2SR); - writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); + int i, retry = 0; + for (retry = 0; retry < 3; retry++) { + if (wait_idle()) + break; + i2c_reset(); + for (i = 0; i < I2C_MAX_TIMEOUT; i++) + udelay(1); + } + if (retry >= I2C_MAX_RETRIES) { + debug("%s:bus is busy(%x)\n", + __func__, readw(I2C_BASE + I2SR)); + return -1; + } + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); - if (tx_byte(chip << 1)) + if (!wait_busy()) { + debug("%s:trigger start fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); return -1; + } + if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + debug("%s:chip address cycle fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); + return -1; + } while (alen--) - if (tx_byte((addr >> (alen * 8)) & 0xff)) + if (tx_byte((addr >> (alen * 8)) & 0xff) || + (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + debug("%s:device address cycle fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); return -1; + } return 0; } int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; + int timeout = I2C_MAX_TIMEOUT; int ret; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", __FUNCTION__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) { @@ -197,7 +248,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) ret = readw(I2C_BASE + I2DR); while (len--) { - if ((ret = rx_byte()) < 0) + if ((ret = rx_byte(len == 0)) < 0) return -1; *buf++ = ret; if (len <= 1) @@ -206,8 +257,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) I2C_BASE + I2CR); } - wait_busy(); - writew(I2CR_IEN, I2C_BASE + I2CR); while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) @@ -218,8 +267,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + int timeout = I2C_MAX_TIMEOUT; + debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", __FUNCTION__, chip, addr, alen, len); if (i2c_addr(chip, addr, alen)) -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-20 8:46 ` [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor Stefano Babic @ 2011-01-20 9:30 ` Wolfgang Denk 2011-01-20 10:27 ` Stefano Babic 2011-01-20 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:30 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-6-git-send-email-sbabic@denx.de> you wrote: > There is sporadic failures when more as one I2C slave > is on the bus and the processor tries to communicate > with more as one slave. > The problem was seen on a mx35pdk (two I2C slaves, > PMIC controller and CAN/RTC chip). Please also mention which approach the patch takes to fix this problem. Checkpatch says: total: 1 errors, 1 warnings, 166 lines checked Please have a look. > -#ifdef DEBUG > -#define DPRINTF(args...) printf(args) > -#else > -#define DPRINTF(args...) > -#endif Ah. Please forget the related comment in my previous message. But please mention this change in the commit message. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de EMACS belongs in <sys/errno.h>: Editor too big! ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-20 9:30 ` Wolfgang Denk @ 2011-01-20 10:27 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:27 UTC (permalink / raw) To: u-boot On 01/20/2011 10:30 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-6-git-send-email-sbabic@denx.de> you wrote: >> There is sporadic failures when more as one I2C slave >> is on the bus and the processor tries to communicate >> with more as one slave. >> The problem was seen on a mx35pdk (two I2C slaves, >> PMIC controller and CAN/RTC chip). > > Please also mention which approach the patch takes to fix this > problem. Ok > > Checkpatch says: > > total: 1 errors, 1 warnings, 166 lines checked I know, but I found the construct ok. checkpatch complains against using assignment in if function, even if it is large used. Again, as we have a tool to check patches, I will change to remove this issue. > > Please have a look. > >> -#ifdef DEBUG >> -#define DPRINTF(args...) printf(args) >> -#else >> -#define DPRINTF(args...) >> -#endif > > Ah. Please forget the related comment in my previous message. ...and you please forget my comment to your comment... > > But please mention this change in the commit message. I will do it. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-20 8:46 ` [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor Stefano Babic 2011-01-20 9:30 ` Wolfgang Denk @ 2011-01-20 17:51 ` Stefano Babic 2011-01-21 6:36 ` Heiko Schocher 1 sibling, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 17:51 UTC (permalink / raw) To: u-boot There is sporadic failures when more as one I2C slave is on the bus and the processor tries to communicate with more as one slave. The problem was seen on a mx35pdk (two I2C slaves, PMIC controller and CAN/RTC chip). The current driver uses the IIF bit in the status register to check if the bus is busy or not. According to the manual, this is not correct, because the IIB bit should be checked. Not only, to check if a transfer is finished must be checked the ICF bit, and this is not tested at all. This patch comes from analyse with a corresponding driver provided by Freescale as part of the LTIB tool. Comparing the two drivers, it appears that the current u-boot driver checks the wrong bits, and depending on race condition, the transfer can be successful or not. The patch gets rid also of own debug function (DPRINTF), replaced with the general debug(). Tested on Freescale mx35pdk. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> --- Changes: Wolfgang Denk: - change commit message explaining the problem and the changes - describe in commit message the drop of DPRINTF drivers/i2c/mxc_i2c.c | 86 ++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 68 insertions(+), 18 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fd6db18..c5ec486 100755 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -72,11 +72,8 @@ #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" #endif -#ifdef DEBUG -#define DPRINTF(args...) printf(args) -#else -#define DPRINTF(args...) -#endif +#define I2C_MAX_TIMEOUT 10000 +#define I2C_MAX_RETRIES 3 static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, @@ -116,31 +113,61 @@ void i2c_init(int speed, int unused) i2c_reset(); } +static int wait_idle(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { + writew(0, I2C_BASE + I2SR); + udelay(1); + } + return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB)); +} + static int wait_busy(void) { - int timeout = 10000; + int timeout = I2C_MAX_TIMEOUT; - while (!(readw(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) udelay(1); writew(0, I2C_BASE + I2SR); /* clear interrupt */ return timeout; } +static int wait_complete(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { + writew(0, I2C_BASE + I2SR); + udelay(1); + } + udelay(200); + + writew(0, I2C_BASE + I2SR); /* clear interrupt */ + + return timeout; +} + + static int tx_byte(u8 byte) { writew(byte, I2C_BASE + I2DR); - if (!wait_busy() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) return -1; return 0; } -static int rx_byte(void) +static int rx_byte(int last) { - if (!wait_busy()) + if (!wait_complete()) return -1; + if (last) + writew(I2CR_IEN, I2C_BASE + I2CR); + return readw(I2C_BASE + I2DR); } @@ -160,21 +187,45 @@ int i2c_probe(uchar chip) static int i2c_addr(uchar chip, uint addr, int alen) { - writew(0, I2C_BASE + I2SR); - writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); + int i, retry = 0; + for (retry = 0; retry < 3; retry++) { + if (wait_idle()) + break; + i2c_reset(); + for (i = 0; i < I2C_MAX_TIMEOUT; i++) + udelay(1); + } + if (retry >= I2C_MAX_RETRIES) { + debug("%s:bus is busy(%x)\n", + __func__, readw(I2C_BASE + I2SR)); + return -1; + } + writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); - if (tx_byte(chip << 1)) + if (!wait_busy()) { + debug("%s:trigger start fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); return -1; + } + if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + debug("%s:chip address cycle fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); + return -1; + } while (alen--) - if (tx_byte((addr >> (alen * 8)) & 0xff)) + if (tx_byte((addr >> (alen * 8)) & 0xff) || + (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { + debug("%s:device address cycle fail(%x)\n", + __func__, readw(I2C_BASE + I2SR)); return -1; + } return 0; } int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) { - int timeout = 10000; + int timeout = I2C_MAX_TIMEOUT; int ret; debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", @@ -197,7 +248,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) ret = readw(I2C_BASE + I2DR); while (len--) { - if ((ret = rx_byte()) < 0) + ret = rx_byte(len == 0); + if (ret < 0) return -1; *buf++ = ret; if (len <= 1) @@ -206,8 +258,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) I2C_BASE + I2CR); } - wait_busy(); - writew(I2CR_IEN, I2C_BASE + I2CR); while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-20 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic @ 2011-01-21 6:36 ` Heiko Schocher 2011-01-21 9:08 ` Stefano Babic 0 siblings, 1 reply; 46+ messages in thread From: Heiko Schocher @ 2011-01-21 6:36 UTC (permalink / raw) To: u-boot Hello Stefano, just a question ... Stefano Babic wrote: > There is sporadic failures when more as one I2C slave > is on the bus and the processor tries to communicate > with more as one slave. > The problem was seen on a mx35pdk (two I2C slaves, > PMIC controller and CAN/RTC chip). > > The current driver uses the IIF bit in the status register > to check if the bus is busy or not. According to the manual, > this is not correct, because the IIB bit should be checked. > Not only, to check if a transfer is finished must be checked > the ICF bit, and this is not tested at all. > > This patch comes from analyse with a corresponding driver > provided by Freescale as part of the LTIB tool. Comparing > the two drivers, it appears that the current u-boot driver checks > the wrong bits, and depending on race condition, the transfer > can be successful or not. > > The patch gets rid also of own debug function (DPRINTF), > replaced with the general debug(). > > Tested on Freescale mx35pdk. > > Signed-off-by: Stefano Babic <sbabic@denx.de> > CC: Heiko Schocher <hs@denx.de> > --- > Changes: > > Wolfgang Denk: > - change commit message explaining the problem > and the changes > - describe in commit message the drop of DPRINTF > > drivers/i2c/mxc_i2c.c | 86 ++++++++++++++++++++++++++++++++++++++---------- > 1 files changed, 68 insertions(+), 18 deletions(-) > > diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c > index fd6db18..c5ec486 100755 > --- a/drivers/i2c/mxc_i2c.c > +++ b/drivers/i2c/mxc_i2c.c [...] > @@ -116,31 +113,61 @@ void i2c_init(int speed, int unused) > i2c_reset(); > } > > +static int wait_idle(void) > +{ > + int timeout = I2C_MAX_TIMEOUT; > + > + while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { > + writew(0, I2C_BASE + I2SR); > + udelay(1); > + } > + return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB)); > +} > + > static int wait_busy(void) > { > - int timeout = 10000; > + int timeout = I2C_MAX_TIMEOUT; > > - while (!(readw(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) > + while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) > udelay(1); > writew(0, I2C_BASE + I2SR); /* clear interrupt */ > > return timeout; > } > > +static int wait_complete(void) > +{ > + int timeout = I2C_MAX_TIMEOUT; > + > + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { > + writew(0, I2C_BASE + I2SR); > + udelay(1); > + } > + udelay(200); Why is this delay necessary? Why exactly 200? Is this documented somewhere in the doc? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-21 6:36 ` Heiko Schocher @ 2011-01-21 9:08 ` Stefano Babic 2011-01-21 9:21 ` Heiko Schocher 0 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-21 9:08 UTC (permalink / raw) To: u-boot On 01/21/2011 07:36 AM, Heiko Schocher wrote: >> +static int wait_complete(void) >> +{ >> + int timeout = I2C_MAX_TIMEOUT; >> + >> + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { >> + writew(0, I2C_BASE + I2SR); >> + udelay(1); >> + } >> + udelay(200); > > Why is this delay necessary? Why exactly 200? Is this documented > somewhere in the doc? Rather I do not have a clear explanation. In the manual there is a hint regarding a delay that SW must introduce after setting the RSTA bit and before writing data into the I2DR register. Really this delay should be very short, but I checked removing the udelay() or decreasing the value to some uSec and it does not work. This is the output with debugging after removing the udelay call: i2c_read chip: 0x08 addr: 0x0007 alen: 1 len: 3 i2c_addr:chip address cycle fail(a1) i2c_addr failed i2c_read chip: 0x08 addr: 0x001e alen: 1 len: 3 i2c_addr:chip address cycle fail(a1) i2c_addr failed This happens in the i2_read() call, and it is the function where the RSTA bit is set. I can only presume the two things are related. I checked then with the driver provided by Freescale in the LTIB, and also in this driver a delay is set after checking transfer is completed. Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 05/11] I2C: mxc_i2c: address failure with mx35 processor 2011-01-21 9:08 ` Stefano Babic @ 2011-01-21 9:21 ` Heiko Schocher 0 siblings, 0 replies; 46+ messages in thread From: Heiko Schocher @ 2011-01-21 9:21 UTC (permalink / raw) To: u-boot Hello Stefano, Stefano Babic wrote: > On 01/21/2011 07:36 AM, Heiko Schocher wrote: >>> +static int wait_complete(void) >>> +{ >>> + int timeout = I2C_MAX_TIMEOUT; >>> + >>> + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { >>> + writew(0, I2C_BASE + I2SR); >>> + udelay(1); >>> + } >>> + udelay(200); >> Why is this delay necessary? Why exactly 200? Is this documented >> somewhere in the doc? > > Rather I do not have a clear explanation. In the manual there is a hint > regarding a delay that SW must introduce after setting the RSTA bit and > before writing data into the I2DR register. Really this delay should be > very short, but I checked removing the udelay() or decreasing the value > to some uSec and it does not work. > > This is the output with debugging after removing the udelay call: > > i2c_read chip: 0x08 addr: 0x0007 alen: 1 len: 3 > i2c_addr:chip address cycle fail(a1) > i2c_addr failed > i2c_read chip: 0x08 addr: 0x001e alen: 1 len: 3 > i2c_addr:chip address cycle fail(a1) > i2c_addr failed > > This happens in the i2_read() call, and it is the function where the > RSTA bit is set. I can only presume the two things are related. > I checked then with the driver provided by Freescale in the LTIB, and > also in this driver a delay is set after checking transfer is completed. Thanks for the explanation, so: Acked-by: Heiko Schocher <hs@denx.de> bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 06/11] Add basic support for Freescale's mc9sdz60 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (4 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 07/11] SPI: mxc_spi: add support for i.MX35 processor Stefano Babic ` (5 subsequent siblings) 11 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot The patch adds helper funtions for basic access to the registers of the MC9sdz60 chip (multifunctional device with RTC and CAN) via I2C interface. Signed-off-by: Stefano Babic <sbabic@denx.de> --- drivers/misc/Makefile | 5 ++- drivers/misc/mc9sdz60.c | 51 ++++++++++++++++++++++++++++ include/mc9sdz60.h | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/mc9sdz60.c create mode 100644 include/mc9sdz60.h diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a76bd4e..b152486 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -28,12 +28,13 @@ LIB := $(obj)libmisc.o COBJS-$(CONFIG_ALI152X) += ali512x.o COBJS-$(CONFIG_DS4510) += ds4510.o COBJS-$(CONFIG_FSL_LAW) += fsl_law.o +COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o COBJS-$(CONFIG_GPIO_LED) += gpio_led.o +COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o COBJS-$(CONFIG_NS87308) += ns87308.o +COBJS-$(CONFIG_PDSP188x) += pdsp188x.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o -COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o -COBJS-$(CONFIG_PDSP188x) += pdsp188x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/mc9sdz60.c b/drivers/misc/mc9sdz60.c new file mode 100644 index 0000000..439d5a6 --- /dev/null +++ b/drivers/misc/mc9sdz60.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 Stefano Babic <sbabic@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <common.h> +#include <asm/errno.h> +#include <linux/types.h> +#include <i2c.h> +#include <mc9sdz60.h> + +#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR +#error "You have to configure I2C address for MC9SDZ60" +#endif + + +u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg) +{ + u8 val; + + if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) { + puts("Error reading MC9SDZ60 register\n"); + return -1; + } + + return val; +} + +void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val) +{ + i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1); +} diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h new file mode 100644 index 0000000..31b894c --- /dev/null +++ b/include/mc9sdz60.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> + * + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_MC9SDZ60_H +#define __ASM_ARCH_MC9SDZ60_H + +/** + * Register addresses for the MC9SDZ60 + * + * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h + * but not include/linux/mfd/mc9s08dz60/pmic.h + * + */ +enum mc9sdz60_reg { + MC9SDZ60_REG_VERSION = 0x00, + /* reserved 0x01 */ + MC9SDZ60_REG_SECS = 0x02, + MC9SDZ60_REG_MINS = 0x03, + MC9SDZ60_REG_HRS = 0x04, + MC9SDZ60_REG_DAY = 0x05, + MC9SDZ60_REG_DATE = 0x06, + MC9SDZ60_REG_MONTH = 0x07, + MC9SDZ60_REG_YEAR = 0x08, + MC9SDZ60_REG_ALARM_SECS = 0x09, + MC9SDZ60_REG_ALARM_MINS = 0x0a, + MC9SDZ60_REG_ALARM_HRS = 0x0b, + /* reserved 0x0c */ + /* reserved 0x0d */ + MC9SDZ60_REG_TS_CONTROL = 0x0e, + MC9SDZ60_REG_X_LOW = 0x0f, + MC9SDZ60_REG_Y_LOW = 0x10, + MC9SDZ60_REG_XY_HIGH = 0x11, + MC9SDZ60_REG_X_LEFT_LOW = 0x12, + MC9SDZ60_REG_X_LEFT_HIGH = 0x13, + MC9SDZ60_REG_X_RIGHT = 0x14, + MC9SDZ60_REG_Y_TOP_LOW = 0x15, + MC9SDZ60_REG_Y_TOP_HIGH = 0x16, + MC9SDZ60_REG_Y_BOTTOM = 0x17, + /* reserved 0x18 */ + /* reserved 0x19 */ + MC9SDZ60_REG_RESET_1 = 0x1a, + MC9SDZ60_REG_RESET_2 = 0x1b, + MC9SDZ60_REG_POWER_CTL = 0x1c, + MC9SDZ60_REG_DELAY_CONFIG = 0x1d, + /* reserved 0x1e */ + /* reserved 0x1f */ + MC9SDZ60_REG_GPIO_1 = 0x20, + MC9SDZ60_REG_GPIO_2 = 0x21, + MC9SDZ60_REG_KPD_1 = 0x22, + MC9SDZ60_REG_KPD_2 = 0x23, + MC9SDZ60_REG_KPD_CONTROL = 0x24, + MC9SDZ60_REG_INT_ENABLE_1 = 0x25, + MC9SDZ60_REG_INT_ENABLE_2 = 0x26, + MC9SDZ60_REG_INT_FLAG_1 = 0x27, + MC9SDZ60_REG_INT_FLAG_2 = 0x28, + MC9SDZ60_REG_DES_FLAG = 0x29, +}; + +extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg); +extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val); + +#endif /* __ASM_ARCH_MC9SDZ60_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 07/11] SPI: mxc_spi: add support for i.MX35 processor 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (5 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 06/11] Add basic support for Freescale's mc9sdz60 Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case Stefano Babic ` (4 subsequent siblings) 11 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot Signed-off-by: Stefano Babic <sbabic@denx.de> --- drivers/spi/mxc_spi.c | 96 ++++++++++++++++++++++++++++++++++++------------ 1 files changed, 72 insertions(+), 24 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index d558137..5670714 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -70,6 +70,8 @@ static unsigned long spi_bases[] = { 0x53f84000, }; +#define mxc_get_clock(x) mx31_get_ipg_clk() + #elif defined(CONFIG_MX51) #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> @@ -111,6 +113,45 @@ static unsigned long spi_bases[] = { CSPI2_BASE_ADDR, CSPI3_BASE_ADDR, }; + +#elif defined(CONFIG_MX35) + +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPIINT 0x0C +#define MXC_CSPIDMA 0x10 +#define MXC_CSPISTAT 0x14 +#define MXC_CSPIPERIOD 0x18 +#define MXC_CSPITEST 0x1C +#define MXC_CSPIRESET 0x00 + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +static unsigned long spi_bases[] = { + 0x43fa4000, + 0x50010000, +}; + #else #error "Unsupported architecture" #endif @@ -158,8 +199,35 @@ void spi_cs_deactivate(struct spi_slave *slave) !(mxcs->ss_pol)); } -#ifdef CONFIG_MX51 -static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, +#if defined(CONFIG_MX31) || defined(CONFIG_MX35) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + unsigned int ctrl_reg; + + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | + MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | + MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_EN | +#ifdef CONFIG_MX35 + MXC_CSPICTRL_SSCTL | +#endif + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) + ctrl_reg |= MXC_CSPICTRL_PHA; + if (mode & SPI_CPOL) + ctrl_reg |= MXC_CSPICTRL_POL; + if (mode & SPI_CS_HIGH) + ctrl_reg |= MXC_CSPICTRL_SSPOL; + mxcs->ctrl_reg = ctrl_reg; + + return 0; +} +#endif + +#if defined(CONFIG_MX51) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); @@ -227,7 +295,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, /* * Configuration register setup - * The MX51 has support different setup for each SS + * The MX51 supports different setup for each SS */ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | (ss_pol << (cs + MXC_CSPICON_SSPOL)); @@ -363,7 +431,6 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, } - int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -441,7 +508,6 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - unsigned int ctrl_reg; struct mxc_spi_slave *mxcs; int ret; @@ -467,30 +533,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->base = spi_bases[bus]; mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; -#ifdef CONFIG_MX51 - /* Can be used for i.MX31 too ? */ - ctrl_reg = 0; - ret = spi_cfg(mxcs, cs, max_hz, mode); + ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); if (ret) { printf("mxc_spi: cannot setup SPI controller\n"); free(mxcs); return NULL; } -#else - ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | - MXC_CSPICTRL_BITCOUNT(31) | - MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ - MXC_CSPICTRL_EN | - MXC_CSPICTRL_MODE; - - if (mode & SPI_CPHA) - ctrl_reg |= MXC_CSPICTRL_PHA; - if (mode & SPI_CPOL) - ctrl_reg |= MXC_CSPICTRL_POL; - if (mode & SPI_CS_HIGH) - ctrl_reg |= MXC_CSPICTRL_SSPOL; - mxcs->ctrl_reg = ctrl_reg; -#endif return &mxcs->slave; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (6 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 07/11] SPI: mxc_spi: add support for i.MX35 processor Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:32 ` Wolfgang Denk 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver Stefano Babic ` (3 subsequent siblings) 11 siblings, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot From: Anatolij Gustschin <agust@denx.de> We need to shift only one time in each cycle in the swapping loop for unaligned tx case. Currently two byte shift operations are performed in each loop cycle causing zero gaps in the transmited data, so not all data scheduled for transmition is actually transmited. The proper swapping in unaligned rx case is missing, so add it as we need to put the received data into the rx buffer in the correct byte order. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> --- drivers/spi/mxc_spi.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5670714..3e99afd 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -372,7 +372,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, /* Buffer is not 32-bit aligned */ if ((unsigned long)dout & 0x03) { data = 0; - for (i = 0; i < 4; i++, data <<= 8) { + for (i = 0; i < 4; i++) { data = (data << 8) | (*dout++ & 0xFF); } } else { @@ -405,11 +405,11 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, if (bitlen % 32) { data = reg_read(mxcs->base + MXC_CSPIRXDATA); cnt = (bitlen % 32) / 8; + data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); debug("SPI Rx unaligned: 0x%x\n", data); if (din) { - for (i = 0; i < cnt; i++, data >>= 8) { - *din++ = data & 0xFF; - } + memcpy(din, &data, cnt); + din += cnt; } nbytes -= cnt; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 8:46 ` [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case Stefano Babic @ 2011-01-20 9:32 ` Wolfgang Denk 2011-01-20 10:29 ` Stefano Babic 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:32 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-9-git-send-email-sbabic@denx.de> you wrote: > From: Anatolij Gustschin <agust@denx.de> > > We need to shift only one time in each cycle in the swapping loop > for unaligned tx case. Currently two byte shift operations are > performed in each loop cycle causing zero gaps in the transmited > data, so not all data scheduled for transmition is actually > transmited. > > The proper swapping in unaligned rx case is missing, so add it > as we need to put the received data into the rx buffer in the > correct byte order. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> > Tested-by: Stefano Babic <sbabic@denx.de> Checkpatch says: [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add total: 0 errors, 1 warnings, 22 lines checked Please have a look. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de The complexity of software is an essential property, not an acciden- tal one. Hence, descriptions of a software entity that abstract away its complexity often abstract away its essence. - Fred Brooks, Jr. ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 9:32 ` Wolfgang Denk @ 2011-01-20 10:29 ` Stefano Babic 2011-01-20 11:59 ` Wolfgang Denk 0 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:29 UTC (permalink / raw) To: u-boot On 01/20/2011 10:32 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-9-git-send-email-sbabic@denx.de> you wrote: >> From: Anatolij Gustschin <agust@denx.de> >> >> We need to shift only one time in each cycle in the swapping loop >> for unaligned tx case. Currently two byte shift operations are >> performed in each loop cycle causing zero gaps in the transmited >> data, so not all data scheduled for transmition is actually >> transmited. >> >> The proper swapping in unaligned rx case is missing, so add it >> as we need to put the received data into the rx buffer in the >> correct byte order. >> >> Signed-off-by: Anatolij Gustschin <agust@denx.de> >> Tested-by: Stefano Babic <sbabic@denx.de> > > Checkpatch says: > > [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add > total: 0 errors, 1 warnings, 22 lines checked WARNING: braces {} are not necessary for single statement blocks #31: FILE: drivers/spi/mxc_spi.c:375: + for (i = 0; i < 4; i++) { data = (data << 8) | (*dout++ & 0xFF); } total: 0 errors, 1 warnings, 22 lines checked This is exactly what you prefer, but checkpatch complains. IMHO I prefer to fix in this patch removing braces, and do not change in previous patches where you suggest to add braces (and then checkpatch will complain about it). Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 10:29 ` Stefano Babic @ 2011-01-20 11:59 ` Wolfgang Denk 0 siblings, 0 replies; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 11:59 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <4D380E7F.60506@denx.de> you wrote: > > > [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add > > total: 0 errors, 1 warnings, 22 lines checked > > WARNING: braces {} are not necessary for single statement blocks > #31: FILE: drivers/spi/mxc_spi.c:375: > + for (i = 0; i < 4; i++) { > data = (data << 8) | (*dout++ & 0xFF); > } > > total: 0 errors, 1 warnings, 22 lines checked > > This is exactly what you prefer, but checkpatch complains. IMHO I prefer > to fix in this patch removing braces, and do not change in previous > patches where you suggest to add braces (and then checkpatch will > complain about it). These are two _different_ situations. Here we have a single statement on a single line. This needs no braces. In the other case, we had a single stament split over multiple lines, and with multiple lines I want to see braces. And checkpatch appears to be happy with braces then, too (and without as well). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "Ada is PL/I trying to be Smalltalk. - Codoso diBlini ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 8:46 ` [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case Stefano Babic 2011-01-20 9:32 ` Wolfgang Denk @ 2011-01-20 17:53 ` Stefano Babic 2011-02-01 17:53 ` Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 17:53 UTC (permalink / raw) To: u-boot From: Anatolij Gustschin <agust@denx.de> We need to shift only one time in each cycle in the swapping loop for unaligned tx case. Currently two byte shift operations are performed in each loop cycle causing zero gaps in the transmited data, so not all data scheduled for transmition is actually transmited. The proper swapping in unaligned rx case is missing, so add it as we need to put the received data into the rx buffer in the correct byte order. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> --- Changes: - code styling drivers/spi/mxc_spi.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5670714..dadf228 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -372,9 +372,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, /* Buffer is not 32-bit aligned */ if ((unsigned long)dout & 0x03) { data = 0; - for (i = 0; i < 4; i++, data <<= 8) { + for (i = 0; i < 4; i++) data = (data << 8) | (*dout++ & 0xFF); - } } else { data = *(u32 *)dout; data = cpu_to_be32(data); @@ -405,11 +404,11 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, if (bitlen % 32) { data = reg_read(mxcs->base + MXC_CSPIRXDATA); cnt = (bitlen % 32) / 8; + data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); debug("SPI Rx unaligned: 0x%x\n", data); if (din) { - for (i = 0; i < cnt; i++, data >>= 8) { - *din++ = data & 0xFF; - } + memcpy(din, &data, cnt); + din += cnt; } nbytes -= cnt; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic @ 2011-02-01 17:53 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-02-01 17:53 UTC (permalink / raw) To: u-boot On 01/20/2011 06:53 PM, Stefano Babic wrote: > From: Anatolij Gustschin <agust@denx.de> > > We need to shift only one time in each cycle in the swapping loop > for unaligned tx case. Currently two byte shift operations are > performed in each loop cycle causing zero gaps in the transmited > data, so not all data scheduled for transmition is actually > transmited. > > The proper swapping in unaligned rx case is missing, so add it > as we need to put the received data into the rx buffer in the > correct byte order. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> > Tested-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-imx, thanks Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (7 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-02-01 17:58 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures Stefano Babic ` (2 subsequent siblings) 11 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot From: Anatolij Gustschin <agust@denx.de> The MXC SPI driver didn't calculate the SPI clock up to now and just used highest possible divider 512 for DATA RATE in the control register. This results in very low transfer rates. The patch adds code to calculate and setup the SPI clock frequency for transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de> --- Changes: Sergei Shtylyov: - fix commit message drivers/spi/mxc_spi.c | 23 ++++++++++++++++++++++- 1 files changed, 22 insertions(+), 1 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 3e99afd..ee7675b 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -199,15 +199,36 @@ void spi_cs_deactivate(struct spi_slave *slave) !(mxcs->ss_pol)); } +u32 get_cspi_div(u32 div) +{ + int i; + + for (i = 0; i < 8; i++) { + if (div <= (4 << i)) + return i; + } + return i; +} + #if defined(CONFIG_MX31) || defined(CONFIG_MX35) static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { unsigned int ctrl_reg; + u32 clk_src; + u32 div; + + clk_src = mxc_get_clock(MXC_CSPI_CLK); + + div = clk_src / max_hz; + div = get_cspi_div(div); + + debug("clk %d Hz, div %d, real clk %d Hz\n", + max_hz, div, clk_src / (4 << div)); ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | - MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_DATARATE(div) | MXC_CSPICTRL_EN | #ifdef CONFIG_MX35 MXC_CSPICTRL_SSCTL | -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver 2011-01-20 8:46 ` [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver Stefano Babic @ 2011-02-01 17:58 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-02-01 17:58 UTC (permalink / raw) To: u-boot On 01/20/2011 09:46 AM, Stefano Babic wrote: > From: Anatolij Gustschin <agust@denx.de> > > The MXC SPI driver didn't calculate the SPI clock up to > now and just used highest possible divider 512 for DATA > RATE in the control register. This results in very low > transfer rates. > > The patch adds code to calculate and setup the SPI clock > frequency for transfers. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> > Signed-off-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-imx, thanks Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (8 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:33 ` Wolfgang Denk 2011-01-20 8:46 ` [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board Stefano Babic 2011-01-20 9:52 ` [U-Boot] Adding support for MX35 Wolfgang Denk 11 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de> --- arch/arm/include/asm/arch-mx31/mx31-regs.h | 11 +++ arch/arm/include/asm/arch-mx35/imx-regs.h | 12 ++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 12 ++++ drivers/spi/mxc_spi.c | 94 ++++++++------------------- 4 files changed, 63 insertions(+), 66 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index 46ed47c..105f7d8 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -64,6 +64,17 @@ struct gpio_regs { u32 gpio_psr; }; +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +}; + #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index e96a37d..6299ba9 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -309,6 +309,18 @@ struct gpt_regs { u32 counter; /* counter */ }; +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +}; + /* Watchdog Timer (WDOG) registers */ struct wdog_regs { u16 wcr; /* Control */ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 09b69f6..a1849f8 100755 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -256,6 +256,18 @@ struct src { u32 simr; }; +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + struct iim_regs { u32 stat; u32 statm; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index ee7675b..5068788 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -36,16 +36,6 @@ #include <asm/arch/mx31.h> -#define MXC_CSPIRXDATA 0x00 -#define MXC_CSPITXDATA 0x04 -#define MXC_CSPICTRL 0x08 -#define MXC_CSPIINT 0x0C -#define MXC_CSPIDMA 0x10 -#define MXC_CSPISTAT 0x14 -#define MXC_CSPIPERIOD 0x18 -#define MXC_CSPITEST 0x1C -#define MXC_CSPIRESET 0x00 - #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) @@ -76,15 +66,6 @@ static unsigned long spi_bases[] = { #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> -#define MXC_CSPIRXDATA 0x00 -#define MXC_CSPITXDATA 0x04 -#define MXC_CSPICTRL 0x08 -#define MXC_CSPICON 0x0C -#define MXC_CSPIINT 0x10 -#define MXC_CSPIDMA 0x14 -#define MXC_CSPISTAT 0x18 -#define MXC_CSPIPERIOD 0x1C -#define MXC_CSPIRESET 0x00 #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) @@ -119,16 +100,6 @@ static unsigned long spi_bases[] = { #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> -#define MXC_CSPIRXDATA 0x00 -#define MXC_CSPITXDATA 0x04 -#define MXC_CSPICTRL 0x08 -#define MXC_CSPIINT 0x0C -#define MXC_CSPIDMA 0x10 -#define MXC_CSPISTAT 0x14 -#define MXC_CSPIPERIOD 0x18 -#define MXC_CSPITEST 0x1C -#define MXC_CSPIRESET 0x00 - #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) @@ -158,6 +129,9 @@ static unsigned long spi_bases[] = { #define OUT MXC_GPIO_DIRECTION_OUT +#define reg_read readl +#define reg_write(a, v) writel(v, a) + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -174,16 +148,6 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) return container_of(slave, struct mxc_spi_slave, slave); } -static inline u32 reg_read(unsigned long addr) -{ - return *(volatile unsigned long*)addr; -} - -static inline void reg_write(unsigned long addr, u32 val) -{ - *(volatile unsigned long*)addr = val; -} - void spi_cs_activate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); @@ -254,17 +218,18 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; if (max_hz == 0) { printf("Error: desired clock is 0\n"); return -1; } - reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); + reg_ctrl = reg_read(®s->ctrl); /* Reset spi */ - reg_write(mxcs->base + MXC_CSPICTRL, 0); - reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); + reg_write(®s->ctrl, 0); + reg_write(®s->ctrl, (reg_ctrl | 0x1)); /* * The following computation is taken directly from Freescale's code. @@ -312,7 +277,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CPHA) sclkpha = 1; - reg_config = reg_read(mxcs->base + MXC_CSPICON); + reg_config = reg_read(®s->cfg); /* * Configuration register setup @@ -326,18 +291,17 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, (sclkpha << (cs + MXC_CSPICON_PHA)); debug("reg_ctrl = 0x%x\n", reg_ctrl); - reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); + reg_write(®s->ctrl, reg_ctrl); debug("reg_config = 0x%x\n", reg_config); - reg_write(mxcs->base + MXC_CSPICON, reg_config); + reg_write(®s->cfg, reg_config); /* save config register and control register */ mxcs->ctrl_reg = reg_ctrl; mxcs->cfg_reg = reg_config; /* clear interrupt reg */ - reg_write(mxcs->base + MXC_CSPIINT, 0); - reg_write(mxcs->base + MXC_CSPISTAT, - MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + reg_write(®s->intr, 0); + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); return 0; } @@ -349,6 +313,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); int nbytes = (bitlen + 7) / 8; u32 data, cnt, i; + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; debug("%s: bitlen %d dout 0x%x din 0x%x\n", __func__, bitlen, (u32)dout, (u32)din); @@ -357,14 +322,13 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | MXC_CSPICTRL_BITCOUNT(bitlen - 1); - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); + reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); #ifdef CONFIG_MX51 - reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); + reg_write(®s->cfg, mxcs->cfg_reg); #endif /* Clear interrupt register */ - reg_write(mxcs->base + MXC_CSPISTAT, - MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); /* * The SPI controller works only with words, @@ -381,7 +345,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, } debug("Sending SPI 0x%x\n", data); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + reg_write(®s->txdata, data); nbytes -= cnt; } @@ -403,28 +367,27 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, dout += 4; } debug("Sending SPI 0x%x\n", data); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + reg_write(®s->txdata, data); nbytes -= 4; } /* FIFO is written, now starts the transfer setting the XCH bit */ - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | + reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); /* Wait until the TC (Transfer completed) bit is set */ - while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) + while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) ; /* Transfer completed, clear any pending request */ - reg_write(mxcs->base + MXC_CSPISTAT, - MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); nbytes = (bitlen + 7) / 8; cnt = nbytes % 32; if (bitlen % 32) { - data = reg_read(mxcs->base + MXC_CSPIRXDATA); + data = reg_read(®s->rxdata); cnt = (bitlen % 32) / 8; data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); debug("SPI Rx unaligned: 0x%x\n", data); @@ -437,7 +400,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, while (nbytes > 0) { u32 tmp; - tmp = reg_read(mxcs->base + MXC_CSPIRXDATA); + tmp = reg_read(®s->rxdata); data = cpu_to_be32(tmp); debug("SPI Rx: 0x%x 0x%x\n", tmp, data); cnt = min(nbytes, sizeof(data)); @@ -469,7 +432,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, spi_cs_activate(slave); while (n_bytes > 0) { - if (n_bytes < MAX_SPI_BYTES) blk_size = n_bytes; else @@ -573,13 +535,13 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; - reg_write(mxcs->base + MXC_CSPIRESET, 1); + reg_write(®s->rxdata, 1); udelay(1); - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); - reg_write(mxcs->base + MXC_CSPIPERIOD, - MXC_CSPIPERIOD_32KHZ); - reg_write(mxcs->base + MXC_CSPIINT, 0); + reg_write(®s->ctrl, mxcs->ctrl_reg); + reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); + reg_write(®s->intr, 0); return 0; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures 2011-01-20 8:46 ` [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures Stefano Babic @ 2011-01-20 9:33 ` Wolfgang Denk 2011-01-20 10:30 ` Stefano Babic 0 siblings, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:33 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-11-git-send-email-sbabic@denx.de> you wrote: > This patch cleans driver code replacing all accesses > to registers with fixed offsets with a corresponding > structure. Checkpatch says: [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with total: 3 errors, 0 warnings, 274 lines checked Please fix. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "I think trash is the most important manifestation of culture we have in my lifetime." - Johnny Legend ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures 2011-01-20 9:33 ` Wolfgang Denk @ 2011-01-20 10:30 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:30 UTC (permalink / raw) To: u-boot On 01/20/2011 10:33 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-11-git-send-email-sbabic@denx.de> you wrote: >> This patch cleans driver code replacing all accesses >> to registers with fixed offsets with a corresponding >> structure. > > Checkpatch says: > > [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with > total: 3 errors, 0 warnings, 274 lines checked > > Please fix. ok, we are clearly a problem using checkpatch: checkpatch.pl --no-tree 0010-SPI-mxc_spi-replace-fixed-offsets-with-structures.patch total: 0 errors, 0 warnings, 274 lines checked 0010-SPI-mxc_spi-replace-fixed-offsets-with-structures.patch has no obvious style problems and is ready for submission. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (9 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures Stefano Babic @ 2011-01-20 8:46 ` Stefano Babic 2011-01-20 9:41 ` Wolfgang Denk 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 9:52 ` [U-Boot] Adding support for MX35 Wolfgang Denk 11 siblings, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 8:46 UTC (permalink / raw) To: u-boot The patch adds suupport for the Freescale's mx35pdk board (known as well as mx35_3stack). The board boots from the NOR flash. Following devices are supported: - two ethernet devices (FEC and SMC911x on debug board) - I2C - PMIC (MC13892) via I2C interface - UART - NOR flash (64MB) - NAND flash (2GB) - basic access to mc9sdz60 registers via I2C interface Signed-off-by: Stefano Babic <sbabic@denx.de> --- MAINTAINERS | 3 +- board/freescale/mx35pdk/Makefile | 49 ++++ board/freescale/mx35pdk/lowlevel_init.S | 363 +++++++++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.c | 309 ++++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.h | 101 +++++++++ boards.cfg | 1 + doc/README.mx35pdk | 188 ++++++++++++++++ include/configs/mx35pdk.h | 303 ++++++++++++++++++++++++++ 8 files changed, 1316 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mx35pdk/Makefile create mode 100644 board/freescale/mx35pdk/lowlevel_init.S create mode 100644 board/freescale/mx35pdk/mx35pdk.c create mode 100644 board/freescale/mx35pdk/mx35pdk.h create mode 100644 doc/README.mx35pdk create mode 100644 include/configs/mx35pdk.h diff --git a/MAINTAINERS b/MAINTAINERS index 79aa596..0c3ddc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -552,9 +552,10 @@ Rowel Atienza <rowel@diwalabs.com> Stefano Babic <sbabic@denx.de> ea20 davinci + mx35pdk i.MX35 + mx51evk i.MX51 polaris xscale trizepsiv xscale - mx51evk i.MX51 vision2 i.MX51 Jason Liu <r64343@freescale.com> diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile new file mode 100644 index 0000000..b4a60d6 --- /dev/null +++ b/board/freescale/mx35pdk/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx35pdk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S new file mode 100644 index 0000000..241cb41 --- /dev/null +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> +#include "mx35pdk.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp + ldr \tmp, =IIM_BASE_ADDR + ldr \ret, [\tmp, #IIM_SREV] + cmp \ret, #0x00 + moveq \tmp, #ROMPATCH_REV + ldreq \ret, [\tmp] + moveq \ret, \ret, lsl #4 + addne \ret, \ret, #0x10 +.endm + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + */ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm + +/* CPLD on CS5 setup */ +.macro init_debug_board + ldr r0, =DBG_BASE_ADDR + ldr r1, =DBG_CSCR_U_CONFIG + str r1, [r0, #0x00] + ldr r1, =DBG_CSCR_L_CONFIG + str r1, [r0, #0x04] + ldr r1, =DBG_CSCR_A_CONFIG + str r1, [r0, #0x08] +.endm + +/* clock setup */ +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* default CLKO to 1/32 of the ARM core*/ + ldr r1, [r0, #CLKCTL_COSR] + bic r1, r1, #0x00000FF00 + bic r1, r1, #0x0000000FF + mov r2, #0x00006C00 + add r2, r2, #0x67 + orr r1, r1, r2 + str r1, [r0, #CLKCTL_COSR] + + ldr r2, =CCM_CCMR_CONFIG + str r2, [r0, #CLKCTL_CCMR] + + check_soc_version r1, r2 + cmp r1, #CHIP_REV_2_0 + ldrhs r3, =CCM_MPLL_532_HZ + bhs 1f + ldr r2, [r0, #CLKCTL_PDR0] + tst r2, #CLKMODE_CONSUMER + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ +1: + str r3, [r0, #CLKCTL_MPCTL] + + ldr r1, =CCM_PPLL_300_HZ + str r1, [r0, #CLKCTL_PPCTL] + + ldr r1, =CCM_PDR0_CONFIG + bic r1, r1, #0x800000 + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, [r0, #CLKCTL_CGR0] + orr r1, r1, #0x0C300000 + str r1, [r0, #CLKCTL_CGR0] + + ldr r1, [r0, #CLKCTL_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CLKCTL_CGR1] +.endm + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /*ip(r12) has used to save lr register in upper calling*/ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + +1: + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] +.endm + +.globl lowlevel_init +lowlevel_init: + mov r10, lr + + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) + + /* Set unaligned access enable */ + orr r1, r1, #(1<<22) + + /* Set low int latency enable */ + orr r1, r1, #(1<<21) + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + + /* Set branch prediction enable */ + mcr 15, 0, r0, c15, c2, 4 + + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* + * initializes very early AIPS + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF + * Also setup the Peripheral Port Remap register inside the core + */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_clock + init_debug_board + + cmp pc, #PHYS_SDRAM_1 + blo init_sdram_start + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo skip_sdram_setup + +init_sdram_start: + /*init_sdram*/ + setup_sdram + +skip_sdram_setup: + mov lr, r10 + mov pc, lr + + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base + */ +setup_sdram_bank: + mov r3, #0xE + tst r2, #0x1 + orreq r3, r3, #0x300 /*DDR2*/ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c new file mode 100644 index 0000000..0542aa3 --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> +#include <fsl_pmic.h> +#include <mc9sdz60.h> +#include <mc13892.h> +#include <linux/types.h> +#include <mxc_gpio.h> +#include <asm/arch/sys_proto.h> +#include <netdev.h> + +#ifndef BOARD_LATE_INIT +#error "BOARD_LATE_INIT must be set for this board" +#endif + +#ifndef CONFIG_BOARD_EARLY_INIT_F +#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +#endif + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return 0; +} + +static void setup_iomux_i2c(void) +{ + int pad; + + /* setup pins for I2C1 */ + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); +} + + +static void setup_iomux_spi(void) +{ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); +} + +static void setup_iomux_fec(void) +{ + int pad; + + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + + pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); +} + +int board_early_init_f(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + /* enable clocks */ + writel(readl(&ccm->cgr0) | + MXC_CCM_CGR0_EMI_MASK | + MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EPIT1_MASK, + &ccm->cgr0); + + writel(readl(&ccm->cgr1) | + MXC_CCM_CGR1_FEC_MASK | + MXC_CCM_CGR1_GPIO1_MASK | + MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | + MXC_CCM_CGR1_I2C1_MASK | + MXC_CCM_CGR1_I2C2_MASK | + MXC_CCM_CGR1_IPU_MASK, + &ccm->cgr1); + + /* Setup NAND */ + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); + + setup_iomux_i2c(); + setup_iomux_fec(); + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static inline int board_detect(void) +{ + int id; + + id = pmic_reg_read(REG_IDENTIFICATION); + + id = (id >> 6) & 0x7; + if (id == 0x7) + return 1; + return 0; +} + +u32 get_board_rev(void) +{ + int rev; + + rev = board_detect(); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +int board_late_init(void) +{ + u8 val; + u32 pmic_val; + + if (board_detect()) { + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | + MUX_CONFIG_ALT1); + + pmic_val = pmic_reg_read(REG_SETTING_0); + pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); + pmic_val = pmic_reg_read(REG_MODE_0); + pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); + + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); + + mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(37, 1); + } + + val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; + mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); + mdelay(200); + + val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + mdelay(200); + + val |= 0x80; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + + return 0; +} + +int checkboard(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + puts("Board: MX35 PDK "); + + /* + * Be sure that I2C is initialized to check + * the board revision + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /* Print board revision */ + puts(board_detect() ? "2.0" : "1.0"); + + /* Print CPU revision */ + puts(" i.MX35 "); + if (get_cpu_rev() & CHIP_REV_2_0) + puts("2.0 ["); + else + puts("1.0 ["); + + switch (readl(&ccm->rcsr) & 0x0F) { + case 0x0000: + puts("POR"); + break; + case 0x0002: + puts("JTAG"); + break; + case 0x0004: + puts("RST"); + break; + case 0x0008: + puts("WDT"); + break; + default: + puts("unknown"); + } + puts("]\n"); + + printf("board rev : 0x%x\n", get_board_rev()); + + return 0; +} + +#if defined(CONFIG_SMC911X) +extern int smc911x_initialize(u8 dev_num, int base_addr); +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} + diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h new file mode 100644 index 0000000..409aeb2 --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.h @@ -0,0 +1,101 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00801000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/* MEMORY SETTING */ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/boards.cfg b/boards.cfg index d312ee8..6fb3882 100644 --- a/boards.cfg +++ b/boards.cfg @@ -38,6 +38,7 @@ qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 imx31_litekit arm arm1136 - logicpd mx31 +mx35pdk arm arm1136 - freescale mx35 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x armadillo arm arm720t diff --git a/doc/README.mx35pdk b/doc/README.mx35pdk new file mode 100644 index 0000000..3d69ed5 --- /dev/null +++ b/doc/README.mx35pdk @@ -0,0 +1,188 @@ +Overview +-------------- + +mx35pdk (known als as mx35_3stack) is a development board by Freescale. +It consists of three pluggable board: + - CPU module, with CPU, RAM, flash + - Personality board, with most interfaces (USB, Network,..) + - Debug board with JTAG header. + +The board is usually delivered with redboot. This howto explains how to boot +a linux kernel and how to replace the original bootloader with U-Boot. + +The board is delivered with Redboot on the NAND flash. It is possible to +switch the boot device with the switches SW1-SW2 on the Personality board, +and with SW5-SW10 on the Debug board. + +Delivered Redboot script to start the kernel +--------------------------------------------------- + +In redboot the following script is stored: + +fis load kernel +exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" + +Kernel is taken from flash. The image is in zImage format. + +Booting from NET, rootfs on NFS: +----------------------------------- + +To change the script in redboot: + +load -r -b 0x100000 <path_to_zImage> +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" + +If the ip address is not set, you can set it with : + +ip_address -l <board_ip/netmask> -h <server_ip> + +Linux partitions: +--------------------------- + +As default, the board is shipped with these partition tables for NAND +and for NOR: + +Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": +0x00000000-0x00100000 : "nand.bootloader" +0x00100000-0x00600000 : "nand.kernel" +0x00600000-0x06600000 : "nand.rootfs" +0x06600000-0x06e00000 : "nand.configure" +0x06e00000-0x80000000 : "nand.userfs" + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. +For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. + +However, the setup in redboot is not correct and does not use the whole flash. + +Better solution is to use the kernel parameter mtdparts. +Here the resulting script to be defined in RedBoot with fconfig: + +load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +Flashing U-Boot +-------------------------------- + +There are two options: the original bootloader in NAND can be replaced with +u-boot, or u-boot can be stored on the NOR flash without erasing +the delivered bootloader. +The boot storage can be select using the switches on the personality board +(SW1-SW2) and on the DEBUG board (SW4-SW10). + +The second option is to be preferred if you have not a JTAG debugger. +If something goes wrong flashing the bootloader, it is always possible to +recover the board booting from the other device. + +Replacing the bootloader on the NAND +-------------------------------------- +To replace RedBoot with U-Boot, the easy way is to do this in linux. +Start the kernel with the suggested options. Make sure to have set the +mtdparts exactly as described, because this matches the layout on the +mx35pdk. + +You should see in your boot log the following entries for the NAND +flash: + +5 cmdlinepart partitions found on MTD device mxc_nand +Creating 5 MTD partitions on "mxc_nand": +0x000000000000-0x000000100000 : "boot" +0x000000100000-0x000000600000 : "linux" +0x000000600000-0x000006600000 : "root" +0x000006600000-0x000006e00000 : "cfg" +0x000006e00000-0x000080000000 : "user" + +You can use the utilities flash_eraseall and nandwrite to put +u-boot on the NAND. The bootloader is marked as "boot", and 1MB is +reserved. If everything is correct, this partition is accessed as +/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and +get the device node from the partition name: + +$ cat /proc/mtd | grep boot + +I suggest you try the utilities on a different partition to be sure +if everything works correctly. If not, and you remove RedBoot, you have to +reinstall it using the ATK tool as suggested by Freescale, or using a +JTAG debugger. + +I report the versions of the utilities I used (they are provided with ELDK): + +-bash-3.2# nandwrite --version +nandwrite $Revision: 1.32 $ + +flash_eraseall --version +flash_eraseall $Revision: 1.22 $ + +nandwrite reports a warning if the file to be saved is not sector aligned. +This should have no consequences, but I preferred to pad u-boot.bin +to get no problem at all. +$ dd if=/dev/zero of=zeros bs=1 count=74800 +$ cat u-boot.bin zeros > u-boot-padded.bin + +To erase the partition: +$ flash_eraseall /dev/mtd4 + +Writing u-boot: + +$ nandwrite /dev/mtd4 u-boot-padded.bin + +Now U-Boot is stored on the booting partition. + +To boot from NAND, you have to select the switches as follows: + +Personality board + SW2 1, 4, 5 on + 2, 3, 6, 7, 8 off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 + + +Saving U-Boot in the NOR flash +--------------------------------- + +The procedure to save in the NOR flash is quite the same as to write into the NAND. + +Check the partition for boot in the NOR flash. Setting the mtdparts as reported, +the boot partition should be /dev/mtd0. + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +To erase the whole partition: +$ flash_eraseall /dev/mtd0 + +Writing u-boot: +dd if=u-boot.bin of=/dev/mtd0 + +To boot from NOR, you have to select the switches as follows: + +Personality board + SW2 all off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h new file mode 100644 index 0000000..086355b --- /dev/null +++ b/include/configs/mx35pdk.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * Configuration for the MX35pdk Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ +#define CONFIG_MX35 +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Set TEXT at the beginning of the NOR flash */ +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define CONFIG_BOARD_EARLY_INIT_F +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX35_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#define CONFIG_MXC_SPI + + +/* + * PMIC Configs + */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_I2C +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 + +/* + * MFD MC9SDZ60 + */ +#define CONFIG_FSL_MC9SDZ60 +#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 + +/* + * UART (console) + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX35_UART1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* + * Command definition + */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_NAND + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SPI +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +/* + * Ethernet on the debug board (SMC911) + */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME + +/* + * Ethernet on SOC (FEC) + */ +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \ + "96m(root),8m(cfg),1938m(user);" \ + "physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor@beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_ENV_IS_IN_FLASH + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND + #define CONFIG_ENV_OFFSET (1024 * 1024) +#endif + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER + +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ +#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ + +/* + * NAND FLASH driver setup + */ +#define CONFIG_NAND_MXC +#define CONFIG_NAND_MXC_V1_1 +#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * Default environment and default scripts + * to update uboot and load kernel + */ +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_HOSTNAME "mx35pdk" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "ethprime=smc911x\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=80800000\0" \ + "kernel_addr_r=80800000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=protect off ${uboot_addr} +40000;" \ + "erase ${uboot_addr} +40000;" \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + "bootcmd=run net_nfs\0" + +#endif /* __CONFIG_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 8:46 ` [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board Stefano Babic @ 2011-01-20 9:41 ` Wolfgang Denk 2011-01-20 10:45 ` Stefano Babic 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:41 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-12-git-send-email-sbabic@denx.de> you wrote: > The patch adds suupport for the Freescale's mx35pdk board > (known as well as mx35_3stack). Checkpatch says: [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. total: 0 errors, 1 warnings, 1331 lines checked (Prototype for smc911x_initialize() is in netdev.h). ... > +.macro init_clock > + ldr r0, =CCM_BASE_ADDR > + > + /* default CLKO to 1/32 of the ARM core*/ > + ldr r1, [r0, #CLKCTL_COSR] > + bic r1, r1, #0x00000FF00 > + bic r1, r1, #0x0000000FF > + mov r2, #0x00006C00 > + add r2, r2, #0x67 > + orr r1, r1, r2 > + str r1, [r0, #CLKCTL_COSR] > + > + ldr r2, =CCM_CCMR_CONFIG > + str r2, [r0, #CLKCTL_CCMR] > + > + check_soc_version r1, r2 > + cmp r1, #CHIP_REV_2_0 > + ldrhs r3, =CCM_MPLL_532_HZ > + bhs 1f > + ldr r2, [r0, #CLKCTL_PDR0] > + tst r2, #CLKMODE_CONSUMER > + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ > + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ etc. etc. Please use TAB for indentation. > +int checkboard(void) > +{ > + struct ccm_regs *ccm = > + (struct ccm_regs *)IMX_CCM_BASE; > + > + puts("Board: MX35 PDK "); > + > + /* > + * Be sure that I2C is initialized to check > + * the board revision > + */ > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); Error checking? > + /* Print board revision */ > + puts(board_detect() ? "2.0" : "1.0"); > + > + /* Print CPU revision */ > + puts(" i.MX35 "); I mentioned this before: If you make board_detect() return 1 or 2, you can combine the calls to puts() for example like that: printf("Board: MX35 PDK %d.0 i.MX35 ", board_detect()); > + if (get_cpu_rev() & CHIP_REV_2_0) > + puts("2.0 ["); > + else > + puts("1.0 ["); Eventually similar improvment could be done here. [Just a hint - feel free to post-pone into a later patch if this affects other boards as well.] Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Romulan women are not like Vulcan females. We are not dedicated to pure logic and the sterility of non-emotion. -- Romulan Commander, "The Enterprise Incident", stardate 5027.3 ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 9:41 ` Wolfgang Denk @ 2011-01-20 10:45 ` Stefano Babic 2011-01-20 12:03 ` Wolfgang Denk 0 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:45 UTC (permalink / raw) To: u-boot On 01/20/2011 10:41 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-12-git-send-email-sbabic@denx.de> you wrote: >> The patch adds suupport for the Freescale's mx35pdk board >> (known as well as mx35_3stack). > > Checkpatch says: > > [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. > total: 0 errors, 1 warnings, 1331 lines checked > > (Prototype for smc911x_initialize() is in netdev.h). Thanks, I have not search with attention. I fix it. > Please use TAB for indentation. Thanks - in this case checkpatch reports nothing, and I suppose everything is ok. > > >> +int checkboard(void) >> +{ >> + struct ccm_regs *ccm = >> + (struct ccm_regs *)IMX_CCM_BASE; >> + >> + puts("Board: MX35 PDK "); >> + >> + /* >> + * Be sure that I2C is initialized to check >> + * the board revision >> + */ >> + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); > > Error checking? I wil ladd it > >> + /* Print board revision */ >> + puts(board_detect() ? "2.0" : "1.0"); >> + >> + /* Print CPU revision */ >> + puts(" i.MX35 "); > > I mentioned this before: If you make board_detect() return 1 or 2, > you can combine the calls to puts() for example like that: I was unsure, it seemed to me easier to understand as it is implemented now, becaues board_detect() is used to detect if the PMIC is installed or not. It returns 0 or 1, and tell if the test for the PMIC was successful. Probably the former version of the board has no pmic at all or was not connected to I2C. So in another part of code board_detect is used in boolean form: if (board_detect()) { I thought that to combine the result makes some confusion. Probably it is clearer to use get_board_rev() instead of board_detect() and to extract the revision number from the returned u32: printf("Board: MX35 PDK %d.0 i.MX35 ", (get_board_rev() >> 8) & 0xFF); > Eventually similar improvment could be done here. [Just a hint - feel > free to post-pone into a later patch if this affects other boards as > well.] Agree, to change this I would prefer a patch for all i.MX boards at the same time. They use at the moment the same approach I use now. best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 10:45 ` Stefano Babic @ 2011-01-20 12:03 ` Wolfgang Denk 0 siblings, 0 replies; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 12:03 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <4D381237.9040309@denx.de> you wrote: > > >> + /* Print board revision */ > >> + puts(board_detect() ? "2.0" : "1.0"); > >> + > >> + /* Print CPU revision */ > >> + puts(" i.MX35 "); > > > > I mentioned this before: If you make board_detect() return 1 or 2, > > you can combine the calls to puts() for example like that: > > I was unsure, it seemed to me easier to understand as it is implemented > now, becaues board_detect() is used to detect if the PMIC is installed > or not. It returns 0 or 1, and tell if the test for the PMIC was > successful. > > Probably the former version of the board has no pmic at all or was not > connected to I2C. So in another part of code board_detect is used in > boolean form: > > if (board_detect()) { This function should be called pmic_detect() or so. > I thought that to combine the result makes some confusion. Probably it > is clearer to use get_board_rev() instead of board_detect() and to > extract the revision number from the returned u32: > > printf("Board: MX35 PDK %d.0 i.MX35 ", (get_board_rev() >> 8) & 0xFF); Agreed. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de It's certainly convenient the way the crime (or condition) of stupidity carries with it its own punishment, automatically admisistered without remorse, pity, or prejudice. :-) -- Tom Christiansen in <559seq$ag1$1@csnews.cs.colorado.edu> ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 8:46 ` [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board Stefano Babic 2011-01-20 9:41 ` Wolfgang Denk @ 2011-01-20 17:53 ` Stefano Babic 2011-01-20 18:05 ` [U-Boot] [PATCH V4 " Stefano Babic 2011-02-01 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 2 replies; 46+ messages in thread From: Stefano Babic @ 2011-01-20 17:53 UTC (permalink / raw) To: u-boot The patch adds suupport for the Freescale's mx35pdk board (known as well as mx35_3stack). The board boots from the NOR flash. Following devices are supported: - two ethernet devices (FEC and SMC911x on debug board) - I2C - PMIC (MC13892) via I2C interface - UART - NOR flash (64MB) - NAND flash (2GB) - basic access to mc9sdz60 registers via I2C interface Signed-off-by: Stefano Babic <sbabic@denx.de> --- Changes: Wolfgang Denk: - replace board_detect with a more correct name - use the output of get_board_rev to print the board revision - remove leading spaces from lowlevel_init.S MAINTAINERS | 3 +- board/freescale/mx35pdk/Makefile | 49 ++++ board/freescale/mx35pdk/lowlevel_init.S | 363 +++++++++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.c | 300 +++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.h | 101 +++++++++ boards.cfg | 1 + doc/README.mx35pdk | 188 ++++++++++++++++ include/configs/mx35pdk.h | 303 ++++++++++++++++++++++++++ 8 files changed, 1307 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mx35pdk/Makefile create mode 100644 board/freescale/mx35pdk/lowlevel_init.S create mode 100644 board/freescale/mx35pdk/mx35pdk.c create mode 100644 board/freescale/mx35pdk/mx35pdk.h create mode 100644 doc/README.mx35pdk create mode 100644 include/configs/mx35pdk.h diff --git a/MAINTAINERS b/MAINTAINERS index 79aa596..0c3ddc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -552,9 +552,10 @@ Rowel Atienza <rowel@diwalabs.com> Stefano Babic <sbabic@denx.de> ea20 davinci + mx35pdk i.MX35 + mx51evk i.MX51 polaris xscale trizepsiv xscale - mx51evk i.MX51 vision2 i.MX51 Jason Liu <r64343@freescale.com> diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile new file mode 100644 index 0000000..b4a60d6 --- /dev/null +++ b/board/freescale/mx35pdk/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx35pdk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S new file mode 100644 index 0000000..8715c8c --- /dev/null +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> +#include "mx35pdk.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp + ldr \tmp, =IIM_BASE_ADDR + ldr \ret, [\tmp, #IIM_SREV] + cmp \ret, #0x00 + moveq \tmp, #ROMPATCH_REV + ldreq \ret, [\tmp] + moveq \ret, \ret, lsl #4 + addne \ret, \ret, #0x10 +.endm + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + */ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm + +/* CPLD on CS5 setup */ +.macro init_debug_board + ldr r0, =DBG_BASE_ADDR + ldr r1, =DBG_CSCR_U_CONFIG + str r1, [r0, #0x00] + ldr r1, =DBG_CSCR_L_CONFIG + str r1, [r0, #0x04] + ldr r1, =DBG_CSCR_A_CONFIG + str r1, [r0, #0x08] +.endm + +/* clock setup */ +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* default CLKO to 1/32 of the ARM core*/ + ldr r1, [r0, #CLKCTL_COSR] + bic r1, r1, #0x00000FF00 + bic r1, r1, #0x0000000FF + mov r2, #0x00006C00 + add r2, r2, #0x67 + orr r1, r1, r2 + str r1, [r0, #CLKCTL_COSR] + + ldr r2, =CCM_CCMR_CONFIG + str r2, [r0, #CLKCTL_CCMR] + + check_soc_version r1, r2 + cmp r1, #CHIP_REV_2_0 + ldrhs r3, =CCM_MPLL_532_HZ + bhs 1f + ldr r2, [r0, #CLKCTL_PDR0] + tst r2, #CLKMODE_CONSUMER + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ +1: + str r3, [r0, #CLKCTL_MPCTL] + + ldr r1, =CCM_PPLL_300_HZ + str r1, [r0, #CLKCTL_PPCTL] + + ldr r1, =CCM_PDR0_CONFIG + bic r1, r1, #0x800000 + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, [r0, #CLKCTL_CGR0] + orr r1, r1, #0x0C300000 + str r1, [r0, #CLKCTL_CGR0] + + ldr r1, [r0, #CLKCTL_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CLKCTL_CGR1] +.endm + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /*ip(r12) has used to save lr register in upper calling*/ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + +1: + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] +.endm + +.globl lowlevel_init +lowlevel_init: + mov r10, lr + + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) + + /* Set unaligned access enable */ + orr r1, r1, #(1<<22) + + /* Set low int latency enable */ + orr r1, r1, #(1<<21) + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + + /* Set branch prediction enable */ + mcr 15, 0, r0, c15, c2, 4 + + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* + * initializes very early AIPS + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF + * Also setup the Peripheral Port Remap register inside the core + */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_clock + init_debug_board + + cmp pc, #PHYS_SDRAM_1 + blo init_sdram_start + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo skip_sdram_setup + +init_sdram_start: + /*init_sdram*/ + setup_sdram + +skip_sdram_setup: + mov lr, r10 + mov pc, lr + + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base + */ +setup_sdram_bank: + mov r3, #0xE + tst r2, #0x1 + orreq r3, r3, #0x300 /*DDR2*/ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c new file mode 100644 index 0000000..83df3bf --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> +#include <fsl_pmic.h> +#include <mc9sdz60.h> +#include <mc13892.h> +#include <linux/types.h> +#include <mxc_gpio.h> +#include <asm/arch/sys_proto.h> +#include <netdev.h> + +#ifndef BOARD_LATE_INIT +#error "BOARD_LATE_INIT must be set for this board" +#endif + +#ifndef CONFIG_BOARD_EARLY_INIT_F +#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +#endif + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return 0; +} + +static void setup_iomux_i2c(void) +{ + int pad; + + /* setup pins for I2C1 */ + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); +} + + +static void setup_iomux_spi(void) +{ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); +} + +static void setup_iomux_fec(void) +{ + int pad; + + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + + pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); +} + +int board_early_init_f(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + /* enable clocks */ + writel(readl(&ccm->cgr0) | + MXC_CCM_CGR0_EMI_MASK | + MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EPIT1_MASK, + &ccm->cgr0); + + writel(readl(&ccm->cgr1) | + MXC_CCM_CGR1_FEC_MASK | + MXC_CCM_CGR1_GPIO1_MASK | + MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | + MXC_CCM_CGR1_I2C1_MASK | + MXC_CCM_CGR1_I2C2_MASK | + MXC_CCM_CGR1_IPU_MASK, + &ccm->cgr1); + + /* Setup NAND */ + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); + + setup_iomux_i2c(); + setup_iomux_fec(); + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static inline int pmic_detect(void) +{ + int id; + + id = pmic_reg_read(REG_IDENTIFICATION); + + id = (id >> 6) & 0x7; + if (id == 0x7) + return 1; + return 0; +} + +u32 get_board_rev(void) +{ + int rev; + + rev = pmic_detect(); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +int board_late_init(void) +{ + u8 val; + u32 pmic_val; + + if (pmic_detect()) { + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | + MUX_CONFIG_ALT1); + + pmic_val = pmic_reg_read(REG_SETTING_0); + pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); + pmic_val = pmic_reg_read(REG_MODE_0); + pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); + + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); + + mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(37, 1); + } + + val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; + mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); + mdelay(200); + + val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + mdelay(200); + + val |= 0x80; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + + return 0; +} + +int checkboard(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 cpu_rev = get_cpu_rev(); + + puts("Board: MX35 PDK "); + + /* + * Be sure that I2C is initialized to check + * the board revision + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /* Print board revision */ + printf("Board: MX35 PDK %d.0 i.MX35 ", (get_board_rev() >> 8) & 0xFF); + + /* Print CPU revision */ + printf(" i.MX35 %d.%d ", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F); + + switch (readl(&ccm->rcsr) & 0x0F) { + case 0x0000: + puts("POR"); + break; + case 0x0002: + puts("JTAG"); + break; + case 0x0004: + puts("RST"); + break; + case 0x0008: + puts("WDT"); + break; + default: + puts("unknown"); + } + puts("]\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} + diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h new file mode 100644 index 0000000..409aeb2 --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.h @@ -0,0 +1,101 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00801000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/* MEMORY SETTING */ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/boards.cfg b/boards.cfg index d312ee8..6fb3882 100644 --- a/boards.cfg +++ b/boards.cfg @@ -38,6 +38,7 @@ qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 imx31_litekit arm arm1136 - logicpd mx31 +mx35pdk arm arm1136 - freescale mx35 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x armadillo arm arm720t diff --git a/doc/README.mx35pdk b/doc/README.mx35pdk new file mode 100644 index 0000000..3d69ed5 --- /dev/null +++ b/doc/README.mx35pdk @@ -0,0 +1,188 @@ +Overview +-------------- + +mx35pdk (known als as mx35_3stack) is a development board by Freescale. +It consists of three pluggable board: + - CPU module, with CPU, RAM, flash + - Personality board, with most interfaces (USB, Network,..) + - Debug board with JTAG header. + +The board is usually delivered with redboot. This howto explains how to boot +a linux kernel and how to replace the original bootloader with U-Boot. + +The board is delivered with Redboot on the NAND flash. It is possible to +switch the boot device with the switches SW1-SW2 on the Personality board, +and with SW5-SW10 on the Debug board. + +Delivered Redboot script to start the kernel +--------------------------------------------------- + +In redboot the following script is stored: + +fis load kernel +exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" + +Kernel is taken from flash. The image is in zImage format. + +Booting from NET, rootfs on NFS: +----------------------------------- + +To change the script in redboot: + +load -r -b 0x100000 <path_to_zImage> +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" + +If the ip address is not set, you can set it with : + +ip_address -l <board_ip/netmask> -h <server_ip> + +Linux partitions: +--------------------------- + +As default, the board is shipped with these partition tables for NAND +and for NOR: + +Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": +0x00000000-0x00100000 : "nand.bootloader" +0x00100000-0x00600000 : "nand.kernel" +0x00600000-0x06600000 : "nand.rootfs" +0x06600000-0x06e00000 : "nand.configure" +0x06e00000-0x80000000 : "nand.userfs" + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. +For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. + +However, the setup in redboot is not correct and does not use the whole flash. + +Better solution is to use the kernel parameter mtdparts. +Here the resulting script to be defined in RedBoot with fconfig: + +load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +Flashing U-Boot +-------------------------------- + +There are two options: the original bootloader in NAND can be replaced with +u-boot, or u-boot can be stored on the NOR flash without erasing +the delivered bootloader. +The boot storage can be select using the switches on the personality board +(SW1-SW2) and on the DEBUG board (SW4-SW10). + +The second option is to be preferred if you have not a JTAG debugger. +If something goes wrong flashing the bootloader, it is always possible to +recover the board booting from the other device. + +Replacing the bootloader on the NAND +-------------------------------------- +To replace RedBoot with U-Boot, the easy way is to do this in linux. +Start the kernel with the suggested options. Make sure to have set the +mtdparts exactly as described, because this matches the layout on the +mx35pdk. + +You should see in your boot log the following entries for the NAND +flash: + +5 cmdlinepart partitions found on MTD device mxc_nand +Creating 5 MTD partitions on "mxc_nand": +0x000000000000-0x000000100000 : "boot" +0x000000100000-0x000000600000 : "linux" +0x000000600000-0x000006600000 : "root" +0x000006600000-0x000006e00000 : "cfg" +0x000006e00000-0x000080000000 : "user" + +You can use the utilities flash_eraseall and nandwrite to put +u-boot on the NAND. The bootloader is marked as "boot", and 1MB is +reserved. If everything is correct, this partition is accessed as +/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and +get the device node from the partition name: + +$ cat /proc/mtd | grep boot + +I suggest you try the utilities on a different partition to be sure +if everything works correctly. If not, and you remove RedBoot, you have to +reinstall it using the ATK tool as suggested by Freescale, or using a +JTAG debugger. + +I report the versions of the utilities I used (they are provided with ELDK): + +-bash-3.2# nandwrite --version +nandwrite $Revision: 1.32 $ + +flash_eraseall --version +flash_eraseall $Revision: 1.22 $ + +nandwrite reports a warning if the file to be saved is not sector aligned. +This should have no consequences, but I preferred to pad u-boot.bin +to get no problem at all. +$ dd if=/dev/zero of=zeros bs=1 count=74800 +$ cat u-boot.bin zeros > u-boot-padded.bin + +To erase the partition: +$ flash_eraseall /dev/mtd4 + +Writing u-boot: + +$ nandwrite /dev/mtd4 u-boot-padded.bin + +Now U-Boot is stored on the booting partition. + +To boot from NAND, you have to select the switches as follows: + +Personality board + SW2 1, 4, 5 on + 2, 3, 6, 7, 8 off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 + + +Saving U-Boot in the NOR flash +--------------------------------- + +The procedure to save in the NOR flash is quite the same as to write into the NAND. + +Check the partition for boot in the NOR flash. Setting the mtdparts as reported, +the boot partition should be /dev/mtd0. + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +To erase the whole partition: +$ flash_eraseall /dev/mtd0 + +Writing u-boot: +dd if=u-boot.bin of=/dev/mtd0 + +To boot from NOR, you have to select the switches as follows: + +Personality board + SW2 all off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h new file mode 100644 index 0000000..086355b --- /dev/null +++ b/include/configs/mx35pdk.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * Configuration for the MX35pdk Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ +#define CONFIG_MX35 +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Set TEXT at the beginning of the NOR flash */ +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define CONFIG_BOARD_EARLY_INIT_F +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX35_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#define CONFIG_MXC_SPI + + +/* + * PMIC Configs + */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_I2C +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 + +/* + * MFD MC9SDZ60 + */ +#define CONFIG_FSL_MC9SDZ60 +#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 + +/* + * UART (console) + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX35_UART1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* + * Command definition + */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_NAND + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SPI +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +/* + * Ethernet on the debug board (SMC911) + */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME + +/* + * Ethernet on SOC (FEC) + */ +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \ + "96m(root),8m(cfg),1938m(user);" \ + "physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor@beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_ENV_IS_IN_FLASH + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND + #define CONFIG_ENV_OFFSET (1024 * 1024) +#endif + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER + +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ +#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ + +/* + * NAND FLASH driver setup + */ +#define CONFIG_NAND_MXC +#define CONFIG_NAND_MXC_V1_1 +#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * Default environment and default scripts + * to update uboot and load kernel + */ +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_HOSTNAME "mx35pdk" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "ethprime=smc911x\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=80800000\0" \ + "kernel_addr_r=80800000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=protect off ${uboot_addr} +40000;" \ + "erase ${uboot_addr} +40000;" \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + "bootcmd=run net_nfs\0" + +#endif /* __CONFIG_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V4 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic @ 2011-01-20 18:05 ` Stefano Babic 2011-02-01 17:51 ` Stefano Babic 2011-02-01 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 1 sibling, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 18:05 UTC (permalink / raw) To: u-boot The patch adds suupport for the Freescale's mx35pdk board (known as well as mx35_3stack). The board boots from the NOR flash. Following devices are supported: - two ethernet devices (FEC and SMC911x on debug board) - I2C - PMIC (MC13892) via I2C interface - UART - NOR flash (64MB) - NAND flash (2GB) - basic access to mc9sdz60 registers via I2C interface Signed-off-by: Stefano Babic <sbabic@denx.de> --- Please ignore V3 of this patch : the board version was not correctly printed. Sorry for noise. Changes: Wolfgang Denk: - replace board_detect with a more correct name - use the output of get_board_rev to print the board revision - remove leading spaces from lowlevel_init.S MAINTAINERS | 3 +- board/freescale/mx35pdk/Makefile | 49 ++++ board/freescale/mx35pdk/lowlevel_init.S | 363 +++++++++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.c | 298 +++++++++++++++++++++++++ board/freescale/mx35pdk/mx35pdk.h | 101 +++++++++ boards.cfg | 1 + doc/README.mx35pdk | 188 ++++++++++++++++ include/configs/mx35pdk.h | 303 ++++++++++++++++++++++++++ 8 files changed, 1305 insertions(+), 1 deletions(-) create mode 100644 board/freescale/mx35pdk/Makefile create mode 100644 board/freescale/mx35pdk/lowlevel_init.S create mode 100644 board/freescale/mx35pdk/mx35pdk.c create mode 100644 board/freescale/mx35pdk/mx35pdk.h create mode 100644 doc/README.mx35pdk create mode 100644 include/configs/mx35pdk.h diff --git a/MAINTAINERS b/MAINTAINERS index 79aa596..0c3ddc1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -552,9 +552,10 @@ Rowel Atienza <rowel@diwalabs.com> Stefano Babic <sbabic@denx.de> ea20 davinci + mx35pdk i.MX35 + mx51evk i.MX51 polaris xscale trizepsiv xscale - mx51evk i.MX51 vision2 i.MX51 Jason Liu <r64343@freescale.com> diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile new file mode 100644 index 0000000..b4a60d6 --- /dev/null +++ b/board/freescale/mx35pdk/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx35pdk.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S new file mode 100644 index 0000000..8715c8c --- /dev/null +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> +#include "mx35pdk.h" + +/* + * return soc version + * 0x10: TO1 + * 0x20: TO2 + * 0x30: TO3 + */ +.macro check_soc_version ret, tmp + ldr \tmp, =IIM_BASE_ADDR + ldr \ret, [\tmp, #IIM_SREV] + cmp \ret, #0x00 + moveq \tmp, #ROMPATCH_REV + ldreq \ret, [\tmp] + moveq \ret, \ret, lsl #4 + addne \ret, \ret, #0x10 +.endm + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + */ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm + +/* CPLD on CS5 setup */ +.macro init_debug_board + ldr r0, =DBG_BASE_ADDR + ldr r1, =DBG_CSCR_U_CONFIG + str r1, [r0, #0x00] + ldr r1, =DBG_CSCR_L_CONFIG + str r1, [r0, #0x04] + ldr r1, =DBG_CSCR_A_CONFIG + str r1, [r0, #0x08] +.endm + +/* clock setup */ +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* default CLKO to 1/32 of the ARM core*/ + ldr r1, [r0, #CLKCTL_COSR] + bic r1, r1, #0x00000FF00 + bic r1, r1, #0x0000000FF + mov r2, #0x00006C00 + add r2, r2, #0x67 + orr r1, r1, r2 + str r1, [r0, #CLKCTL_COSR] + + ldr r2, =CCM_CCMR_CONFIG + str r2, [r0, #CLKCTL_CCMR] + + check_soc_version r1, r2 + cmp r1, #CHIP_REV_2_0 + ldrhs r3, =CCM_MPLL_532_HZ + bhs 1f + ldr r2, [r0, #CLKCTL_PDR0] + tst r2, #CLKMODE_CONSUMER + ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ + ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ +1: + str r3, [r0, #CLKCTL_MPCTL] + + ldr r1, =CCM_PPLL_300_HZ + str r1, [r0, #CLKCTL_PPCTL] + + ldr r1, =CCM_PDR0_CONFIG + bic r1, r1, #0x800000 + str r1, [r0, #CLKCTL_PDR0] + + ldr r1, [r0, #CLKCTL_CGR0] + orr r1, r1, #0x0C300000 + str r1, [r0, #CLKCTL_CGR0] + + ldr r1, [r0, #CLKCTL_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #CLKCTL_CGR1] +.endm + +.macro setup_sdram + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /*ip(r12) has used to save lr register in upper calling*/ + mov fp, lr + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD0_BASE_ADDR + bl setup_sdram_bank + cmp r3, #0x0 + orreq r5, r5, #1 + eorne r2, r2, #0x1 + blne setup_sdram_bank + + mov lr, fp + +1: + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] +.endm + +.globl lowlevel_init +lowlevel_init: + mov r10, lr + + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) + + /* Set unaligned access enable */ + orr r1, r1, #(1<<22) + + /* Set low int latency enable */ + orr r1, r1, #(1<<21) + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + + /* Set branch prediction enable */ + mcr 15, 0, r0, c15, c2, 4 + + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* + * initializes very early AIPS + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF + * Also setup the Peripheral Port Remap register inside the core + */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_clock + init_debug_board + + cmp pc, #PHYS_SDRAM_1 + blo init_sdram_start + cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + blo skip_sdram_setup + +init_sdram_start: + /*init_sdram*/ + setup_sdram + +skip_sdram_setup: + mov lr, r10 + mov pc, lr + + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base + */ +setup_sdram_bank: + mov r3, #0xE + tst r2, #0x1 + orreq r3, r3, #0x300 /*DDR2*/ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c new file mode 100644 index 0000000..656121c --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> +#include <fsl_pmic.h> +#include <mc9sdz60.h> +#include <mc13892.h> +#include <linux/types.h> +#include <mxc_gpio.h> +#include <asm/arch/sys_proto.h> +#include <netdev.h> + +#ifndef BOARD_LATE_INIT +#error "BOARD_LATE_INIT must be set for this board" +#endif + +#ifndef CONFIG_BOARD_EARLY_INIT_F +#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +#endif + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return 0; +} + +static void setup_iomux_i2c(void) +{ + int pad; + + /* setup pins for I2C1 */ + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); +} + + +static void setup_iomux_spi(void) +{ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); +} + +static void setup_iomux_fec(void) +{ + int pad; + + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + + pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); + + mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \ + PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); +} + +int board_early_init_f(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + /* enable clocks */ + writel(readl(&ccm->cgr0) | + MXC_CCM_CGR0_EMI_MASK | + MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EPIT1_MASK, + &ccm->cgr0); + + writel(readl(&ccm->cgr1) | + MXC_CCM_CGR1_FEC_MASK | + MXC_CCM_CGR1_GPIO1_MASK | + MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | + MXC_CCM_CGR1_I2C1_MASK | + MXC_CCM_CGR1_I2C2_MASK | + MXC_CCM_CGR1_IPU_MASK, + &ccm->cgr1); + + /* Setup NAND */ + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); + + setup_iomux_i2c(); + setup_iomux_fec(); + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static inline int pmic_detect(void) +{ + int id; + + id = pmic_reg_read(REG_IDENTIFICATION); + + id = (id >> 6) & 0x7; + if (id == 0x7) + return 1; + return 0; +} + +u32 get_board_rev(void) +{ + int rev; + + rev = pmic_detect(); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +int board_late_init(void) +{ + u8 val; + u32 pmic_val; + + if (pmic_detect()) { + mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | + MUX_CONFIG_ALT1); + + pmic_val = pmic_reg_read(REG_SETTING_0); + pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); + pmic_val = pmic_reg_read(REG_MODE_0); + pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); + + mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); + mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); + + mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(37, 1); + } + + val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; + mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); + mdelay(200); + + val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + mdelay(200); + + val |= 0x80; + mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); + + return 0; +} + +int checkboard(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 cpu_rev = get_cpu_rev(); + + /* + * Be sure that I2C is initialized to check + * the board revision + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + /* Print board revision */ + printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F); + + /* Print CPU revision */ + printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F); + + switch (readl(&ccm->rcsr) & 0x0F) { + case 0x0000: + puts("POR"); + break; + case 0x0002: + puts("JTAG"); + break; + case 0x0004: + puts("RST"); + break; + case 0x0008: + puts("WDT"); + break; + default: + puts("unknown"); + } + puts("]\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + cpu_eth_init(bis); + + return rc; +} + diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h new file mode 100644 index 0000000..409aeb2 --- /dev/null +++ b/board/freescale/mx35pdk/mx35pdk.h @@ -0,0 +1,101 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00801000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/* MEMORY SETTING */ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/boards.cfg b/boards.cfg index d312ee8..6fb3882 100644 --- a/boards.cfg +++ b/boards.cfg @@ -38,6 +38,7 @@ qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 imx31_litekit arm arm1136 - logicpd mx31 +mx35pdk arm arm1136 - freescale mx35 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x armadillo arm arm720t diff --git a/doc/README.mx35pdk b/doc/README.mx35pdk new file mode 100644 index 0000000..3d69ed5 --- /dev/null +++ b/doc/README.mx35pdk @@ -0,0 +1,188 @@ +Overview +-------------- + +mx35pdk (known als as mx35_3stack) is a development board by Freescale. +It consists of three pluggable board: + - CPU module, with CPU, RAM, flash + - Personality board, with most interfaces (USB, Network,..) + - Debug board with JTAG header. + +The board is usually delivered with redboot. This howto explains how to boot +a linux kernel and how to replace the original bootloader with U-Boot. + +The board is delivered with Redboot on the NAND flash. It is possible to +switch the boot device with the switches SW1-SW2 on the Personality board, +and with SW5-SW10 on the Debug board. + +Delivered Redboot script to start the kernel +--------------------------------------------------- + +In redboot the following script is stored: + +fis load kernel +exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" + +Kernel is taken from flash. The image is in zImage format. + +Booting from NET, rootfs on NFS: +----------------------------------- + +To change the script in redboot: + +load -r -b 0x100000 <path_to_zImage> +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" + +If the ip address is not set, you can set it with : + +ip_address -l <board_ip/netmask> -h <server_ip> + +Linux partitions: +--------------------------- + +As default, the board is shipped with these partition tables for NAND +and for NOR: + +Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": +0x00000000-0x00100000 : "nand.bootloader" +0x00100000-0x00600000 : "nand.kernel" +0x00600000-0x06600000 : "nand.rootfs" +0x06600000-0x06e00000 : "nand.configure" +0x06e00000-0x80000000 : "nand.userfs" + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. +For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. + +However, the setup in redboot is not correct and does not use the whole flash. + +Better solution is to use the kernel parameter mtdparts. +Here the resulting script to be defined in RedBoot with fconfig: + +load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +Flashing U-Boot +-------------------------------- + +There are two options: the original bootloader in NAND can be replaced with +u-boot, or u-boot can be stored on the NOR flash without erasing +the delivered bootloader. +The boot storage can be select using the switches on the personality board +(SW1-SW2) and on the DEBUG board (SW4-SW10). + +The second option is to be preferred if you have not a JTAG debugger. +If something goes wrong flashing the bootloader, it is always possible to +recover the board booting from the other device. + +Replacing the bootloader on the NAND +-------------------------------------- +To replace RedBoot with U-Boot, the easy way is to do this in linux. +Start the kernel with the suggested options. Make sure to have set the +mtdparts exactly as described, because this matches the layout on the +mx35pdk. + +You should see in your boot log the following entries for the NAND +flash: + +5 cmdlinepart partitions found on MTD device mxc_nand +Creating 5 MTD partitions on "mxc_nand": +0x000000000000-0x000000100000 : "boot" +0x000000100000-0x000000600000 : "linux" +0x000000600000-0x000006600000 : "root" +0x000006600000-0x000006e00000 : "cfg" +0x000006e00000-0x000080000000 : "user" + +You can use the utilities flash_eraseall and nandwrite to put +u-boot on the NAND. The bootloader is marked as "boot", and 1MB is +reserved. If everything is correct, this partition is accessed as +/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and +get the device node from the partition name: + +$ cat /proc/mtd | grep boot + +I suggest you try the utilities on a different partition to be sure +if everything works correctly. If not, and you remove RedBoot, you have to +reinstall it using the ATK tool as suggested by Freescale, or using a +JTAG debugger. + +I report the versions of the utilities I used (they are provided with ELDK): + +-bash-3.2# nandwrite --version +nandwrite $Revision: 1.32 $ + +flash_eraseall --version +flash_eraseall $Revision: 1.22 $ + +nandwrite reports a warning if the file to be saved is not sector aligned. +This should have no consequences, but I preferred to pad u-boot.bin +to get no problem at all. +$ dd if=/dev/zero of=zeros bs=1 count=74800 +$ cat u-boot.bin zeros > u-boot-padded.bin + +To erase the partition: +$ flash_eraseall /dev/mtd4 + +Writing u-boot: + +$ nandwrite /dev/mtd4 u-boot-padded.bin + +Now U-Boot is stored on the booting partition. + +To boot from NAND, you have to select the switches as follows: + +Personality board + SW2 1, 4, 5 on + 2, 3, 6, 7, 8 off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 + + +Saving U-Boot in the NOR flash +--------------------------------- + +The procedure to save in the NOR flash is quite the same as to write into the NAND. + +Check the partition for boot in the NOR flash. Setting the mtdparts as reported, +the boot partition should be /dev/mtd0. + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +To erase the whole partition: +$ flash_eraseall /dev/mtd0 + +Writing u-boot: +dd if=u-boot.bin of=/dev/mtd0 + +To boot from NOR, you have to select the switches as follows: + +Personality board + SW2 all off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h new file mode 100644 index 0000000..086355b --- /dev/null +++ b/include/configs/mx35pdk.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * Configuration for the MX35pdk Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ +#define CONFIG_MX35 +#define CONFIG_MX35_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Set TEXT at the beginning of the NOR flash */ +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define CONFIG_BOARD_EARLY_INIT_F +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* + * Hardware drivers + */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX35_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#define CONFIG_MXC_SPI + + +/* + * PMIC Configs + */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_I2C +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 + +/* + * MFD MC9SDZ60 + */ +#define CONFIG_FSL_MC9SDZ60 +#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 + +/* + * UART (console) + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX35_UART1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* + * Command definition + */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_NAND + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SPI +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +/* + * Ethernet on the debug board (SMC911) + */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR + +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME + +/* + * Ethernet on SOC (FEC) + */ +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX35 U-Boot > " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \ + "96m(root),8m(cfg),1938m(user);" \ + "physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +/* Monitor@beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_ENV_IS_IN_FLASH + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND + #define CONFIG_ENV_OFFSET (1024 * 1024) +#endif + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER + +/* A non-standard buffered write algorithm */ +#define CONFIG_FLASH_SPANSION_S29WS_N +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ +#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ + +/* + * NAND FLASH driver setup + */ +#define CONFIG_NAND_MXC +#define CONFIG_NAND_MXC_V1_1 +#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * Default environment and default scripts + * to update uboot and load kernel + */ +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_HOSTNAME "mx35pdk" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "ethprime=smc911x\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=80800000\0" \ + "kernel_addr_r=80800000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=protect off ${uboot_addr} +40000;" \ + "erase ${uboot_addr} +40000;" \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + "bootcmd=run net_nfs\0" + +#endif /* __CONFIG_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V4 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 18:05 ` [U-Boot] [PATCH V4 " Stefano Babic @ 2011-02-01 17:51 ` Stefano Babic 0 siblings, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-02-01 17:51 UTC (permalink / raw) To: u-boot On 01/20/2011 07:05 PM, Stefano Babic wrote: > The patch adds suupport for the Freescale's mx35pdk board > (known as well as mx35_3stack). > > The board boots from the NOR flash. Following devices > are supported: > - two ethernet devices (FEC and SMC911x on debug board) > - I2C > - PMIC (MC13892) via I2C interface > - UART > - NOR flash (64MB) > - NAND flash (2GB) > - basic access to mc9sdz60 registers via I2C interface > > Signed-off-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-imx, thanks Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] [PATCH V3 11/11] Add support for Freescale's mx35pdk board. 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 18:05 ` [U-Boot] [PATCH V4 " Stefano Babic @ 2011-02-01 17:51 ` Stefano Babic 1 sibling, 0 replies; 46+ messages in thread From: Stefano Babic @ 2011-02-01 17:51 UTC (permalink / raw) To: u-boot On 01/20/2011 06:53 PM, Stefano Babic wrote: > The patch adds suupport for the Freescale's mx35pdk board > (known as well as mx35_3stack). > > The board boots from the NOR flash. Following devices > are supported: > - two ethernet devices (FEC and SMC911x on debug board) > - I2C > - PMIC (MC13892) via I2C interface > - UART > - NOR flash (64MB) > - NAND flash (2GB) > - basic access to mc9sdz60 registers via I2C interface > > Signed-off-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-imx, thanks Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] Adding support for MX35 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic ` (10 preceding siblings ...) 2011-01-20 8:46 ` [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board Stefano Babic @ 2011-01-20 9:52 ` Wolfgang Denk 2011-01-20 10:50 ` Stefano Babic 11 siblings, 1 reply; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 9:52 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <1295513194-16158-1-git-send-email-sbabic@denx.de> you wrote: > Patchset V2 contain patches for SPI sent previously independently to ML > and additional patches for I2C. I just learned that I was running an old version of checkpatch, which turned out some false positives (and my short visual inspection did not recognize this). Sorry for the flase alarms. The remaining warnings are: [U-Boot] [PATCH V2 01/11] Add support for MX35 processor total: 0 errors, 8 warnings, 2109 lines checked [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access total: 0 errors, 2 warnings, 169 lines checked [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 total: 1 errors, 1 warnings, 166 lines checked [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add total: 0 errors, 1 warnings, 22 lines checked [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. total: 0 errors, 1 warnings, 1331 lines checked Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de What was sliced bread the greatest thing since? ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] Adding support for MX35 2011-01-20 9:52 ` [U-Boot] Adding support for MX35 Wolfgang Denk @ 2011-01-20 10:50 ` Stefano Babic 2011-01-20 12:04 ` Wolfgang Denk 0 siblings, 1 reply; 46+ messages in thread From: Stefano Babic @ 2011-01-20 10:50 UTC (permalink / raw) To: u-boot On 01/20/2011 10:52 AM, Wolfgang Denk wrote: > Dear Stefano Babic, > > In message <1295513194-16158-1-git-send-email-sbabic@denx.de> you wrote: >> Patchset V2 contain patches for SPI sent previously independently to ML >> and additional patches for I2C. > > I just learned that I was running an old version of checkpatch, which > turned out some false positives (and my short visual inspection did > not recognize this) > > Sorry for the flase alarms. No problem, this explains the the different results. I ran checkpatch on the patchset. > > The remaining warnings are: > > [U-Boot] [PATCH V2 01/11] Add support for MX35 processor > total: 0 errors, 8 warnings, 2109 lines checked They are related to typedef (mmmhh...there is one regarding usage of volatile, I will fix it). I do not think that using typedef is forbidden. > > [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access > total: 0 errors, 2 warnings, 169 lines checked __FUNCTION__, I will fix it > > [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 > total: 1 errors, 1 warnings, 166 lines checked See my previous comment. In any case, I will change to avoid checkpatch complains > > [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add > total: 0 errors, 1 warnings, 22 lines checked Braces, braces...do you agree to follow checkpatch's rule (no braces for single statement) ? > > [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board. > total: 0 errors, 1 warnings, 1331 lines checked You already give me the solution Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 46+ messages in thread
* [U-Boot] Adding support for MX35 2011-01-20 10:50 ` Stefano Babic @ 2011-01-20 12:04 ` Wolfgang Denk 0 siblings, 0 replies; 46+ messages in thread From: Wolfgang Denk @ 2011-01-20 12:04 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <4D381387.50904@denx.de> you wrote: > > > [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add > > total: 0 errors, 1 warnings, 22 lines checked > > Braces, braces...do you agree to follow checkpatch's rule (no braces for > single statement) ? Try it out :-) Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Faith may be defined briefly as an illogical belief in the occurence of the improbable. - H. L. Mencken ^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2011-02-01 17:58 UTC | newest] Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-01-20 8:46 [U-Boot] Adding support for MX35 Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 01/11] Add support for MX35 processor Stefano Babic 2011-01-20 9:25 ` Wolfgang Denk 2011-01-20 10:19 ` Stefano Babic 2011-01-20 11:52 ` Wolfgang Denk 2011-01-20 17:49 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-02-01 17:50 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 02/11] serial_mxc: add support for Freescale's i.MX35 processor Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 03/11] mxc_i2c: Add support for the " Stefano Babic 2011-01-21 6:28 ` Heiko Schocher 2011-01-20 8:46 ` [U-Boot] [PATCH V2 04/11] I2C: mxc_i2c: get rid of __REG access Stefano Babic 2011-01-20 9:27 ` Wolfgang Denk 2011-01-20 10:23 ` Stefano Babic 2011-01-20 17:50 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-21 6:30 ` Heiko Schocher 2011-01-20 8:46 ` [U-Boot] [PATCH V2 05/11] I2C: mxc_i2c: address failure with mx35 processor Stefano Babic 2011-01-20 9:30 ` Wolfgang Denk 2011-01-20 10:27 ` Stefano Babic 2011-01-20 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-21 6:36 ` Heiko Schocher 2011-01-21 9:08 ` Stefano Babic 2011-01-21 9:21 ` Heiko Schocher 2011-01-20 8:46 ` [U-Boot] [PATCH V2 06/11] Add basic support for Freescale's mc9sdz60 Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 07/11] SPI: mxc_spi: add support for i.MX35 processor Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 08/11] SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case Stefano Babic 2011-01-20 9:32 ` Wolfgang Denk 2011-01-20 10:29 ` Stefano Babic 2011-01-20 11:59 ` Wolfgang Denk 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-02-01 17:53 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver Stefano Babic 2011-02-01 17:58 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 10/11] SPI: mxc_spi: replace fixed offsets with structures Stefano Babic 2011-01-20 9:33 ` Wolfgang Denk 2011-01-20 10:30 ` Stefano Babic 2011-01-20 8:46 ` [U-Boot] [PATCH V2 11/11] Add support for Freescale's mx35pdk board Stefano Babic 2011-01-20 9:41 ` Wolfgang Denk 2011-01-20 10:45 ` Stefano Babic 2011-01-20 12:03 ` Wolfgang Denk 2011-01-20 17:53 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 18:05 ` [U-Boot] [PATCH V4 " Stefano Babic 2011-02-01 17:51 ` Stefano Babic 2011-02-01 17:51 ` [U-Boot] [PATCH V3 " Stefano Babic 2011-01-20 9:52 ` [U-Boot] Adding support for MX35 Wolfgang Denk 2011-01-20 10:50 ` Stefano Babic 2011-01-20 12:04 ` Wolfgang Denk
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