[PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[Rodrigo Vivi]

This wrong logic and useless define came from first versions and
came along with all rework. Just now I notice how ugly, wrong and
useless this is.

val is already defined as 0 anyway and logic is completelly wrong
and useless. So let's starting the link_standby fix with this
cleaning.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 -
 drivers/gpu/drm/i915/intel_psr.c | 3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..b95554d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2658,7 +2658,6 @@ enum skl_disp_power_wells {
 #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE			(1<<31)
 #define   BDW_PSR_SINGLE_FRAME			(1<<30)
-#define   EDP_PSR_LINK_DISABLE			(0<<27)
 #define   EDP_PSR_LINK_STANDBY			(1<<27)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b9f40c2..2e6831d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -247,8 +247,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
 		val |= EDP_PSR_SKIP_AUX_EXIT;
-	} else
-		val |= EDP_PSR_LINK_DISABLE;
+	}
 
 	I915_WRITE(EDP_PSR_CTL(dev), val |
 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
-- 
1.9.3

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[PATCH 2/7] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[Rodrigo Vivi]

Since the begining there is a missunderstanding on the meaning of this
dpcd bit.
This bit should'n indicate wheter to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.

Even with help of frontbuffer tracking to do exit HW tracking is still
fully responsible for this exit logic with DP training or not.

Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e6831d..6c8e9e0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -242,8 +242,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby) {
+	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
+
+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
 		val |= EDP_PSR_SKIP_AUX_EXIT;
@@ -354,8 +356,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	/* First we check VBT, but we must respect sink and source
 	 * known restrictions */
 	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
-	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
+	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
 		dev_priv->psr.link_standby = true;
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
-- 
1.9.3

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[PATCH 3/7] drm/i915: PSR: deprecate link_standby support for core platforms.

[Rodrigo Vivi]

On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. hen this condition hits, panel will intermittently
display black frame.

The known W/A for this case involve the of single_frame update
that isn't supported on Haswell and to be supported on Broadwell
3 other workarounds would be required. So it is better and safe to
just deprecate link_standby for now.

Also, link fully off saves more power than link_standby and afwk
no OEM is requesting link standby on VBT. There is no reason for that.

For Skylake let's just consider it behaves like Broadwell until
we prove otherwise.

Reference: HSD: bdwgfx/1912559
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
 drivers/gpu/drm/i915/i915_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 94b3984..756bf4e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		}
 	seq_puts(m, "\n");
 
-	seq_printf(m, "Link standby: %s\n",
-		   yesno((bool)dev_priv->psr.link_standby));
-
 	/* CHV PSR has no kind of performance counter */
 	if (HAS_PSR(dev) && HAS_DDI(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a1dd8bc..dfd044f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -863,7 +863,6 @@ struct i915_psr {
 	bool active;
 	struct delayed_work work;
 	unsigned busy_frontbuffer_bits;
-	bool link_standby;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6c8e9e0..d2ff87d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
-	/* Enable PSR in sink */
-	if (dev_priv->psr.link_standby)
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-	else
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
-
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
 				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
@@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 	}
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby)
-		val |= EDP_PSR_LINK_STANDBY;
-
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
@@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
+	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
+				    (dig_port->port != PORT_A))){
+		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
+		return false;
+	}
+
 	dev_priv->psr.source_ok = true;
 	return true;
 }
@@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	if (!intel_psr_match_conditions(intel_dp))
 		goto unlock;
 
-	/* First we check VBT, but we must respect sink and source
-	 * known restrictions */
-	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
-		dev_priv->psr.link_standby = true;
-
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	if (HAS_DDI(dev)) {
-- 
1.9.3

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[PATCH 4/7] drm/i915: PSR VLV: Add single frame update.

[Rodrigo Vivi]

According to spec: "In PSR HW or SW mode, SW set this bit before writing
registers for a flip. It will be self-clear when it gets to the PSR
active state."

Some versions of spec mention that this is needed when in
"Persistent mode" but define it as same as "SW mode". Since this
fix the page flip case let's assume this is exactly what we need.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_frontbuffer.c |  2 ++
 drivers/gpu/drm/i915/intel_psr.c         | 42 ++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1fb1529..55ece8f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1182,6 +1182,7 @@ void intel_psr_invalidate(struct drm_device *dev,
 void intel_psr_flush(struct drm_device *dev,
 			 unsigned frontbuffer_bits);
 void intel_psr_init(struct drm_device *dev);
+void intel_psr_single_frame_update(struct drm_device *dev);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 73cb6e0..2094c06 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -254,6 +254,8 @@ void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 	/* Remove stale busy bits due to the old buffer. */
 	dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
 	mutex_unlock(&dev_priv->fb_tracking.lock);
+
+	intel_psr_single_frame_update(dev);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d2ff87d..c1ca923 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -553,6 +553,48 @@ static void intel_psr_exit(struct drm_device *dev)
 }
 
 /**
+ * intel_psr_single_frame_update - Single Frame Update
+ * @dev: DRM device
+ *
+ * Some platforms support a single frame update feature that is used to
+ * send and update only one frame on Remote Frame Buffer.
+ * So far it is only implemented for Valleyview and Cherryview because
+ * hardware requires this to be done before a page flip.
+ */
+void intel_psr_single_frame_update(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	enum pipe pipe;
+	u32 val;
+
+	/*
+	 * Single frame update is already supported on BDW+ but it requires
+	 * many W/A and it isn't really needed.
+	 */
+	if (!IS_VALLEYVIEW(dev))
+		return;
+
+	mutex_lock(&dev_priv->psr.lock);
+	if (!dev_priv->psr.enabled) {
+		mutex_unlock(&dev_priv->psr.lock);
+		return;
+	}
+
+	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
+	pipe = to_intel_crtc(crtc)->pipe;
+	val = I915_READ(VLV_PSRCTL(pipe));
+
+	/*
+	 * We need to set this bit before writing registers for a flip.
+	 * This bit will be self-clear when it gets to the PSR active state.
+	 */
+	I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
+
+	mutex_unlock(&dev_priv->psr.lock);
+}
+
+/**
  * intel_psr_invalidate - Invalidade PSR
  * @dev: DRM device
  * @frontbuffer_bits: frontbuffer plane tracking bits
-- 
1.9.3

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[PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Rodrigo Vivi]

There are some cases like suspend/resume or dpms off/on sequences
that can flush frontbuffer bits. In these cases features that relies
on frontbuffer tracking can start working and user can stop getting
screen updates on fbcon having impression the system is frozen.

So, let's make sure on fbcon write operation we also invalidate
frontbuffer bits so we will be on the safest side with fbcon.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_fbdev.c | 120 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 117 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 234a699..1b512f2 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
 	return ret;
 }
 
+void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev =
+		container_of(fb_helper, struct intel_fbdev, helper);
+
+	cfb_fillrect(info, rect);
+
+	/*
+	 * FIXME: fbdev presumes that all callbacks also work from
+	 * atomic contexts and relies on that for emergency oops
+	 * printing. KMS totally doesn't do that and the locking here is
+	 * by far not the only place this goes wrong.  Ignore this for
+	 * now until we solve this for real.
+	 */
+	mutex_lock(&fb_helper->dev->struct_mutex);
+
+	/*
+	 * There are some cases that can flush frontbuffer bits
+	 * while we are still on console. So, let's make sure the fb obj
+	 * gets invalidated on this write op so we don't have any risk
+	 * of missing screen updates when PSR, FBC or any other power saving
+	 * feature is enabled.
+	 */
+	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
+	mutex_unlock(&fb_helper->dev->struct_mutex);
+}
+
+void intel_fbdev_copyarea(struct fb_info *info,
+			  const struct fb_copyarea *region)\
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev =
+		container_of(fb_helper, struct intel_fbdev, helper);
+
+	cfb_copyarea(info, region);
+
+	/*
+	 * FIXME: fbdev presumes that all callbacks also work from
+	 * atomic contexts and relies on that for emergency oops
+	 * printing. KMS totally doesn't do that and the locking here is
+	 * by far not the only place this goes wrong.  Ignore this for
+	 * now until we solve this for real.
+	 */
+	mutex_lock(&fb_helper->dev->struct_mutex);
+
+	/*
+	 * There are some cases that can flush frontbuffer bits
+	 * while we are still on console. So, let's make sure the fb obj
+	 * gets invalidated on this write op so we don't have any risk
+	 * of missing screen updates when PSR, FBC or any other power saving
+	 * feature is enabled.
+	 */
+	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
+	mutex_unlock(&fb_helper->dev->struct_mutex);
+}
+
+void intel_fbdev_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev =
+		container_of(fb_helper, struct intel_fbdev, helper);
+
+	cfb_imageblit(info, image);
+
+	/*
+	 * FIXME: fbdev presumes that all callbacks also work from
+	 * atomic contexts and relies on that for emergency oops
+	 * printing. KMS totally doesn't do that and the locking here is
+	 * by far not the only place this goes wrong.  Ignore this for
+	 * now until we solve this for real.
+	 */
+	mutex_lock(&fb_helper->dev->struct_mutex);
+
+	/*
+	 * There are some cases that can flush frontbuffer bits
+	 * while we are still on console. So, let's make sure the fb obj
+	 * gets invalidated on this write op so we don't have any risk
+	 * of missing screen updates when PSR, FBC or any other power saving
+	 * feature is enabled.
+	 */
+	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
+	mutex_unlock(&fb_helper->dev->struct_mutex);
+}
+
+int intel_fbdev_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev =
+		container_of(fb_helper, struct intel_fbdev, helper);
+
+	/*
+	 * FIXME: fbdev presumes that all callbacks also work from
+	 * atomic contexts and relies on that for emergency oops
+	 * printing. KMS totally doesn't do that and the locking here is
+	 * by far not the only place this goes wrong.  Ignore this for
+	 * now until we solve this for real.
+	 */
+	mutex_lock(&fb_helper->dev->struct_mutex);
+
+	/*
+	 * There are some cases that can flush frontbuffer bits
+	 * while we are still on console. So, let's make sure the fb obj
+	 * gets invalidated on this write op so we don't have any risk
+	 * of missing screen updates when PSR, FBC or any other power saving
+	 * feature is enabled.
+	 */
+	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
+	mutex_unlock(&fb_helper->dev->struct_mutex);
+
+	return 0;
+}
+
 static struct fb_ops intelfb_ops = {
 	.owner = THIS_MODULE,
 	.fb_check_var = drm_fb_helper_check_var,
 	.fb_set_par = intel_fbdev_set_par,
-	.fb_fillrect = cfb_fillrect,
-	.fb_copyarea = cfb_copyarea,
-	.fb_imageblit = cfb_imageblit,
+	.fb_fillrect = intel_fbdev_fillrect,
+	.fb_copyarea = intel_fbdev_copyarea,
+	.fb_imageblit = intel_fbdev_imageblit,
+	.fb_cursor = intel_fbdev_cursor,
 	.fb_pan_display = drm_fb_helper_pan_display,
 	.fb_blank = drm_fb_helper_blank,
 	.fb_setcmap = drm_fb_helper_setcmap,
-- 
1.9.3

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[PATCH 6/7] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[Rodrigo Vivi]

Since active function on VLV immediately activate PSR let's give more
time for idleness.

v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
    there is a huge risk of getting blank screens when planes are being enabled.
v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
    actually time for link training what we aren't doing, but with only 100 sec
    in some cases kms_psr_sink_crc manual was showing blank screen,
    so let's use this for now. Also changed comment by a FIXME.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c1ca923..3c1d2b3 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -648,6 +648,12 @@ void intel_psr_flush(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	enum pipe pipe;
+	/* FIXME: kms_psr_sink_crc in manual mode shows black screen on
+	 * the very first primary plane enabling. W/A is to delay
+	 * the activate a bit more. On regular use 100 would be enough and
+	 * better for good power savings.
+	 */
+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (!dev_priv->psr.enabled) {
@@ -680,7 +686,7 @@ void intel_psr_flush(struct drm_device *dev,
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
 		schedule_delayed_work(&dev_priv->psr.work,
-				      msecs_to_jiffies(100));
+				      msecs_to_jiffies(delay));
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
-- 
1.9.3

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[PATCH 7/7] drm/i915: Enable PSR by default.

[Rodrigo Vivi]

With a reliable frontbuffer tracking and all instability corner cases solved
let's re-enabled PSR by default on all supported platforms.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 44f2262..2c1a90e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_execlists = -1,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
-	.enable_psr = 0,
+	.enable_psr = 1,
 	.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
 	.disable_power_well = 1,
 	.enable_ips = 1,
@@ -127,7 +127,7 @@ MODULE_PARM_DESC(enable_execlists,
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named(enable_psr, i915.enable_psr, int, 0600);
-MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
+MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
 
 module_param_named(preliminary_hw_support, i915.preliminary_hw_support, int, 0600);
 MODULE_PARM_DESC(preliminary_hw_support,
-- 
1.9.3

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Re: [PATCH 3/7] drm/i915: PSR: deprecate link_standby support for core platforms.

[Jindal, Sonika]

On 2/28/2015 6:56 AM, Rodrigo Vivi wrote:
> On Haswell and Broadwell with link in standby when exit event happens
> between vblank and VSC packet, PSR exit on panel but DPA transmitter
> still sends black pixel. hen this condition hits, panel will intermittently
> display black frame.
>
> The known W/A for this case involve the of single_frame update
> that isn't supported on Haswell and to be supported on Broadwell
> 3 other workarounds would be required. So it is better and safe to
> just deprecate link_standby for now.
>
> Also, link fully off saves more power than link_standby and afwk
> no OEM is requesting link standby on VBT. There is no reason for that.
>
> For Skylake let's just consider it behaves like Broadwell until
> we prove otherwise.
>
Hmm, on SKL I am able to read the sink crc only when I keep this 
link_standby true. Not sure if we'l have to pull it back or need to look 
for another solution.
> Reference: HSD: bdwgfx/1912559
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
>   drivers/gpu/drm/i915/i915_drv.h     |  1 -
>   drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
>   3 files changed, 8 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 94b3984..756bf4e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>   		}
>   	seq_puts(m, "\n");
>
> -	seq_printf(m, "Link standby: %s\n",
> -		   yesno((bool)dev_priv->psr.link_standby));
> -
>   	/* CHV PSR has no kind of performance counter */
>   	if (HAS_PSR(dev) && HAS_DDI(dev)) {
>   		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a1dd8bc..dfd044f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -863,7 +863,6 @@ struct i915_psr {
>   	bool active;
>   	struct delayed_work work;
>   	unsigned busy_frontbuffer_bits;
> -	bool link_standby;
>   };
>
>   enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6c8e9e0..d2ff87d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>
>   	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>
> -	/* Enable PSR in sink */
> -	if (dev_priv->psr.link_standby)
> -		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> -				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
> -	else
> -		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> -				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
> -
>   	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
>   				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
>   	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> @@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>   		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>   		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>   	}
> +
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
>   }
>
>   static void vlv_psr_enable_source(struct intel_dp *intel_dp)
> @@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>   	uint32_t val = 0x0;
>   	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
> -	if (dev_priv->psr.link_standby)
> -		val |= EDP_PSR_LINK_STANDBY;
> -
>   	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>   		val |= EDP_PSR_TP2_TP3_TIME_0us;
>   		val |= EDP_PSR_TP1_TIME_0us;
> @@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>   		return false;
>   	}
>
> +	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
> +				    (dig_port->port != PORT_A))){
> +		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
> +		return false;
> +	}
> +
>   	dev_priv->psr.source_ok = true;
>   	return true;
>   }
> @@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>   	if (!intel_psr_match_conditions(intel_dp))
>   		goto unlock;
>
> -	/* First we check VBT, but we must respect sink and source
> -	 * known restrictions */
> -	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
> -	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
> -		dev_priv->psr.link_standby = true;
> -
>   	dev_priv->psr.busy_frontbuffer_bits = 0;
>
>   	if (HAS_DDI(dev)) {
>
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Re: [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[Daniel Vetter]

On Fri, Feb 27, 2015 at 08:26:01PM -0500, Rodrigo Vivi wrote:
> This wrong logic and useless define came from first versions and
> came along with all rework. Just now I notice how ugly, wrong and
> useless this is.
> 
> val is already defined as 0 anyway and logic is completelly wrong
> and useless. So let's starting the link_standby fix with this
> cleaning.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 1 -
>  drivers/gpu/drm/i915/intel_psr.c | 3 +--
>  2 files changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 55143cb..b95554d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2658,7 +2658,6 @@ enum skl_disp_power_wells {
>  #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
>  #define   EDP_PSR_ENABLE			(1<<31)
>  #define   BDW_PSR_SINGLE_FRAME			(1<<30)
> -#define   EDP_PSR_LINK_DISABLE			(0<<27)

Please don't remove the #define if that itself is correct.
-Daniel

>  #define   EDP_PSR_LINK_STANDBY			(1<<27)
>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b9f40c2..2e6831d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -247,8 +247,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  		val |= EDP_PSR_TP2_TP3_TIME_0us;
>  		val |= EDP_PSR_TP1_TIME_0us;
>  		val |= EDP_PSR_SKIP_AUX_EXIT;
> -	} else
> -		val |= EDP_PSR_LINK_DISABLE;
> +	}
>  
>  	I915_WRITE(EDP_PSR_CTL(dev), val |
>  		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
> -- 
> 1.9.3
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Daniel Vetter]

On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> There are some cases like suspend/resume or dpms off/on sequences
> that can flush frontbuffer bits. In these cases features that relies
> on frontbuffer tracking can start working and user can stop getting
> screen updates on fbcon having impression the system is frozen.
> 
> So, let's make sure on fbcon write operation we also invalidate
> frontbuffer bits so we will be on the safest side with fbcon.

This is just a bandaid since you can always just directly access the
fbdev framebuffer. We really need to figure out why we have frontbuffer
bit flushes after we've invalidated them for fbcon and catch them all.
-Daniel

> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_fbdev.c | 120 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 117 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index 234a699..1b512f2 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
>  	return ret;
>  }
>  
> +void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
> +{
> +	struct drm_fb_helper *fb_helper = info->par;
> +	struct intel_fbdev *ifbdev =
> +		container_of(fb_helper, struct intel_fbdev, helper);
> +
> +	cfb_fillrect(info, rect);
> +
> +	/*
> +	 * FIXME: fbdev presumes that all callbacks also work from
> +	 * atomic contexts and relies on that for emergency oops
> +	 * printing. KMS totally doesn't do that and the locking here is
> +	 * by far not the only place this goes wrong.  Ignore this for
> +	 * now until we solve this for real.
> +	 */
> +	mutex_lock(&fb_helper->dev->struct_mutex);
> +
> +	/*
> +	 * There are some cases that can flush frontbuffer bits
> +	 * while we are still on console. So, let's make sure the fb obj
> +	 * gets invalidated on this write op so we don't have any risk
> +	 * of missing screen updates when PSR, FBC or any other power saving
> +	 * feature is enabled.
> +	 */
> +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> +	mutex_unlock(&fb_helper->dev->struct_mutex);
> +}
> +
> +void intel_fbdev_copyarea(struct fb_info *info,
> +			  const struct fb_copyarea *region)\
> +{
> +	struct drm_fb_helper *fb_helper = info->par;
> +	struct intel_fbdev *ifbdev =
> +		container_of(fb_helper, struct intel_fbdev, helper);
> +
> +	cfb_copyarea(info, region);
> +
> +	/*
> +	 * FIXME: fbdev presumes that all callbacks also work from
> +	 * atomic contexts and relies on that for emergency oops
> +	 * printing. KMS totally doesn't do that and the locking here is
> +	 * by far not the only place this goes wrong.  Ignore this for
> +	 * now until we solve this for real.
> +	 */
> +	mutex_lock(&fb_helper->dev->struct_mutex);
> +
> +	/*
> +	 * There are some cases that can flush frontbuffer bits
> +	 * while we are still on console. So, let's make sure the fb obj
> +	 * gets invalidated on this write op so we don't have any risk
> +	 * of missing screen updates when PSR, FBC or any other power saving
> +	 * feature is enabled.
> +	 */
> +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> +	mutex_unlock(&fb_helper->dev->struct_mutex);
> +}
> +
> +void intel_fbdev_imageblit(struct fb_info *info, const struct fb_image *image)
> +{
> +	struct drm_fb_helper *fb_helper = info->par;
> +	struct intel_fbdev *ifbdev =
> +		container_of(fb_helper, struct intel_fbdev, helper);
> +
> +	cfb_imageblit(info, image);
> +
> +	/*
> +	 * FIXME: fbdev presumes that all callbacks also work from
> +	 * atomic contexts and relies on that for emergency oops
> +	 * printing. KMS totally doesn't do that and the locking here is
> +	 * by far not the only place this goes wrong.  Ignore this for
> +	 * now until we solve this for real.
> +	 */
> +	mutex_lock(&fb_helper->dev->struct_mutex);
> +
> +	/*
> +	 * There are some cases that can flush frontbuffer bits
> +	 * while we are still on console. So, let's make sure the fb obj
> +	 * gets invalidated on this write op so we don't have any risk
> +	 * of missing screen updates when PSR, FBC or any other power saving
> +	 * feature is enabled.
> +	 */
> +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> +	mutex_unlock(&fb_helper->dev->struct_mutex);
> +}
> +
> +int intel_fbdev_cursor(struct fb_info *info, struct fb_cursor *cursor)
> +{
> +	struct drm_fb_helper *fb_helper = info->par;
> +	struct intel_fbdev *ifbdev =
> +		container_of(fb_helper, struct intel_fbdev, helper);
> +
> +	/*
> +	 * FIXME: fbdev presumes that all callbacks also work from
> +	 * atomic contexts and relies on that for emergency oops
> +	 * printing. KMS totally doesn't do that and the locking here is
> +	 * by far not the only place this goes wrong.  Ignore this for
> +	 * now until we solve this for real.
> +	 */
> +	mutex_lock(&fb_helper->dev->struct_mutex);
> +
> +	/*
> +	 * There are some cases that can flush frontbuffer bits
> +	 * while we are still on console. So, let's make sure the fb obj
> +	 * gets invalidated on this write op so we don't have any risk
> +	 * of missing screen updates when PSR, FBC or any other power saving
> +	 * feature is enabled.
> +	 */
> +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> +	mutex_unlock(&fb_helper->dev->struct_mutex);
> +
> +	return 0;
> +}
> +
>  static struct fb_ops intelfb_ops = {
>  	.owner = THIS_MODULE,
>  	.fb_check_var = drm_fb_helper_check_var,
>  	.fb_set_par = intel_fbdev_set_par,
> -	.fb_fillrect = cfb_fillrect,
> -	.fb_copyarea = cfb_copyarea,
> -	.fb_imageblit = cfb_imageblit,
> +	.fb_fillrect = intel_fbdev_fillrect,
> +	.fb_copyarea = intel_fbdev_copyarea,
> +	.fb_imageblit = intel_fbdev_imageblit,
> +	.fb_cursor = intel_fbdev_cursor,
>  	.fb_pan_display = drm_fb_helper_pan_display,
>  	.fb_blank = drm_fb_helper_blank,
>  	.fb_setcmap = drm_fb_helper_setcmap,
> -- 
> 1.9.3
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Vivi, Rodrigo]

On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > There are some cases like suspend/resume or dpms off/on sequences
> > that can flush frontbuffer bits. In these cases features that relies
> > on frontbuffer tracking can start working and user can stop getting
> > screen updates on fbcon having impression the system is frozen.
> > 
> > So, let's make sure on fbcon write operation we also invalidate
> > frontbuffer bits so we will be on the safest side with fbcon.
> 
> This is just a bandaid since you can always just directly access the
> fbdev framebuffer. We really need to figure out why we have frontbuffer
> bit flushes after we've invalidated them for fbcon and catch them all.

yeah, an ugly bandaid... Just to make PSR a bit more reliable without
breaking fbcon environment when it gets enabled by default.

The issue is that on the logs I see:

1.fbdev_blank dpms off
2. disable planes
3. flush frontbuffer bits
--- blank stage ---
4. fbdev_blank dpms on
5. enable planes
6. flush frontbuffer bits

So even if we put the invalidate there it will still get flushed.

Along with this sequence I see bunch of fillrect, cursor, imageblt,
copyarea so what ever happens first right after the "6." will invalidate
the frontbuffer_bits again so any direct write thought fbdev framebuffer
will be safe enough.

So yeah, with this bandaid for now I believe we are safe to enable psr
by default while we continue the investigation to come up with a proper
fix.

> -Daniel
> 
> > 
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_fbdev.c | 120 ++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 117 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> > index 234a699..1b512f2 100644
> > --- a/drivers/gpu/drm/i915/intel_fbdev.c
> > +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> > @@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
> >  	return ret;
> >  }
> >  
> > +void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
> > +{
> > +	struct drm_fb_helper *fb_helper = info->par;
> > +	struct intel_fbdev *ifbdev =
> > +		container_of(fb_helper, struct intel_fbdev, helper);
> > +
> > +	cfb_fillrect(info, rect);
> > +
> > +	/*
> > +	 * FIXME: fbdev presumes that all callbacks also work from
> > +	 * atomic contexts and relies on that for emergency oops
> > +	 * printing. KMS totally doesn't do that and the locking here is
> > +	 * by far not the only place this goes wrong.  Ignore this for
> > +	 * now until we solve this for real.
> > +	 */
> > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > +
> > +	/*
> > +	 * There are some cases that can flush frontbuffer bits
> > +	 * while we are still on console. So, let's make sure the fb obj
> > +	 * gets invalidated on this write op so we don't have any risk
> > +	 * of missing screen updates when PSR, FBC or any other power saving
> > +	 * feature is enabled.
> > +	 */
> > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > +}
> > +
> > +void intel_fbdev_copyarea(struct fb_info *info,
> > +			  const struct fb_copyarea *region)\
> > +{
> > +	struct drm_fb_helper *fb_helper = info->par;
> > +	struct intel_fbdev *ifbdev =
> > +		container_of(fb_helper, struct intel_fbdev, helper);
> > +
> > +	cfb_copyarea(info, region);
> > +
> > +	/*
> > +	 * FIXME: fbdev presumes that all callbacks also work from
> > +	 * atomic contexts and relies on that for emergency oops
> > +	 * printing. KMS totally doesn't do that and the locking here is
> > +	 * by far not the only place this goes wrong.  Ignore this for
> > +	 * now until we solve this for real.
> > +	 */
> > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > +
> > +	/*
> > +	 * There are some cases that can flush frontbuffer bits
> > +	 * while we are still on console. So, let's make sure the fb obj
> > +	 * gets invalidated on this write op so we don't have any risk
> > +	 * of missing screen updates when PSR, FBC or any other power saving
> > +	 * feature is enabled.
> > +	 */
> > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > +}
> > +
> > +void intel_fbdev_imageblit(struct fb_info *info, const struct fb_image *image)
> > +{
> > +	struct drm_fb_helper *fb_helper = info->par;
> > +	struct intel_fbdev *ifbdev =
> > +		container_of(fb_helper, struct intel_fbdev, helper);
> > +
> > +	cfb_imageblit(info, image);
> > +
> > +	/*
> > +	 * FIXME: fbdev presumes that all callbacks also work from
> > +	 * atomic contexts and relies on that for emergency oops
> > +	 * printing. KMS totally doesn't do that and the locking here is
> > +	 * by far not the only place this goes wrong.  Ignore this for
> > +	 * now until we solve this for real.
> > +	 */
> > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > +
> > +	/*
> > +	 * There are some cases that can flush frontbuffer bits
> > +	 * while we are still on console. So, let's make sure the fb obj
> > +	 * gets invalidated on this write op so we don't have any risk
> > +	 * of missing screen updates when PSR, FBC or any other power saving
> > +	 * feature is enabled.
> > +	 */
> > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > +}
> > +
> > +int intel_fbdev_cursor(struct fb_info *info, struct fb_cursor *cursor)
> > +{
> > +	struct drm_fb_helper *fb_helper = info->par;
> > +	struct intel_fbdev *ifbdev =
> > +		container_of(fb_helper, struct intel_fbdev, helper);
> > +
> > +	/*
> > +	 * FIXME: fbdev presumes that all callbacks also work from
> > +	 * atomic contexts and relies on that for emergency oops
> > +	 * printing. KMS totally doesn't do that and the locking here is
> > +	 * by far not the only place this goes wrong.  Ignore this for
> > +	 * now until we solve this for real.
> > +	 */
> > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > +
> > +	/*
> > +	 * There are some cases that can flush frontbuffer bits
> > +	 * while we are still on console. So, let's make sure the fb obj
> > +	 * gets invalidated on this write op so we don't have any risk
> > +	 * of missing screen updates when PSR, FBC or any other power saving
> > +	 * feature is enabled.
> > +	 */
> > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > +
> > +	return 0;
> > +}
> > +
> >  static struct fb_ops intelfb_ops = {
> >  	.owner = THIS_MODULE,
> >  	.fb_check_var = drm_fb_helper_check_var,
> >  	.fb_set_par = intel_fbdev_set_par,
> > -	.fb_fillrect = cfb_fillrect,
> > -	.fb_copyarea = cfb_copyarea,
> > -	.fb_imageblit = cfb_imageblit,
> > +	.fb_fillrect = intel_fbdev_fillrect,
> > +	.fb_copyarea = intel_fbdev_copyarea,
> > +	.fb_imageblit = intel_fbdev_imageblit,
> > +	.fb_cursor = intel_fbdev_cursor,
> >  	.fb_pan_display = drm_fb_helper_pan_display,
> >  	.fb_blank = drm_fb_helper_blank,
> >  	.fb_setcmap = drm_fb_helper_setcmap,
> > -- 
> > 1.9.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [PATCH 3/7] drm/i915: PSR: deprecate link_standby support for core platforms.

[Rodrigo Vivi]

On Mon, Mar 2, 2015 at 3:41 AM, Jindal, Sonika <sonika.jindal@intel.com> wrote:
>
>
> On 2/28/2015 6:56 AM, Rodrigo Vivi wrote:
>>
>> On Haswell and Broadwell with link in standby when exit event happens
>> between vblank and VSC packet, PSR exit on panel but DPA transmitter
>> still sends black pixel. hen this condition hits, panel will
>> intermittently
>> display black frame.
>>
>> The known W/A for this case involve the of single_frame update
>> that isn't supported on Haswell and to be supported on Broadwell
>> 3 other workarounds would be required. So it is better and safe to
>> just deprecate link_standby for now.
>>
>> Also, link fully off saves more power than link_standby and afwk
>> no OEM is requesting link standby on VBT. There is no reason for that.
>>
>> For Skylake let's just consider it behaves like Broadwell until
>> we prove otherwise.
>>
> Hmm, on SKL I am able to read the sink crc only when I keep this
> link_standby true. Not sure if we'l have to pull it back or need to look for
> another solution.

I faced this on BDW as well, but after reworking the test case I could
make it read crc on BDW with link fully off.

Could you please try this on SKL? kms_psr_sink_crc from psr-crc-skl
branch at: http://cgit.freedesktop.org/~vivijim/intel-gpu-tools/log/?h=psr-crc-skl

>
>> Reference: HSD: bdwgfx/1912559
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
>>   drivers/gpu/drm/i915/i915_drv.h     |  1 -
>>   drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
>>   3 files changed, 8 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 94b3984..756bf4e 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m,
>> void *data)
>>                 }
>>         seq_puts(m, "\n");
>>
>> -       seq_printf(m, "Link standby: %s\n",
>> -                  yesno((bool)dev_priv->psr.link_standby));
>> -
>>         /* CHV PSR has no kind of performance counter */
>>         if (HAS_PSR(dev) && HAS_DDI(dev)) {
>>                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index a1dd8bc..dfd044f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -863,7 +863,6 @@ struct i915_psr {
>>         bool active;
>>         struct delayed_work work;
>>         unsigned busy_frontbuffer_bits;
>> -       bool link_standby;
>>   };
>>
>>   enum intel_pch {
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 6c8e9e0..d2ff87d 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp
>> *intel_dp)
>>
>>         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>>
>> -       /* Enable PSR in sink */
>> -       if (dev_priv->psr.link_standby)
>> -               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>> -                                  DP_PSR_ENABLE |
>> DP_PSR_MAIN_LINK_ACTIVE);
>> -       else
>> -               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>> -                                  DP_PSR_ENABLE &
>> ~DP_PSR_MAIN_LINK_ACTIVE);
>> -
>>         aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
>>                                 DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
>>         aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
>> @@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp
>> *intel_dp)
>>                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>>                    (aux_clock_divider <<
>> DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
>>         }
>> +
>> +       drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
>>   }
>>
>>   static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>> @@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp
>> *intel_dp)
>>         uint32_t val = 0x0;
>>         const uint32_t link_entry_time =
>> EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>>
>> -       if (dev_priv->psr.link_standby)
>> -               val |= EDP_PSR_LINK_STANDBY;
>> -
>>         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>>                 val |= EDP_PSR_TP2_TP3_TIME_0us;
>>                 val |= EDP_PSR_TP1_TIME_0us;
>> @@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct
>> intel_dp *intel_dp)
>>                 return false;
>>         }
>>
>> +       if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
>> +                                   (dig_port->port != PORT_A))){
>> +               DRM_DEBUG_KMS("PSR condition failed: Link Standby
>> requested/needed but not supported on this platform\n");
>> +               return false;
>> +       }
>> +
>>         dev_priv->psr.source_ok = true;
>>         return true;
>>   }
>> @@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>         if (!intel_psr_match_conditions(intel_dp))
>>                 goto unlock;
>>
>> -       /* First we check VBT, but we must respect sink and source
>> -        * known restrictions */
>> -       dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>> -       if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
>> -               dev_priv->psr.link_standby = true;
>> -
>>         dev_priv->psr.busy_frontbuffer_bits = 0;
>>
>>         if (HAS_DDI(dev)) {
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Daniel Vetter]

On Mon, Mar 02, 2015 at 06:35:26PM +0000, Vivi, Rodrigo wrote:
> On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > > There are some cases like suspend/resume or dpms off/on sequences
> > > that can flush frontbuffer bits. In these cases features that relies
> > > on frontbuffer tracking can start working and user can stop getting
> > > screen updates on fbcon having impression the system is frozen.
> > > 
> > > So, let's make sure on fbcon write operation we also invalidate
> > > frontbuffer bits so we will be on the safest side with fbcon.
> > 
> > This is just a bandaid since you can always just directly access the
> > fbdev framebuffer. We really need to figure out why we have frontbuffer
> > bit flushes after we've invalidated them for fbcon and catch them all.
> 
> yeah, an ugly bandaid... Just to make PSR a bit more reliable without
> breaking fbcon environment when it gets enabled by default.
> 
> The issue is that on the logs I see:
> 
> 1.fbdev_blank dpms off
> 2. disable planes
> 3. flush frontbuffer bits
> --- blank stage ---
> 4. fbdev_blank dpms on

so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
Can you please attach full backtraces for steps 5&6?

> 5. enable planes
> 6. flush frontbuffer bits
> 
> So even if we put the invalidate there it will still get flushed.
> 
> Along with this sequence I see bunch of fillrect, cursor, imageblt,
> copyarea so what ever happens first right after the "6." will invalidate
> the frontbuffer_bits again so any direct write thought fbdev framebuffer
> will be safe enough.

Yeah generally fbcon starts out with drawing a bit black rectangle for the
entire screen, so this should generally work. But first I really want to
understand where that enable plane is coming from, before I give up and
apply this.

Thanks, Daniel

> 
> So yeah, with this bandaid for now I believe we are safe to enable psr
> by default while we continue the investigation to come up with a proper
> fix.
> 
> > -Daniel
> > 
> > > 
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_fbdev.c | 120 ++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 117 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> > > index 234a699..1b512f2 100644
> > > --- a/drivers/gpu/drm/i915/intel_fbdev.c
> > > +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> > > @@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
> > >  	return ret;
> > >  }
> > >  
> > > +void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
> > > +{
> > > +	struct drm_fb_helper *fb_helper = info->par;
> > > +	struct intel_fbdev *ifbdev =
> > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > +	cfb_fillrect(info, rect);
> > > +
> > > +	/*
> > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > +	 * atomic contexts and relies on that for emergency oops
> > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > +	 * now until we solve this for real.
> > > +	 */
> > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > +	/*
> > > +	 * There are some cases that can flush frontbuffer bits
> > > +	 * while we are still on console. So, let's make sure the fb obj
> > > +	 * gets invalidated on this write op so we don't have any risk
> > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > +	 * feature is enabled.
> > > +	 */
> > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > +}
> > > +
> > > +void intel_fbdev_copyarea(struct fb_info *info,
> > > +			  const struct fb_copyarea *region)\
> > > +{
> > > +	struct drm_fb_helper *fb_helper = info->par;
> > > +	struct intel_fbdev *ifbdev =
> > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > +	cfb_copyarea(info, region);
> > > +
> > > +	/*
> > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > +	 * atomic contexts and relies on that for emergency oops
> > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > +	 * now until we solve this for real.
> > > +	 */
> > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > +	/*
> > > +	 * There are some cases that can flush frontbuffer bits
> > > +	 * while we are still on console. So, let's make sure the fb obj
> > > +	 * gets invalidated on this write op so we don't have any risk
> > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > +	 * feature is enabled.
> > > +	 */
> > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > +}
> > > +
> > > +void intel_fbdev_imageblit(struct fb_info *info, const struct fb_image *image)
> > > +{
> > > +	struct drm_fb_helper *fb_helper = info->par;
> > > +	struct intel_fbdev *ifbdev =
> > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > +	cfb_imageblit(info, image);
> > > +
> > > +	/*
> > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > +	 * atomic contexts and relies on that for emergency oops
> > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > +	 * now until we solve this for real.
> > > +	 */
> > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > +	/*
> > > +	 * There are some cases that can flush frontbuffer bits
> > > +	 * while we are still on console. So, let's make sure the fb obj
> > > +	 * gets invalidated on this write op so we don't have any risk
> > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > +	 * feature is enabled.
> > > +	 */
> > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > +}
> > > +
> > > +int intel_fbdev_cursor(struct fb_info *info, struct fb_cursor *cursor)
> > > +{
> > > +	struct drm_fb_helper *fb_helper = info->par;
> > > +	struct intel_fbdev *ifbdev =
> > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > +	/*
> > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > +	 * atomic contexts and relies on that for emergency oops
> > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > +	 * now until we solve this for real.
> > > +	 */
> > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > +	/*
> > > +	 * There are some cases that can flush frontbuffer bits
> > > +	 * while we are still on console. So, let's make sure the fb obj
> > > +	 * gets invalidated on this write op so we don't have any risk
> > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > +	 * feature is enabled.
> > > +	 */
> > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static struct fb_ops intelfb_ops = {
> > >  	.owner = THIS_MODULE,
> > >  	.fb_check_var = drm_fb_helper_check_var,
> > >  	.fb_set_par = intel_fbdev_set_par,
> > > -	.fb_fillrect = cfb_fillrect,
> > > -	.fb_copyarea = cfb_copyarea,
> > > -	.fb_imageblit = cfb_imageblit,
> > > +	.fb_fillrect = intel_fbdev_fillrect,
> > > +	.fb_copyarea = intel_fbdev_copyarea,
> > > +	.fb_imageblit = intel_fbdev_imageblit,
> > > +	.fb_cursor = intel_fbdev_cursor,
> > >  	.fb_pan_display = drm_fb_helper_pan_display,
> > >  	.fb_blank = drm_fb_helper_blank,
> > >  	.fb_setcmap = drm_fb_helper_setcmap,
> > > -- 
> > > 1.9.3
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5865
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -5              278/278              273/278
ILK                 -8              308/308              300/308
SNB                 -1              284/284              283/284
IVB                                  380/380              380/380
BYT                                  294/294              294/294
HSW                 -1              387/387              386/387
BDW                 -2              316/316              314/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-sync      CRASH(3)PASS(6)      CRASH(2)
 PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(2)PASS(5)      CRASH(2)
*PNV  igt_gem_userptr_blits_minor-unsync-interruptible      PASS(4)      DMESG_WARN(1)PASS(1)
 PNV  igt_gen3_render_linear_blits      FAIL(3)PASS(5)      FAIL(2)
 PNV  igt_gen3_render_mixed_blits      FAIL(2)PASS(8)      FAIL(2)
*ILK  igt_gem_bad_length      PASS(2)      DMESG_WARN(1)PASS(1)
*ILK  igt_gem_exec_params_no-blt      PASS(2)      DMESG_WARN(1)PASS(1)
*ILK  igt_gem_exec_params_sol-reset-not-gen7      PASS(2)      DMESG_WARN(1)PASS(1)
*ILK  igt_gem_reloc_overflow_source-offset-negative-reloc-cpu      PASS(2)      DMESG_WARN(2)
*ILK  igt_gem_reloc_overflow_source-offset-negative-reloc-gtt      PASS(2)      DMESG_WARN(1)PASS(1)
*ILK  igt_gem_seqno_wrap      PASS(2)      DMESG_WARN(1)PASS(1)
 ILK  igt_gem_unfence_active_buffers      DMESG_WARN(1)PASS(2)      DMESG_WARN(1)PASS(1)
*ILK  igt_kms_addfb_small-bo      PASS(2)      DMESG_WARN(1)PASS(1)
*SNB  igt_gem_flink_bad-open      PASS(4)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_storedw_loop_blt      PASS(3)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(12)      TIMEOUT(1)PASS(1)
*BDW  igt_gem_ringfill_blitter-interruptible      PASS(2)      NO_RESULT(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Vivi, Rodrigo]

[-- Attachment #1: Type: text/plain, Size: 9354 bytes --]

On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
> On Mon, Mar 02, 2015 at 06:35:26PM +0000, Vivi, Rodrigo wrote:
> > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> > > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > > > There are some cases like suspend/resume or dpms off/on sequences
> > > > that can flush frontbuffer bits. In these cases features that relies
> > > > on frontbuffer tracking can start working and user can stop getting
> > > > screen updates on fbcon having impression the system is frozen.
> > > > 
> > > > So, let's make sure on fbcon write operation we also invalidate
> > > > frontbuffer bits so we will be on the safest side with fbcon.
> > > 
> > > This is just a bandaid since you can always just directly access the
> > > fbdev framebuffer. We really need to figure out why we have frontbuffer
> > > bit flushes after we've invalidated them for fbcon and catch them all.
> > 
> > yeah, an ugly bandaid... Just to make PSR a bit more reliable without
> > breaking fbcon environment when it gets enabled by default.
> > 
> > The issue is that on the logs I see:
> > 
> > 1.fbdev_blank dpms off
> > 2. disable planes
> > 3. flush frontbuffer bits
> > --- blank stage ---
> > 4. fbdev_blank dpms on
> 
> so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
> Can you please attach full backtraces for steps 5&6?

[  156.665517] [drm:intel_fbdev_set_par] PSR FBDEV modeset
[  759.232969] [drm:intel_fbdev_blank] PSR FBDEV blank normal
[  759.232987] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable
planes flush fb bits
[  897.313095] [drm:intel_fbdev_blank] PSR FBDEV unblank
[  897.313112] [drm:intel_crtc_control] PSR FBDEV crtc enable planes
[  897.527818] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
[  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable
planes flush fb bits

(full attached)

> 
> > 5. enable planes
> > 6. flush frontbuffer bits
> > 
> > So even if we put the invalidate there it will still get flushed.
> > 
> > Along with this sequence I see bunch of fillrect, cursor, imageblt,
> > copyarea so what ever happens first right after the "6." will invalidate
> > the frontbuffer_bits again so any direct write thought fbdev framebuffer
> > will be safe enough.
> 
> Yeah generally fbcon starts out with drawing a bit black rectangle for the
> entire screen, so this should generally work. But first I really want to
> understand where that enable plane is coming from, before I give up and
> apply this.

fair enough! thanks for all help here.

> 
> Thanks, Daniel
> 
> > 
> > So yeah, with this bandaid for now I believe we are safe to enable psr
> > by default while we continue the investigation to come up with a proper
> > fix.
> > 
> > > -Daniel
> > > 
> > > > 
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_fbdev.c | 120 ++++++++++++++++++++++++++++++++++++-
> > > >  1 file changed, 117 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> > > > index 234a699..1b512f2 100644
> > > > --- a/drivers/gpu/drm/i915/intel_fbdev.c
> > > > +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> > > > @@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
> > > >  	return ret;
> > > >  }
> > > >  
> > > > +void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
> > > > +{
> > > > +	struct drm_fb_helper *fb_helper = info->par;
> > > > +	struct intel_fbdev *ifbdev =
> > > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > > +
> > > > +	cfb_fillrect(info, rect);
> > > > +
> > > > +	/*
> > > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > > +	 * atomic contexts and relies on that for emergency oops
> > > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > > +	 * now until we solve this for real.
> > > > +	 */
> > > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > > +
> > > > +	/*
> > > > +	 * There are some cases that can flush frontbuffer bits
> > > > +	 * while we are still on console. So, let's make sure the fb obj
> > > > +	 * gets invalidated on this write op so we don't have any risk
> > > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > > +	 * feature is enabled.
> > > > +	 */
> > > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > > +}
> > > > +
> > > > +void intel_fbdev_copyarea(struct fb_info *info,
> > > > +			  const struct fb_copyarea *region)\
> > > > +{
> > > > +	struct drm_fb_helper *fb_helper = info->par;
> > > > +	struct intel_fbdev *ifbdev =
> > > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > > +
> > > > +	cfb_copyarea(info, region);
> > > > +
> > > > +	/*
> > > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > > +	 * atomic contexts and relies on that for emergency oops
> > > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > > +	 * now until we solve this for real.
> > > > +	 */
> > > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > > +
> > > > +	/*
> > > > +	 * There are some cases that can flush frontbuffer bits
> > > > +	 * while we are still on console. So, let's make sure the fb obj
> > > > +	 * gets invalidated on this write op so we don't have any risk
> > > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > > +	 * feature is enabled.
> > > > +	 */
> > > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > > +}
> > > > +
> > > > +void intel_fbdev_imageblit(struct fb_info *info, const struct fb_image *image)
> > > > +{
> > > > +	struct drm_fb_helper *fb_helper = info->par;
> > > > +	struct intel_fbdev *ifbdev =
> > > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > > +
> > > > +	cfb_imageblit(info, image);
> > > > +
> > > > +	/*
> > > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > > +	 * atomic contexts and relies on that for emergency oops
> > > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > > +	 * now until we solve this for real.
> > > > +	 */
> > > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > > +
> > > > +	/*
> > > > +	 * There are some cases that can flush frontbuffer bits
> > > > +	 * while we are still on console. So, let's make sure the fb obj
> > > > +	 * gets invalidated on this write op so we don't have any risk
> > > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > > +	 * feature is enabled.
> > > > +	 */
> > > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > > +}
> > > > +
> > > > +int intel_fbdev_cursor(struct fb_info *info, struct fb_cursor *cursor)
> > > > +{
> > > > +	struct drm_fb_helper *fb_helper = info->par;
> > > > +	struct intel_fbdev *ifbdev =
> > > > +		container_of(fb_helper, struct intel_fbdev, helper);
> > > > +
> > > > +	/*
> > > > +	 * FIXME: fbdev presumes that all callbacks also work from
> > > > +	 * atomic contexts and relies on that for emergency oops
> > > > +	 * printing. KMS totally doesn't do that and the locking here is
> > > > +	 * by far not the only place this goes wrong.  Ignore this for
> > > > +	 * now until we solve this for real.
> > > > +	 */
> > > > +	mutex_lock(&fb_helper->dev->struct_mutex);
> > > > +
> > > > +	/*
> > > > +	 * There are some cases that can flush frontbuffer bits
> > > > +	 * while we are still on console. So, let's make sure the fb obj
> > > > +	 * gets invalidated on this write op so we don't have any risk
> > > > +	 * of missing screen updates when PSR, FBC or any other power saving
> > > > +	 * feature is enabled.
> > > > +	 */
> > > > +	intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > > +	mutex_unlock(&fb_helper->dev->struct_mutex);
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  static struct fb_ops intelfb_ops = {
> > > >  	.owner = THIS_MODULE,
> > > >  	.fb_check_var = drm_fb_helper_check_var,
> > > >  	.fb_set_par = intel_fbdev_set_par,
> > > > -	.fb_fillrect = cfb_fillrect,
> > > > -	.fb_copyarea = cfb_copyarea,
> > > > -	.fb_imageblit = cfb_imageblit,
> > > > +	.fb_fillrect = intel_fbdev_fillrect,
> > > > +	.fb_copyarea = intel_fbdev_copyarea,
> > > > +	.fb_imageblit = intel_fbdev_imageblit,
> > > > +	.fb_cursor = intel_fbdev_cursor,
> > > >  	.fb_pan_display = drm_fb_helper_pan_display,
> > > >  	.fb_blank = drm_fb_helper_blank,
> > > >  	.fb_setcmap = drm_fb_helper_setcmap,
> > > > -- 
> > > > 1.9.3
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > 
> 


[-- Attachment #2: dmesg.full --]
[-- Type: text/plain, Size: 150686 bytes --]

[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 4.0.0-rc1+ (vivijim@rdvivi-talin) (gcc version 4.9.2 20141101 (Red Hat 4.9.2-1) (GCC) ) #69 SMP Thu Feb 26 16:18:50 PST 2015
[    0.000000] Command line: BOOT_IMAGE=/vmlinuz-4.0.0-rc1+ root=/dev/mapper/fedora-root ro rd.lvm.lv=fedora/swap rd.lvm.lv=fedora/root rd.luks.uuid=luks-bb84aed4-fb17-49b0-82cd-6d738ff09168 rhgb quiet drm.debug=0xe LANG=en_US.UTF-8 i915.enable_ips=0 i915.enable_execlists=0 i915.enable_ppgtt=1
[    0.000000] e820: BIOS-provided physical RAM map:
[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x0000000000087fff] usable
[    0.000000] BIOS-e820: [mem 0x0000000000088000-0x000000000009ffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x0000000094089fff] usable
[    0.000000] BIOS-e820: [mem 0x000000009408a000-0x0000000094989fff] ACPI NVS
[    0.000000] BIOS-e820: [mem 0x000000009498a000-0x000000009c48efff] usable
[    0.000000] BIOS-e820: [mem 0x000000009c48f000-0x000000009ce7efff] reserved
[    0.000000] BIOS-e820: [mem 0x000000009ce7f000-0x000000009cf7efff] ACPI NVS
[    0.000000] BIOS-e820: [mem 0x000000009cf7f000-0x000000009cffefff] ACPI data
[    0.000000] BIOS-e820: [mem 0x000000009cfff000-0x000000009cffffff] usable
[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000feb00000-0x00000000feb03fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000ffa00000-0x00000000ffffffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000025effffff] usable
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] e820: update [mem 0x93075018-0x93085057] usable ==> usable
[    0.000000] extended physical RAM map:
[    0.000000] reserve setup_data: [mem 0x0000000000000000-0x0000000000057fff] usable
[    0.000000] reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved
[    0.000000] reserve setup_data: [mem 0x0000000000059000-0x0000000000087fff] usable
[    0.000000] reserve setup_data: [mem 0x0000000000088000-0x000000000009ffff] reserved
[    0.000000] reserve setup_data: [mem 0x0000000000100000-0x0000000093075017] usable
[    0.000000] reserve setup_data: [mem 0x0000000093075018-0x0000000093085057] usable
[    0.000000] reserve setup_data: [mem 0x0000000093085058-0x0000000094089fff] usable
[    0.000000] reserve setup_data: [mem 0x000000009408a000-0x0000000094989fff] ACPI NVS
[    0.000000] reserve setup_data: [mem 0x000000009498a000-0x000000009c48efff] usable
[    0.000000] reserve setup_data: [mem 0x000000009c48f000-0x000000009ce7efff] reserved
[    0.000000] reserve setup_data: [mem 0x000000009ce7f000-0x000000009cf7efff] ACPI NVS
[    0.000000] reserve setup_data: [mem 0x000000009cf7f000-0x000000009cffefff] ACPI data
[    0.000000] reserve setup_data: [mem 0x000000009cfff000-0x000000009cffffff] usable
[    0.000000] reserve setup_data: [mem 0x00000000e0000000-0x00000000efffffff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000feb00000-0x00000000feb03fff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000fed10000-0x00000000fed19fff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[    0.000000] reserve setup_data: [mem 0x00000000ffa00000-0x00000000ffffffff] reserved
[    0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000025effffff] usable
[    0.000000] efi: EFI v2.40 by INSYDE Corp.
[    0.000000] efi:  SMBIOS=0x9c708000  ACPI 2.0=0x9cffe014 
[    0.000000] efi: mem00: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000000000-0x0000000000001000) (0MB)
[    0.000000] efi: mem01: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000001000-0x0000000000002000) (0MB)
[    0.000000] efi: mem02: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000002000-0x000000000000e000) (0MB)
[    0.000000] efi: mem03: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000000000e000-0x0000000000010000) (0MB)
[    0.000000] efi: mem04: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000010000-0x0000000000038000) (0MB)
[    0.000000] efi: mem05: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000038000-0x0000000000058000) (0MB)
[    0.000000] efi: mem06: [Reserved           |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000058000-0x0000000000059000) (0MB)
[    0.000000] efi: mem07: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000059000-0x000000000005e000) (0MB)
[    0.000000] efi: mem08: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000000005e000-0x000000000005f000) (0MB)
[    0.000000] efi: mem09: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000000005f000-0x0000000000060000) (0MB)
[    0.000000] efi: mem10: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000060000-0x0000000000088000) (0MB)
[    0.000000] efi: mem11: [Runtime Data       |RUN|  |  |  |   |WB|WT|WC|UC] range=[0x0000000000088000-0x000000000009f000) (0MB)
[    0.000000] efi: mem12: [Reserved           |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000000009f000-0x00000000000a0000) (0MB)
[    0.000000] efi: mem13: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000100000-0x0000000000c00000) (11MB)
[    0.000000] efi: mem14: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000c00000-0x0000000001000000) (4MB)
[    0.000000] efi: mem15: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000001000000-0x00000000022c8000) (18MB)
[    0.000000] efi: mem16: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000022c8000-0x0000000010000000) (221MB)
[    0.000000] efi: mem17: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000010000000-0x000000001000b000) (0MB)
[    0.000000] efi: mem18: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000001000b000-0x000000003de27000) (734MB)
[    0.000000] efi: mem19: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000003de27000-0x0000000040000000) (33MB)
[    0.000000] efi: mem20: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000040000000-0x000000006b01b000) (688MB)
[    0.000000] efi: mem21: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006b01b000-0x000000009095e000) (601MB)
[    0.000000] efi: mem22: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009095e000-0x000000009097e000) (0MB)
[    0.000000] efi: mem23: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009097e000-0x0000000093075000) (38MB)
[    0.000000] efi: mem24: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000093075000-0x000000009328e000) (2MB)
[    0.000000] efi: mem25: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009328e000-0x000000009408a000) (13MB)
[    0.000000] efi: mem26: [ACPI Memory NVS    |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009408a000-0x000000009498a000) (9MB)
[    0.000000] efi: mem27: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009498a000-0x0000000094990000) (0MB)
[    0.000000] efi: mem28: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000094990000-0x000000009499b000) (0MB)
[    0.000000] efi: mem29: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009499b000-0x000000009499f000) (0MB)
[    0.000000] efi: mem30: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009499f000-0x0000000094a78000) (0MB)
[    0.000000] efi: mem31: [Loader Code        |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000094a78000-0x0000000094b9f000) (1MB)
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[    0.000000] efi: mem33: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000979c4000-0x0000000097c7f000) (2MB)
[    0.000000] efi: mem34: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097c7f000-0x0000000097d17000) (0MB)
[    0.000000] efi: mem35: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097d17000-0x0000000097dad000) (0MB)
[    0.000000] efi: mem36: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097dad000-0x0000000097db2000) (0MB)
[    0.000000] efi: mem37: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097db2000-0x0000000097ed6000) (1MB)
[    0.000000] efi: mem38: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097ed6000-0x0000000097f11000) (0MB)
[    0.000000] efi: mem39: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f11000-0x0000000097f1a000) (0MB)
[    0.000000] efi: mem40: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f1a000-0x0000000097f40000) (0MB)
[    0.000000] efi: mem41: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f40000-0x0000000097f41000) (0MB)
[    0.000000] efi: mem42: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f41000-0x0000000097f6c000) (0MB)
[    0.000000] efi: mem43: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f6c000-0x0000000097f75000) (0MB)
[    0.000000] efi: mem44: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f75000-0x0000000097f76000) (0MB)
[    0.000000] efi: mem45: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097f76000-0x0000000097fb3000) (0MB)
[    0.000000] efi: mem46: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fb3000-0x0000000097fb5000) (0MB)
[    0.000000] efi: mem47: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fb5000-0x0000000097fb6000) (0MB)
[    0.000000] efi: mem48: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fb6000-0x0000000097fc0000) (0MB)
[    0.000000] efi: mem49: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fc0000-0x0000000097fc4000) (0MB)
[    0.000000] efi: mem50: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fc4000-0x0000000097fc8000) (0MB)
[    0.000000] efi: mem51: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fc8000-0x0000000097fc9000) (0MB)
[    0.000000] efi: mem52: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000097fc9000-0x00000000980f2000) (1MB)
[    0.000000] efi: mem53: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000980f2000-0x0000000098910000) (8MB)
[    0.000000] efi: mem54: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098910000-0x00000000989aa000) (0MB)
[    0.000000] efi: mem55: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000989aa000-0x00000000989ac000) (0MB)
[    0.000000] efi: mem56: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000989ac000-0x00000000989ad000) (0MB)
[    0.000000] efi: mem57: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000989ad000-0x00000000989b3000) (0MB)
[    0.000000] efi: mem58: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000989b3000-0x0000000098a2c000) (0MB)
[    0.000000] efi: mem59: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a2c000-0x0000000098a35000) (0MB)
[    0.000000] efi: mem60: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a35000-0x0000000098a8a000) (0MB)
[    0.000000] efi: mem61: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a8a000-0x0000000098a8c000) (0MB)
[    0.000000] efi: mem62: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a8c000-0x0000000098a8d000) (0MB)
[    0.000000] efi: mem63: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a8d000-0x0000000098a8f000) (0MB)
[    0.000000] efi: mem64: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098a8f000-0x0000000098abf000) (0MB)
[    0.000000] efi: mem65: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098abf000-0x0000000098ac2000) (0MB)
[    0.000000] efi: mem66: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098ac2000-0x0000000098b11000) (0MB)
[    0.000000] efi: mem67: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b11000-0x0000000098b12000) (0MB)
[    0.000000] efi: mem68: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b12000-0x0000000098b69000) (0MB)
[    0.000000] efi: mem69: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b69000-0x0000000098b6e000) (0MB)
[    0.000000] efi: mem70: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b6e000-0x0000000098b71000) (0MB)
[    0.000000] efi: mem71: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b71000-0x0000000098b72000) (0MB)
[    0.000000] efi: mem72: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b72000-0x0000000098b91000) (0MB)
[    0.000000] efi: mem73: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b91000-0x0000000098b92000) (0MB)
[    0.000000] efi: mem74: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b92000-0x0000000098b93000) (0MB)
[    0.000000] efi: mem75: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b93000-0x0000000098b94000) (0MB)
[    0.000000] efi: mem76: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b94000-0x0000000098b96000) (0MB)
[    0.000000] efi: mem77: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b96000-0x0000000098b97000) (0MB)
[    0.000000] efi: mem78: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098b97000-0x0000000098ba9000) (0MB)
[    0.000000] efi: mem79: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000098ba9000-0x000000009ba8f000) (46MB)
[    0.000000] efi: mem80: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009ba8f000-0x000000009c062000) (5MB)
[    0.000000] efi: mem81: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009c062000-0x000000009c48f000) (4MB)
[    0.000000] efi: mem82: [Runtime Code       |RUN|  |  |  |   |WB|WT|WC|UC] range=[0x000000009c48f000-0x000000009c68f000) (2MB)
[    0.000000] efi: mem83: [Runtime Data       |RUN|  |  |  |   |WB|WT|WC|UC] range=[0x000000009c68f000-0x000000009c98f000) (3MB)
[    0.000000] efi: mem84: [Reserved           |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009c98f000-0x000000009ce7f000) (4MB)
[    0.000000] efi: mem85: [ACPI Memory NVS    |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009ce7f000-0x000000009cf7f000) (1MB)
[    0.000000] efi: mem86: [ACPI Reclaim Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009cf7f000-0x000000009cfff000) (0MB)
[    0.000000] efi: mem87: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000009cfff000-0x000000009d000000) (0MB)
[    0.000000] efi: mem88: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000100000000-0x000000025f000000) (5616MB)
[    0.000000] efi: mem89: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000e0000000-0x00000000f0000000) (256MB)
[    0.000000] efi: mem90: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000feb00000-0x00000000feb04000) (0MB)
[    0.000000] efi: mem91: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000fec00000-0x00000000fec01000) (0MB)
[    0.000000] efi: mem92: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000fed10000-0x00000000fed1a000) (0MB)
[    0.000000] efi: mem93: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000fed1c000-0x00000000fed20000) (0MB)
[    0.000000] efi: mem94: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000fee00000-0x00000000fee01000) (0MB)
[    0.000000] efi: mem95: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000ffa00000-0x0000000100000000) (6MB)
[    0.000000] SMBIOS 2.7 present.
[    0.000000] DMI: LENOVO 80HE/VIUU4, BIOS A6CN38WW 09/30/2014
[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[    0.000000] e820: last_pfn = 0x25f000 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-BFFFF uncachable
[    0.000000]   C0000-E7FFF write-protect
[    0.000000]   E8000-EFFFF write-combining
[    0.000000]   F0000-FFFFF write-protect
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 0000000000 mask 7C00000000 write-back
[    0.000000]   1 base 009D000000 mask 7FFF000000 uncachable
[    0.000000]   2 base 009E000000 mask 7FFE000000 uncachable
[    0.000000]   3 base 00A0000000 mask 7FE0000000 uncachable
[    0.000000]   4 base 00C0000000 mask 7FC0000000 uncachable
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000]   8 disabled
[    0.000000]   9 disabled
[    0.000000] PAT configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- UC  
[    0.000000] e820: update [mem 0x9d000000-0xffffffff] usable ==> reserved
[    0.000000] e820: last_pfn = 0x9d000 max_arch_pfn = 0x400000000
[    0.000000] Base memory trampoline at [ffff880000032000] 32000 size 24576
[    0.000000] Using GB pages for direct mapping
[    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
[    0.000000]  [mem 0x00000000-0x000fffff] page 4k
[    0.000000] BRK [0x02004000, 0x02004fff] PGTABLE
[    0.000000] BRK [0x02005000, 0x02005fff] PGTABLE
[    0.000000] BRK [0x02006000, 0x02006fff] PGTABLE
[    0.000000] init_memory_mapping: [mem 0x25ee00000-0x25effffff]
[    0.000000]  [mem 0x25ee00000-0x25effffff] page 2M
[    0.000000] BRK [0x02007000, 0x02007fff] PGTABLE
[    0.000000] init_memory_mapping: [mem 0x240000000-0x25edfffff]
[    0.000000]  [mem 0x240000000-0x25edfffff] page 2M
[    0.000000] init_memory_mapping: [mem 0x220000000-0x23fffffff]
[    0.000000]  [mem 0x220000000-0x23fffffff] page 1G
[    0.000000] init_memory_mapping: [mem 0x00100000-0x94089fff]
[    0.000000]  [mem 0x00100000-0x001fffff] page 4k
[    0.000000]  [mem 0x00200000-0x3fffffff] page 2M
[    0.000000]  [mem 0x40000000-0x7fffffff] page 1G
[    0.000000]  [mem 0x80000000-0x93ffffff] page 2M
[    0.000000]  [mem 0x94000000-0x94089fff] page 4k
[    0.000000] init_memory_mapping: [mem 0x9498a000-0x9c48efff]
[    0.000000]  [mem 0x9498a000-0x949fffff] page 4k
[    0.000000]  [mem 0x94a00000-0x9c3fffff] page 2M
[    0.000000]  [mem 0x9c400000-0x9c48efff] page 4k
[    0.000000] BRK [0x02008000, 0x02008fff] PGTABLE
[    0.000000] BRK [0x02009000, 0x02009fff] PGTABLE
[    0.000000] init_memory_mapping: [mem 0x9cfff000-0x9cffffff]
[    0.000000]  [mem 0x9cfff000-0x9cffffff] page 4k
[    0.000000] init_memory_mapping: [mem 0x100000000-0x21fffffff]
[    0.000000]  [mem 0x100000000-0x21fffffff] page 1G
[    0.000000] RAMDISK: [mem 0x3de27000-0x3fffafff]
[    0.000000] ACPI: Early table checksum verification disabled
[    0.000000] ACPI: RSDP 0x000000009CFFE014 000024 (v02 LENOVO)
[    0.000000] ACPI: XSDT 0x000000009CFCB188 0000DC (v01 LENOVO CB-01    00000001      01000013)
[    0.000000] ACPI: FACP 0x000000009CFF0000 00010C (v05 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: DSDT 0x000000009CFDB000 00FFA6 (v02 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: FACS 0x000000009CF7A000 000040
[    0.000000] ACPI: UEFI 0x000000009CFFC000 000042 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: MSDM 0x000000009CFF5000 000055 (v03 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: ASPT 0x000000009CFF3000 000034 (v07 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: DBGP 0x000000009CFF1000 000034 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: LPIT 0x000000009CFEE000 000094 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: MCFG 0x000000009CFEC000 00003C (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFD6000 00067E (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFD5000 000473 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFCE000 005AFC (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFF6000 005FD2 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: BOOT 0x000000009CFF2000 000028 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: APIC 0x000000009CFED000 00008C (v03 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFD7000 00340B (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: SSDT 0x000000009CFD4000 000B74 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: ASF! 0x000000009CFF4000 0000A5 (v32 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: WDAT 0x000000009CFEB000 000224 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: UEFI 0x000000009CFFD000 000236 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: HPET 0x000000009CFEF000 000038 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: DMAR 0x000000009CFCD000 0000CC (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: CSRT 0x000000009CFCC000 0000C4 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: FPDT 0x000000009CFCA000 000044 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: BGRT 0x000000009CFC9000 000038 (v01 LENOVO CB-01    00000001 ACPI 00040000)
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] No NUMA configuration found
[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000025effffff]
[    0.000000] NODE_DATA(0) allocated [mem 0x25efe9000-0x25effcfff]
[    0.000000]  [ffffea0000000000-ffffea00097fffff] PMD -> [ffff880256600000-ffff88025e5fffff] on node 0
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
[    0.000000]   Normal   [mem 0x0000000100000000-0x000000025effffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
[    0.000000]   node   0: [mem 0x0000000000059000-0x0000000000087fff]
[    0.000000]   node   0: [mem 0x0000000000100000-0x0000000094089fff]
[    0.000000]   node   0: [mem 0x000000009498a000-0x000000009c48efff]
[    0.000000]   node   0: [mem 0x000000009cfff000-0x000000009cffffff]
[    0.000000]   node   0: [mem 0x0000000100000000-0x000000025effffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000025effffff]
[    0.000000] On node 0 totalpages: 2075414
[    0.000000]   DMA zone: 64 pages used for memmap
[    0.000000]   DMA zone: 1119 pages reserved
[    0.000000]   DMA zone: 3974 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 9903 pages used for memmap
[    0.000000]   DMA32 zone: 633744 pages, LIFO batch:31
[    0.000000]   Normal zone: 22464 pages used for memmap
[    0.000000]   Normal zone: 1437696 pages, LIFO batch:31
[    0.000000] tboot: non-0 tboot_addr but it is not of type E820_RESERVED
[    0.000000] Reserving Intel graphics stolen memory at 0x9e000000-0x9fffffff
[    0.000000] ACPI: PM-Timer IO Port: 0x1808
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0xff] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0xff] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0xff] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0xff] disabled)
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-39
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
[    0.000000] smpboot: Allowing 8 CPUs, 4 hotplug CPUs
[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
[    0.000000] PM: Registered nosave memory: [mem 0x00088000-0x0009ffff]
[    0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff]
[    0.000000] PM: Registered nosave memory: [mem 0x93075000-0x93075fff]
[    0.000000] PM: Registered nosave memory: [mem 0x93085000-0x93085fff]
[    0.000000] PM: Registered nosave memory: [mem 0x9408a000-0x94989fff]
[    0.000000] PM: Registered nosave memory: [mem 0x9c48f000-0x9ce7efff]
[    0.000000] PM: Registered nosave memory: [mem 0x9ce7f000-0x9cf7efff]
[    0.000000] PM: Registered nosave memory: [mem 0x9cf7f000-0x9cffefff]
[    0.000000] PM: Registered nosave memory: [mem 0x9d000000-0x9dffffff]
[    0.000000] PM: Registered nosave memory: [mem 0x9e000000-0x9fffffff]
[    0.000000] PM: Registered nosave memory: [mem 0xa0000000-0xdfffffff]
[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff]
[    0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfeafffff]
[    0.000000] PM: Registered nosave memory: [mem 0xfeb00000-0xfeb03fff]
[    0.000000] PM: Registered nosave memory: [mem 0xfeb04000-0xfebfffff]
[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfed0ffff]
[    0.000000] PM: Registered nosave memory: [mem 0xfed10000-0xfed19fff]
[    0.000000] PM: Registered nosave memory: [mem 0xfed1a000-0xfed1bfff]
[    0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff]
[    0.000000] PM: Registered nosave memory: [mem 0xfed20000-0xfedfffff]
[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xff9fffff]
[    0.000000] PM: Registered nosave memory: [mem 0xffa00000-0xffffffff]
[    0.000000] e820: [mem 0xa0000000-0xdfffffff] available for PCI devices
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1
[    0.000000] PERCPU: Embedded 32 pages/cpu @ffff88025ec00000 s92632 r8192 d30248 u262144
[    0.000000] pcpu-alloc: s92632 r8192 d30248 u262144 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 2041864
[    0.000000] Policy zone: Normal
[    0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.0.0-rc1+ root=/dev/mapper/fedora-root ro rd.lvm.lv=fedora/swap rd.lvm.lv=fedora/root rd.luks.uuid=luks-bb84aed4-fb17-49b0-82cd-6d738ff09168 rhgb quiet drm.debug=0xe LANG=en_US.UTF-8 i915.enable_ips=0 i915.enable_execlists=0 i915.enable_ppgtt=1
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340 using standard form
[    0.000000] Memory: 7967372K/8301656K available (7521K kernel code, 1153K rwdata, 3280K rodata, 1476K init, 1444K bss, 334284K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU dyntick-idle grace-period acceleration is enabled.
[    0.000000] NR_IRQS:4352 nr_irqs:760 16
[    0.000000] 	Offload RCU callbacks from all CPUs
[    0.000000] 	Offload RCU callbacks from CPUs: 0-7.
[    0.000000] Console: colour dummy device 80x25
[    0.000000] console [tty0] enabled
[    0.000000] hpet clockevent registered
[    0.000000] tsc: Fast TSC calibration using PIT
[    0.000000] tsc: Detected 1296.951 MHz processor
[    0.000053] Calibrating delay loop (skipped), value calculated using timer frequency.. 2593.90 BogoMIPS (lpj=1296951)
[    0.000058] pid_max: default: 32768 minimum: 301
[    0.000067] ACPI: Core revision 20150204
[    0.034872] ACPI: All ACPI Tables successfully acquired
[    0.039153] Security Framework initialized
[    0.039165] SELinux:  Initializing.
[    0.039177] SELinux:  Starting in permissive mode
[    0.040231] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
[    0.043177] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.044423] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
[    0.044442] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
[    0.044776] Initializing cgroup subsys blkio
[    0.044780] Initializing cgroup subsys devices
[    0.044783] Initializing cgroup subsys freezer
[    0.044787] Initializing cgroup subsys net_cls
[    0.044790] Initializing cgroup subsys perf_event
[    0.044793] Initializing cgroup subsys net_prio
[    0.044833] CPU: Physical Processor ID: 0
[    0.044835] CPU: Processor Core ID: 0
[    0.044842] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
[    0.044843] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
[    0.046574] mce: CPU supports 7 MCE banks
[    0.046596] CPU0: Thermal monitoring enabled (TM1)
[    0.046613] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
[    0.046615] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
[    0.047288] Freeing SMP alternatives memory: 24K (ffffffff81e93000 - ffffffff81e99000)
[    0.048767] Ignoring BGRT: invalid status 0 (expected 1)
[    0.054106] ftrace: allocating 27227 entries in 107 pages
[    0.074743] dmar: Host address width 39
[    0.074747] dmar: DRHD base: 0x000000fed90000 flags: 0x0
[    0.074757] dmar: IOMMU 0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e1ff0505e
[    0.074760] dmar: DRHD base: 0x000000fed91000 flags: 0x1
[    0.074771] dmar: IOMMU 1: reg_base_addr fed91000 ver 1:0 cap d2008c20660462 ecap f010da
[    0.074773] dmar: RMRR base: 0x0000009ce26000 end: 0x0000009ce45fff
[    0.074776] dmar: RMRR base: 0x0000009d800000 end: 0x0000009fffffff
[    0.074779] dmar: ANDD device: 1 name: \_SB.PCI0.SDMA
[    0.074782] IOAPIC id 2 under DRHD base  0xfed91000 IOMMU 1
[    0.074784] HPET id 0 under DRHD base 0xfed91000
[    0.075285] Your BIOS is broken and requested that x2apic be disabled.
This will slightly decrease performance.
Use 'intremap=no_x2apic_optout' to override BIOS request.
[    0.075309] Enabled IRQ remapping in xapic mode
[    0.075311] x2apic: IRQ remapping doesn't support X2APIC mode
[    0.076043] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.086062] TSC deadline timer enabled
[    0.086067] smpboot: CPU0: Intel(R) Processor 5Y70 CPU @ 1.10GHz (fam: 06, model: 3d, stepping: 04)
[    0.086106] Performance Events: PEBS fmt2+, generic architected perfmon, full-width counters, Intel PMU driver.
[    0.086115] ... version:                3
[    0.086117] ... bit width:              48
[    0.086118] ... generic registers:      4
[    0.086120] ... value mask:             0000ffffffffffff
[    0.086122] ... max period:             0000ffffffffffff
[    0.086124] ... fixed-purpose events:   3
[    0.086125] ... event mask:             000000070000000f
[    0.087416] x86: Booting SMP configuration:
[    0.087418] .... node  #0, CPUs:      #1
[    0.102488] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
[    0.102625]  #2 #3
[    0.132936] x86: Booted up 1 node, 4 CPUs
[    0.132941] smpboot: Total of 4 processors activated (10375.60 BogoMIPS)
[    0.141175] devtmpfs: initialized
[    0.146361] PM: Registering ACPI NVS region [mem 0x9408a000-0x94989fff] (9437184 bytes)
[    0.146556] PM: Registering ACPI NVS region [mem 0x9ce7f000-0x9cf7efff] (1048576 bytes)
[    0.146846] atomic64_test: passed for x86-64 platform with CX8 and with SSE
[    0.146850] pinctrl core: initialized pinctrl subsystem
[    0.146910] RTC time: 19:44:25, date: 03/03/15
[    0.147106] NET: Registered protocol family 16
[    0.153833] cpuidle: using governor menu
[    0.153988] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[    0.153991] ACPI: bus type PCI registered
[    0.153993] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[    0.154100] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[    0.154104] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
[    0.154648] PCI: Using configuration type 1 for base access
[    0.162441] ACPI: Added _OSI(Module Device)
[    0.162445] ACPI: Added _OSI(Processor Device)
[    0.162447] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.162449] ACPI: Added _OSI(Processor Aggregator Device)
[    0.172255] ACPI: Executed 16 blocks of module-level executable AML code
[    0.182385] ACPI: Dynamic OEM Table Load:
[    0.182406] ACPI: SSDT 0xFFFF880254809800 0003D3 (v01 PmRef  Cpu0Cst  00003001 INTL 20121220)
[    0.183981] ACPI: Dynamic OEM Table Load:
[    0.184000] ACPI: SSDT 0xFFFF880254DD2000 0005AA (v01 PmRef  ApIst    00003000 INTL 20121220)
[    0.185655] ACPI: Dynamic OEM Table Load:
[    0.185670] ACPI: SSDT 0xFFFF880254802C00 000119 (v01 PmRef  ApCst    00003000 INTL 20121220)
[    0.196670] ACPI: Interpreter enabled
[    0.196685] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20150204/hwxface-580)
[    0.196698] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150204/hwxface-580)
[    0.196737] ACPI: (supports S0 S3 S4 S5)
[    0.196739] ACPI: Using IOAPIC for interrupt routing
[    0.196788] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.197607] ACPI: Power Resource [PG00] (on)
[    0.198311] ACPI: Power Resource [PG01] (on)
[    0.198987] ACPI: Power Resource [PG02] (on)
[    0.214551] acpi ABCD0000:00: ACPI dock station (docks/bays count: 1)
[    0.217094] ACPI: Power Resource [FN00] (off)
[    0.217217] ACPI: Power Resource [FN01] (off)
[    0.217335] ACPI: Power Resource [FN02] (off)
[    0.217450] ACPI: Power Resource [FN03] (off)
[    0.217567] ACPI: Power Resource [FN04] (off)
[    0.219115] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
[    0.219125] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[    0.220555] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[    0.221877] PCI host bridge to bus 0000:00
[    0.221883] pci_bus 0000:00: root bus resource [bus 00-fe]
[    0.221886] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
[    0.221889] pci_bus 0000:00: root bus resource [io  0x0cf8-0x0cff]
[    0.221892] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
[    0.221895] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[    0.221898] pci_bus 0000:00: root bus resource [mem 0xa0000000-0xfeafffff window]
[    0.221911] pci 0000:00:00.0: [8086:1604] type 00 class 0x060000
[    0.222355] pci 0000:00:02.0: [8086:161e] type 00 class 0x030000
[    0.222377] pci 0000:00:02.0: reg 0x10: [mem 0xc0000000-0xc0ffffff 64bit]
[    0.222389] pci 0000:00:02.0: reg 0x18: [mem 0xb0000000-0xbfffffff 64bit pref]
[    0.222398] pci 0000:00:02.0: reg 0x20: [io  0x3000-0x303f]
[    0.222826] pci 0000:00:03.0: [8086:160c] type 00 class 0x040300
[    0.222842] pci 0000:00:03.0: reg 0x10: [mem 0xc1318000-0xc131bfff 64bit]
[    0.223295] pci 0000:00:04.0: [8086:1603] type 00 class 0x118000
[    0.223317] pci 0000:00:04.0: reg 0x10: [mem 0xc1310000-0xc1317fff 64bit]
[    0.223778] pci 0000:00:14.0: [8086:9cb1] type 00 class 0x0c0330
[    0.223804] pci 0000:00:14.0: reg 0x10: [mem 0xc1300000-0xc130ffff 64bit]
[    0.223894] pci 0000:00:14.0: PME# supported from D3hot D3cold
[    0.224249] pci 0000:00:14.0: System wakeup disabled by ACPI
[    0.224313] pci 0000:00:16.0: [8086:9cba] type 00 class 0x078000
[    0.224340] pci 0000:00:16.0: reg 0x10: [mem 0xc1321000-0xc132101f 64bit]
[    0.224441] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
[    0.224844] pci 0000:00:1b.0: [8086:9ca0] type 00 class 0x040300
[    0.224869] pci 0000:00:1b.0: reg 0x10: [mem 0xc131c000-0xc131ffff 64bit]
[    0.224960] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[    0.225311] pci 0000:00:1b.0: System wakeup disabled by ACPI
[    0.225370] pci 0000:00:1c.0: [8086:9c94] type 01 class 0x060400
[    0.225485] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[    0.225828] pci 0000:00:1c.0: System wakeup disabled by ACPI
[    0.225901] pci 0000:00:1f.0: [8086:9cc7] type 00 class 0x060100
[    0.226431] pci 0000:00:1f.2: [8086:9c83] type 00 class 0x010601
[    0.226452] pci 0000:00:1f.2: reg 0x10: [io  0x3088-0x308f]
[    0.226462] pci 0000:00:1f.2: reg 0x14: [io  0x3094-0x3097]
[    0.226475] pci 0000:00:1f.2: reg 0x18: [io  0x3080-0x3087]
[    0.226485] pci 0000:00:1f.2: reg 0x1c: [io  0x3090-0x3093]
[    0.226494] pci 0000:00:1f.2: reg 0x20: [io  0x3060-0x307f]
[    0.226506] pci 0000:00:1f.2: reg 0x24: [mem 0xc1324000-0xc13247ff]
[    0.226564] pci 0000:00:1f.2: PME# supported from D3hot
[    0.226949] pci 0000:00:1f.3: [8086:9ca2] type 00 class 0x0c0500
[    0.226968] pci 0000:00:1f.3: reg 0x10: [mem 0xc1320000-0xc13200ff 64bit]
[    0.226996] pci 0000:00:1f.3: reg 0x20: [io  0x3040-0x305f]
[    0.227416] pci 0000:00:1f.6: [8086:9ca4] type 00 class 0x118000
[    0.227454] pci 0000:00:1f.6: reg 0x10: [mem 0xc1323000-0xc1323fff 64bit]
[    0.228110] pci 0000:01:00.0: [14e4:43b1] type 00 class 0x028000
[    0.228153] pci 0000:01:00.0: reg 0x10: [mem 0xc1200000-0xc1207fff 64bit]
[    0.228183] pci 0000:01:00.0: reg 0x18: [mem 0xc1000000-0xc11fffff 64bit]
[    0.228386] pci 0000:01:00.0: supports D1 D2
[    0.228389] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.228446] pci 0000:01:00.0: System wakeup disabled by ACPI
[    0.231102] pci 0000:00:1c.0: PCI bridge to [bus 01]
[    0.231110] pci 0000:00:1c.0:   bridge window [mem 0xc1000000-0xc12fffff]
[    0.231163] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported)
[    0.234501] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 15) *7
[    0.234578] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15)
[    0.234651] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15)
[    0.234726] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 *10 11 12 14 15)
[    0.234799] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
[    0.234871] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
[    0.234943] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15)
[    0.235014] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
[    0.235794] ACPI: Enabled 6 GPEs in block 00 to 7F
[    0.236155] ACPI : EC: GPE = 0x34, I/O: command/status = 0x66, data = 0x62
[    0.236312] vgaarb: setting as boot device: PCI:0000:00:02.0
[    0.236315] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[    0.236319] vgaarb: loaded
[    0.236321] vgaarb: bridge control possible 0000:00:02.0
[    0.236479] SCSI subsystem initialized
[    0.236536] libata version 3.00 loaded.
[    0.236584] ACPI: bus type USB registered
[    0.236612] usbcore: registered new interface driver usbfs
[    0.236631] usbcore: registered new interface driver hub
[    0.236657] usbcore: registered new device driver usb
[    0.236846] PCI: Using ACPI for IRQ routing
[    0.244763] PCI: pci_cache_line_size set to 64 bytes
[    0.244807] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
[    0.244810] e820: reserve RAM buffer [mem 0x00088000-0x0008ffff]
[    0.244812] e820: reserve RAM buffer [mem 0x93075018-0x93ffffff]
[    0.244814] e820: reserve RAM buffer [mem 0x9408a000-0x97ffffff]
[    0.244816] e820: reserve RAM buffer [mem 0x9c48f000-0x9fffffff]
[    0.244819] e820: reserve RAM buffer [mem 0x9d000000-0x9fffffff]
[    0.244821] e820: reserve RAM buffer [mem 0x25f000000-0x25fffffff]
[    0.245021] NetLabel: Initializing
[    0.245023] NetLabel:  domain hash size = 128
[    0.245024] NetLabel:  protocols = UNLABELED CIPSOv4
[    0.245044] NetLabel:  unlabeled traffic allowed by default
[    0.245167] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[    0.245175] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
[    0.247221] Switched to clocksource hpet
[    0.257261] pnp: PnP ACPI init
[    0.257569] system 00:00: [io  0x06a4] has been reserved
[    0.257574] system 00:00: [io  0x06a0] has been reserved
[    0.257580] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.257936] system 00:01: [io  0x0680-0x069f] has been reserved
[    0.257940] system 00:01: [io  0xffff] has been reserved
[    0.257944] system 00:01: [io  0xffff] has been reserved
[    0.257947] system 00:01: [io  0xffff] has been reserved
[    0.257951] system 00:01: [io  0x1800-0x18fe] could not be reserved
[    0.257955] system 00:01: [io  0x164e-0x164f] has been reserved
[    0.257959] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.258041] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.258104] system 00:03: [io  0x1854-0x1857] has been reserved
[    0.258109] system 00:03: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[    0.258160] pnp 00:04: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.258957] system 00:05: [mem 0xfe102000-0xfe102fff] has been reserved
[    0.258961] system 00:05: [mem 0xfe104000-0xfe104fff] has been reserved
[    0.258965] system 00:05: [mem 0xfe106000-0xfe106fff] has been reserved
[    0.258969] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.259655] system 00:06: [mem 0xfed1c000-0xfed1ffff] has been reserved
[    0.259659] system 00:06: [mem 0xfed10000-0xfed17fff] has been reserved
[    0.259663] system 00:06: [mem 0xfed18000-0xfed18fff] has been reserved
[    0.259666] system 00:06: [mem 0xfed19000-0xfed19fff] has been reserved
[    0.259670] system 00:06: [mem 0xe0000000-0xefffffff] has been reserved
[    0.259674] system 00:06: [mem 0xfed20000-0xfed3ffff] has been reserved
[    0.259678] system 00:06: [mem 0xfed90000-0xfed93fff] could not be reserved
[    0.259681] system 00:06: [mem 0xfed45000-0xfed8ffff] has been reserved
[    0.259685] system 00:06: [mem 0xff000000-0xffffffff] could not be reserved
[    0.259689] system 00:06: [mem 0xfee00000-0xfeefffff] could not be reserved
[    0.259692] system 00:06: [mem 0xa0010000-0xa001ffff] has been reserved
[    0.259695] system 00:06: [mem 0xa0000000-0xa000ffff] has been reserved
[    0.259700] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.260371] pnp: PnP ACPI: found 7 devices
[    0.267682] pci 0000:00:1c.0: PCI bridge to [bus 01]
[    0.267691] pci 0000:00:1c.0:   bridge window [mem 0xc1000000-0xc12fffff]
[    0.267702] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
[    0.267705] pci_bus 0000:00: resource 5 [io  0x0cf8-0x0cff]
[    0.267708] pci_bus 0000:00: resource 6 [io  0x0d00-0xffff window]
[    0.267711] pci_bus 0000:00: resource 7 [mem 0x000a0000-0x000bffff window]
[    0.267714] pci_bus 0000:00: resource 8 [mem 0xa0000000-0xfeafffff window]
[    0.267717] pci_bus 0000:01: resource 1 [mem 0xc1000000-0xc12fffff]
[    0.267784] NET: Registered protocol family 2
[    0.268102] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
[    0.268364] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.268553] TCP: Hash tables configured (established 65536 bind 65536)
[    0.268582] TCP: reno registered
[    0.268602] UDP hash table entries: 4096 (order: 5, 131072 bytes)
[    0.268646] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
[    0.268749] NET: Registered protocol family 1
[    0.268770] pci 0000:00:02.0: Video device with shadowed ROM
[    0.268907] pci 0000:00:14.0: can't derive routing for PCI INT A
[    0.268910] pci 0000:00:14.0: PCI INT A: no GSI
[    0.270272] PCI: CLS 64 bytes, default 64
[    0.270344] Unpacking initramfs...
[    1.283742] Freeing initrd memory: 34640K (ffff88003de27000 - ffff88003fffb000)
[    1.283817] dmar: ACPI device "INTL9C60:00" under DMAR at fed91000 as 00:15.0
[    1.283833] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[    1.283837] software IO TLB [mem 0x8c95e000-0x9095e000] (64MB) mapped at [ffff88008c95e000-ffff88009095dfff]
[    1.283967] Simple Boot Flag at 0x44 set to 0x1
[    1.284291] microcode: CPU0 sig=0x306d4, pf=0x80, revision=0xe
[    1.284304] microcode: CPU1 sig=0x306d4, pf=0x80, revision=0xe
[    1.284313] microcode: CPU2 sig=0x306d4, pf=0x80, revision=0xe
[    1.284323] microcode: CPU3 sig=0x306d4, pf=0x80, revision=0xe
[    1.284397] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[    1.284944] AVX2 version of gcm_enc/dec engaged.
[    1.284946] AES CTR mode by8 optimization enabled
[    1.288342] alg: No test for __gcm-aes-aesni (__driver-gcm-aes-aesni)
[    1.289022] futex hash table entries: 2048 (order: 5, 131072 bytes)
[    1.289056] Initialise system trusted keyring
[    1.289091] audit: initializing netlink subsys (disabled)
[    1.289114] audit: type=2000 audit(1425411865.267:1): initialized
[    1.289591] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    1.291922] zpool: loaded
[    1.292195] VFS: Disk quotas dquot_6.5.2
[    1.292252] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.292933] Key type big_key registered
[    1.292940] SELinux:  Registering netfilter hooks
[    1.294249] alg: No test for stdrng (krng)
[    1.294263] NET: Registered protocol family 38
[    1.294271] Key type asymmetric registered
[    1.294275] Asymmetric key parser 'x509' registered
[    1.294335] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
[    1.294388] io scheduler noop registered
[    1.294392] io scheduler deadline registered
[    1.294449] io scheduler cfq registered (default)
[    1.294902] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt
[    1.294906] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[    1.294911] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded
[    1.294921] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[    1.294947] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[    1.294994] efifb: probing for efifb
[    1.295056] efifb: framebuffer at 0xb0000000, mapped to 0xffffc90010f00000, using 22500k, total 22500k
[    1.295059] efifb: mode is 3200x1800x32, linelength=12800, pages=1
[    1.295060] efifb: scrolling: redraw
[    1.295063] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[    1.316735] Console: switching to colour frame buffer device 400x112
[    1.337323] fb0: EFI VGA frame buffer device
[    1.337338] intel_idle: MWAIT substates: 0x11142120
[    1.337341] intel_idle: v0.4 model 0x3D
[    1.337342] intel_idle: lapic_timer_reliable_states 0xffffffff
[    1.337819] ACPI: AC Adapter [ADP1] (on-line)
[    1.338021] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
[    1.338063] ACPI: Lid Switch [LID0]
[    1.338120] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
[    1.338125] ACPI: Power Button [PWRB]
[    1.338174] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2
[    1.338178] ACPI: Sleep Button [SLPB]
[    1.338231] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
[    1.338234] ACPI: Power Button [PWRF]
[    1.339350] thermal LNXTHERM:00: registered as thermal_zone0
[    1.339354] ACPI: Thermal Zone [TZ00] (28 C)
[    1.339524] thermal LNXTHERM:01: registered as thermal_zone1
[    1.339526] ACPI: Thermal Zone [TZ01] (30 C)
[    1.339609] GHES: HEST is not enabled!
[    1.339741] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    2.286541] tsc: Refined TSC clocksource calibration: 1296.997 MHz
[    3.287336] Switched to clocksource tsc
[    3.849295] Non-volatile memory driver v1.3
[    3.849386] Linux agpgart interface v0.103
[    3.849687] ahci 0000:00:1f.2: version 3.0
[    3.849905] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[    3.849911] ahci 0000:00:1f.2: flags: 64bit ncq pm led clo only pio slum part deso sadm sds apst 
[    3.850208] scsi host0: ahci
[    3.850291] ata1: SATA max UDMA/133 abar m2048@0xc1324000 port 0xc1324100 irq 43
[    3.850437] libphy: Fixed MDIO Bus: probed
[    3.850697] xhci_hcd 0000:00:14.0: can't derive routing for PCI INT A
[    3.850701] xhci_hcd 0000:00:14.0: PCI INT A: no GSI
[    3.850728] xhci_hcd 0000:00:14.0: xHCI Host Controller
[    3.850839] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
[    3.850952] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00001810
[    3.850964] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
[    3.851066] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    3.851068] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.851071] usb usb1: Product: xHCI Host Controller
[    3.851073] usb usb1: Manufacturer: Linux 4.0.0-rc1+ xhci-hcd
[    3.851076] usb usb1: SerialNumber: 0000:00:14.0
[    3.851293] hub 1-0:1.0: USB hub found
[    3.851307] hub 1-0:1.0: 11 ports detected
[    3.852911] ACPI: Battery Slot [BAT1] (battery present)
[    3.854784] xhci_hcd 0000:00:14.0: xHCI Host Controller
[    3.854874] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
[    3.854919] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[    3.854922] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    3.854924] usb usb2: Product: xHCI Host Controller
[    3.854927] usb usb2: Manufacturer: Linux 4.0.0-rc1+ xhci-hcd
[    3.854929] usb usb2: SerialNumber: 0000:00:14.0
[    3.855112] hub 2-0:1.0: USB hub found
[    3.855123] hub 2-0:1.0: 4 ports detected
[    3.855830] usb: failed to peer usb2-port4 and usb1-port3 by location (usb2-port4:none) (usb1-port3:usb2-port3)
[    3.855833] usb usb2-port4: failed to peer to usb1-port3 (-16)
[    3.855835] usb: port power management may be unreliable
[    3.855931] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.855941] ehci-pci: EHCI PCI platform driver
[    3.855959] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    3.855966] ohci-pci: OHCI PCI platform driver
[    3.855982] uhci_hcd: USB Universal Host Controller Interface driver
[    3.856054] usbcore: registered new interface driver usbserial
[    3.856064] usbcore: registered new interface driver usbserial_generic
[    3.856073] usbserial: USB Serial support registered for generic
[    3.856118] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
[    3.856120] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
[    3.857569] serio: i8042 KBD port at 0x60,0x64 irq 1
[    3.857714] mousedev: PS/2 mouse device common for all mice
[    3.858191] rtc_cmos 00:02: RTC can wake from S4
[    3.858376] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
[    3.858415] rtc_cmos 00:02: alarms up to one month, 242 bytes nvram, hpet irqs
[    3.858515] device-mapper: uevent: version 1.0.3
[    3.858613] device-mapper: ioctl: 4.30.0-ioctl (2014-12-22) initialised: dm-devel@redhat.com
[    3.858703] Intel P-state driver initializing.
[    3.860018] EFI Variables Facility v0.08 2004-May-17
[    3.871205] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
[    3.892487] hidraw: raw HID events driver (C) Jiri Kosina
[    3.892584] usbcore: registered new interface driver usbhid
[    3.892585] usbhid: USB HID core driver
[    3.892628] drop_monitor: Initializing network drop monitor service
[    3.892697] ip_tables: (C) 2000-2006 Netfilter Core Team
[    3.892742] TCP: cubic registered
[    3.892744] Initializing XFRM netlink socket
[    3.892856] NET: Registered protocol family 10
[    3.893007] mip6: Mobile IPv6
[    3.893010] NET: Registered protocol family 17
[    3.893401] Loading compiled-in X.509 certificates
[    3.894117] Loaded X.509 cert 'Magrathea: Glacier signing key: 97b745a891c9430fcc725c0832700658d063a4db'
[    3.894126] registered taskstats version 1
[    3.894416]   Magic number: 7:904:747
[    3.894510] rtc_cmos 00:02: setting system clock to 2015-03-03 19:44:28 UTC (1425411868)
[    3.894592] PM: Hibernation image not present or could not be loaded.
[    4.155698] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[    4.157787] ata1.00: ACPI cmd ef/10:09:00:00:00:b0 (SET FEATURES) succeeded
[    4.157996] usb 2-2: new SuperSpeed USB device number 2 using xhci_hcd
[    4.158056] ata1.00: failed to get NCQ Send/Recv Log Emask 0x1
[    4.158060] ata1.00: ATA-9: SAMSUNG MZNTE256HMHP-000L2, EXT26L0Q, max UDMA/133
[    4.158063] ata1.00: 500118192 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
[    4.158490] ata1.00: ACPI cmd ef/10:09:00:00:00:b0 (SET FEATURES) succeeded
[    4.158760] ata1.00: failed to get NCQ Send/Recv Log Emask 0x1
[    4.158854] ata1.00: configured for UDMA/133
[    4.159180] scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG MZNTE256 6L0Q PQ: 0 ANSI: 5
[    4.159637] sd 0:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB)
[    4.159701] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    4.159747] sd 0:0:0:0: [sda] Write Protect is off
[    4.159751] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    4.159804] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    4.163974]  sda: sda1 sda2 sda3
[    4.164463] sd 0:0:0:0: [sda] Attached SCSI disk
[    4.164885] Freeing unused kernel memory: 1476K (ffffffff81d22000 - ffffffff81e93000)
[    4.164889] Write protecting the kernel read-only data: 12288k
[    4.165262] Freeing unused kernel memory: 660K (ffff88000175b000 - ffff880001800000)
[    4.165514] Freeing unused kernel memory: 816K (ffff880001b34000 - ffff880001c00000)
[    4.177195] usb 2-2: New USB device found, idVendor=0b95, idProduct=1790
[    4.177198] usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    4.177199] usb 2-2: Product: AX88179
[    4.177201] usb 2-2: Manufacturer: ASIX Elec. Corp.
[    4.177202] usb 2-2: SerialNumber: 000000000000C2
[    4.207833] usb 1-4: new full-speed USB device number 2 using xhci_hcd
[    4.214165] random: systemd urandom read with 19 bits of entropy available
[    4.374208] usb 1-4: New USB device found, idVendor=0489, idProduct=e07a
[    4.374213] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    4.374216] usb 1-4: Product: BCM20702A0
[    4.374218] usb 1-4: Manufacturer: Broadcom Corp
[    4.374220] usb 1-4: SerialNumber: B01041F2D77E
[    4.476026] sdhci: Secure Digital Host Controller Interface driver
[    4.476029] sdhci: Copyright(c) Pierre Ossman
[    4.500723] alg: No test for crc32 (crc32-pclmul)
[    4.531868] usb 1-7: new high-speed USB device number 3 using xhci_hcd
[    4.543637] [drm] Initialized drm 1.1.0 20060810
[    4.732432] Setting dangerous option enable_ppgtt - tainting kernel
[    4.733611] [drm:i915_dump_device_info] i915 device info: gen=8, pciid=0x161e rev=0x08 flags=is_mobile,need_gfx_hws,has_fbc,has_hotplug,has_llc,has_ddi,has_fpga_dbg,
[    4.733627] [drm:intel_detect_pch] Found LynxPoint LP PCH
[    4.733730] [drm] Memory usable by graphics device = 4096M
[    4.733731] [drm:i915_gem_gtt_init] GMADR size = 256M
[    4.733732] [drm:i915_gem_gtt_init] GTT stolen size = 32M
[    4.733733] [drm:i915_gem_gtt_init] ppgtt mode: 1
[    4.733735] checking generic (b0000000 15f9000) vs hw (b0000000 10000000)
[    4.733736] fb: switching to inteldrmfb from EFI VGA
[    4.733764] Console: switching to colour dummy device 80x25
[    4.733903] [drm] Replacing VGA console driver
[    4.734502] [drm:intel_opregion_setup] graphic opregion physical addr: 0x9cf73018
[    4.734508] [drm:intel_opregion_setup] Public ACPI methods supported
[    4.734509] [drm:intel_opregion_setup] SWSCI supported
[    4.739044] usb 1-7: New USB device found, idVendor=5986, idProduct=0535
[    4.739049] usb 1-7: New USB device strings: Mfr=3, Product=1, SerialNumber=2
[    4.739052] usb 1-7: Product: Lenovo EasyCamera
[    4.739055] usb 1-7: Manufacturer: Generic
[    4.739057] usb 1-7: SerialNumber: 200901010001
[    4.740038] [drm:swsci_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700583
[    4.740042] [drm:intel_opregion_setup] ASLE supported
[    4.740214] [drm:intel_device_info_runtime_init] slice total: 0
[    4.740217] [drm:intel_device_info_runtime_init] subslice total: 0
[    4.740220] [drm:intel_device_info_runtime_init] subslice per slice: 0
[    4.740223] [drm:intel_device_info_runtime_init] EU total: 0
[    4.740226] [drm:intel_device_info_runtime_init] EU per subslice: 0
[    4.740229] [drm:intel_device_info_runtime_init] has slice power gating: n
[    4.740232] [drm:intel_device_info_runtime_init] has subslice power gating: n
[    4.740237] [drm:intel_device_info_runtime_init] has EU power gating: n
[    4.740240] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    4.740242] [drm] Driver supports precise vblank timestamp query.
[    4.740245] [drm:init_vbt_defaults] Set default to SSC at 120000 kHz
[    4.740248] [drm:validate_vbt] Using VBT from OpRegion: $VBT HASWELL        d
[    4.740251] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
[    4.740253] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
[    4.740256] [drm:parse_lfp_panel_data] DRRS supported mode is static
[    4.740259] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
[    4.740263] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 0 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x8 0xa
[    4.740265] [drm:parse_lfp_panel_data] VBT initial LVDS value 30033c
[    4.740268] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255
[    4.740271] [drm:parse_sdvo_panel_data] Found SDVO panel mode in BIOS VBT tables:
[    4.740274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
[    4.740276] [drm:parse_sdvo_device_mapping] No SDVO device info is found in VBT
[    4.740279] [drm:parse_driver_features] DRRS State Enabled:0
[    4.740282] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
[    4.740284] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0
[    4.740287] [drm:parse_ddi_port] Port C VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
[    4.740289] [drm:parse_ddi_port] VBT HDMI level shift for port C: 15
[    4.740301] [drm:intel_dsm_pci_probe] no _DSM method for intel device
[    4.740309] [drm:i915_gem_init_stolen] found 33554432 bytes of stolen memory at 9e000000
[    4.740313] [drm:intel_display_power_get] enabling always-on
[    4.740314] [drm:intel_display_power_get] enabling display
[    4.740413] [drm:intel_print_wm_latency] Primary WM0 latency 20 (2.0 usec)
[    4.740417] [drm:intel_print_wm_latency] Primary WM1 latency 50 (25.0 usec)
[    4.740419] [drm:intel_print_wm_latency] Primary WM2 latency 90 (45.0 usec)
[    4.740422] [drm:intel_print_wm_latency] Primary WM3 latency 130 (65.0 usec)
[    4.740424] [drm:intel_print_wm_latency] Primary WM4 latency 160 (80.0 usec)
[    4.740426] [drm:intel_print_wm_latency] Sprite WM0 latency 20 (2.0 usec)
[    4.740428] [drm:intel_print_wm_latency] Sprite WM1 latency 50 (25.0 usec)
[    4.740430] [drm:intel_print_wm_latency] Sprite WM2 latency 90 (45.0 usec)
[    4.740432] [drm:intel_print_wm_latency] Sprite WM3 latency 130 (65.0 usec)
[    4.740434] [drm:intel_print_wm_latency] Sprite WM4 latency 160 (80.0 usec)
[    4.740436] [drm:intel_print_wm_latency] Cursor WM0 latency 20 (2.0 usec)
[    4.740438] [drm:intel_print_wm_latency] Cursor WM1 latency 50 (25.0 usec)
[    4.740440] [drm:intel_print_wm_latency] Cursor WM2 latency 90 (45.0 usec)
[    4.740442] [drm:intel_print_wm_latency] Cursor WM3 latency 130 (65.0 usec)
[    4.740444] [drm:intel_print_wm_latency] Cursor WM4 latency 160 (80.0 usec)
[    4.740447] [drm:intel_modeset_init] 3 display pipes available.
[    4.740465] [drm:intel_ddi_pll_init] CDCLK running at 450000KHz
[    4.740469] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    4.740786] [drm:intel_dp_init_connector] Adding eDP connector on port A
[    4.740866] [drm:intel_dp_init_panel_power_sequencer] cur t1_t3 2000 t8 0 t9 2000 t10 500 t11_t12 6000
[    4.740870] [drm:intel_dp_init_panel_power_sequencer] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
[    4.740874] [drm:intel_dp_init_panel_power_sequencer] panel power up delay 200, power down delay 50, power cycle delay 600
[    4.740877] [drm:intel_dp_init_panel_power_sequencer] backlight on delay 1, off delay 200
[    4.740882] [drm:intel_dp_aux_init] registering DPDDC-A bus for card0-eDP-1
[    4.740993] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[    4.741003] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
[    4.741438] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 40 00 00 01 c0 02 00 00 00 1f 0b 00
[    4.741745] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
[    4.741747] [drm:intel_dp_get_dpcd] Displayport TPS3 supported
[    4.741756] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06
[    4.765095] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[    4.765097] [drm:intel_dp_drrs_init] VBT doesn't support DRRS
[    4.765101] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, enabled, brightness 937/937
[    4.771064] [drm:intel_modeset_readout_hw_state] [CRTC:20] hw state readout: enabled
[    4.771069] [drm:intel_modeset_readout_hw_state] [CRTC:24] hw state readout: disabled
[    4.771072] [drm:intel_modeset_readout_hw_state] [CRTC:28] hw state readout: disabled
[    4.771075] [drm:intel_modeset_readout_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
[    4.771078] [drm:intel_modeset_readout_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
[    4.771084] [drm:intel_modeset_readout_hw_state] [ENCODER:30:TMDS-30] hw state readout: enabled, pipe A
[    4.771087] [drm:intel_modeset_readout_hw_state] [ENCODER:39:TMDS-39] hw state readout: disabled, pipe A
[    4.771090] [drm:intel_modeset_readout_hw_state] [CONNECTOR:31:eDP-1] hw state readout: enabled
[    4.771093] [drm:intel_modeset_readout_hw_state] [CONNECTOR:40:HDMI-A-1] hw state readout: disabled
[    4.771098] [drm:intel_dump_pipe_config] [CRTC:20][setup_hw_state] config for pipe A
[    4.771100] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    4.771102] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    4.771104] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.771107] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 350797, link_n: 524288, tu: 64
[    4.771109] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    4.771111] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    4.771113] [drm:intel_dump_pipe_config] requested mode:
[    4.771116] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 3200 0 0 0 1800 0 0 0 0x0 0x0
[    4.771118] [drm:intel_dump_pipe_config] adjusted mode:
[    4.771121] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
[    4.771124] [drm:intel_dump_crtc_timings] crtc timings: 361309 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x0 flags: 0xa
[    4.771126] [drm:intel_dump_pipe_config] port clock: 540000
[    4.771128] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    4.771130] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    4.771132] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x0c800708, enabled
[    4.771134] [drm:intel_dump_pipe_config] ips: 0
[    4.771135] [drm:intel_dump_pipe_config] double wide: 0
[    4.771139] [drm:intel_dump_pipe_config] [CRTC:24][setup_hw_state] config for pipe B
[    4.771141] [drm:intel_dump_pipe_config] cpu_transcoder: B
[    4.771143] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[    4.771145] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.771147] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.771150] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    4.771151] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    4.771153] [drm:intel_dump_pipe_config] requested mode:
[    4.771155] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    4.771157] [drm:intel_dump_pipe_config] adjusted mode:
[    4.771160] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    4.771162] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[    4.771164] [drm:intel_dump_pipe_config] port clock: 0
[    4.771166] [drm:intel_dump_pipe_config] pipe src size: 0x0
[    4.771168] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    4.771169] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    4.771171] [drm:intel_dump_pipe_config] ips: 0
[    4.771173] [drm:intel_dump_pipe_config] double wide: 0
[    4.771175] [drm:intel_dump_pipe_config] [CRTC:28][setup_hw_state] config for pipe C
[    4.771177] [drm:intel_dump_pipe_config] cpu_transcoder: C
[    4.771179] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[    4.771181] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.771183] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.771185] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    4.771187] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    4.771188] [drm:intel_dump_pipe_config] requested mode:
[    4.771191] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    4.771192] [drm:intel_dump_pipe_config] adjusted mode:
[    4.771195] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    4.771198] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[    4.771199] [drm:intel_dump_pipe_config] port clock: 0
[    4.771201] [drm:intel_dump_pipe_config] pipe src size: 0x0
[    4.771203] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    4.771205] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    4.771206] [drm:intel_dump_pipe_config] ips: 0
[    4.771208] [drm:intel_dump_pipe_config] double wide: 0
[    4.771217] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
[    4.771220] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
[    4.771223] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
[    4.771225] [drm:check_crtc_state] [CRTC:20]
[    4.771234] [drm:check_crtc_state] [CRTC:24]
[    4.771237] [drm:check_crtc_state] [CRTC:28]
[    4.771239] [drm:check_shared_dpll_state] WRPLL 1
[    4.771241] [drm:check_shared_dpll_state] WRPLL 2
[    4.771248] [drm:ironlake_get_initial_plane_config] pipe A with fb: size=3200x1800@32, offset=0, pitch 12800, size 0x15f9000
[    4.771251] [drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=15f9000
[    4.771257] [drm:i915_pages_create_for_stolen] offset=0x0, size=23040000
[    4.771262] [drm:intel_alloc_plane_obj] plane fb obj ffff88024fd88000
[    4.771266] [drm:i915_gem_setup_global_gtt] reserving preallocated space: 0 + 15f9000
[    4.771269] [drm:i915_gem_setup_global_gtt] clearing unused GTT space: [15f9000, fffff000]
[    4.775160] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (0 wasted)
[    4.775162] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (0 wasted)
[    4.775201] [drm:i915_gem_context_init] HW context support initialized
[    4.775207] [drm:init_status_page] render ring hws offset: 0x0160b000
[    4.775253] [drm:intel_init_pipe_control] render ring pipe control offset: 0x0162c000
[    4.775257] [drm:init_status_page] bsd ring hws offset: 0x0162d000
[    4.775295] [drm:init_status_page] blitter ring hws offset: 0x0164e000
[    4.775329] [drm:init_status_page] video enhancement ring hws offset: 0x0166f000
[    4.775430] [drm:intel_ring_workarounds_emit] Number of Workarounds emitted: 7
[    4.775667] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered
[    4.775701] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[    4.775704] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[    4.776037] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[    4.776346] [drm:intel_dp_probe_oui] Branch OUI: 000000
[    4.776350] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] status updated from 3 to 1
[    4.776360] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[    4.776363] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[    4.776365] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    4.776367] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[    4.776368] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[    4.776369] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[    4.776534] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[    4.776536] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[    4.776538] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] status updated from 3 to 2
[    4.776540] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[    4.776542] [drm:drm_setup_crtcs] 
[    4.776543] [drm:drm_enable_connectors] connector 31 enabled? yes
[    4.776544] [drm:drm_enable_connectors] connector 40 enabled? no
[    4.776546] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1
[    4.776547] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0
[    4.776548] [drm:intel_fb_initial_config] connector eDP-1 on pipe A [CRTC:20]: 3200x1800
[    4.776549] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
[    4.776551] [drm:drm_setup_crtcs] desired mode 3200x1800 set on crtc 20 (0,0)
[    4.776552] [drm:intelfb_create] no BIOS fb, allocating a new one
[    4.776554] [drm:i915_gem_object_create_stolen] creating stolen object: size=15f9000
[    4.777670] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[    4.777815] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input5
[    4.777920] [drm] Initialized i915 1.6.0 20150214 for 0000:00:02.0 on minor 0
[    4.790457] [drm:intelfb_create] allocated 3200x1800 fb: 0x01691000, bo ffff88024dd14000
[    4.790531] fbcon: inteldrmfb (fb0) is primary device
[    4.790572] [drm:intel_fbdev_set_par] PSR FBDEV modeset
[    4.790590] [drm:intel_fbc_update] disabled per chip default
[    4.790602] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[    4.790603] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
[    4.790605] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    4.790606] [drm:drm_mode_debug_printmodeline] Modeline 43:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    4.790607] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
[    4.790608] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    4.790609] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    4.790610] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    4.790612] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    4.790616] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    4.790616] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    4.790617] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    4.790620] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    4.790620] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    4.790621] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    4.790621] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    4.790622] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    4.790623] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    4.790624] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    4.790624] [drm:intel_dump_pipe_config] requested mode:
[    4.790625] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    4.790626] [drm:intel_dump_pipe_config] adjusted mode:
[    4.790627] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    4.790628] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    4.790628] [drm:intel_dump_pipe_config] port clock: 540000
[    4.790629] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    4.790629] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    4.790630] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    4.790630] [drm:intel_dump_pipe_config] ips: 0
[    4.790631] [drm:intel_dump_pipe_config] double wide: 0
[    4.790634] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable planes flush fb bits
[    4.792042] [drm:intel_edp_backlight_off] 
[    4.806608] ax88179_178a 2-2:1.0 eth0: register 'ax88179_178a' at usb-0000:00:14.0-2, ASIX AX88179 USB 3.0 Gigabit Ethernet, 9c:eb:e8:10:58:6c
[    4.806640] usbcore: registered new interface driver ax88179_178a
[    4.807652] ax88179_178a 2-2:1.0 enp0s20u2: renamed from eth0
[    4.898168] usb 1-8: new full-speed USB device number 4 using xhci_hcd
[    4.993198] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[    4.999395] [drm:edp_panel_off] Turn eDP port A panel power off
[    4.999399] [drm:wait_panel_off] Wait for panel power off time
[    4.999404] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
[    5.054284] [drm:wait_panel_status] Wait complete
[    5.054299] [drm:intel_display_power_put] disabling display
[    5.054301] [drm:hsw_set_power_well] Requesting to disable the power well
[    5.054323] [drm:__intel_set_mode] PSR FBDEV crtc enable planes
[    5.054341] [drm:edp_panel_on] Turn eDP port A panel power on
[    5.054343] [drm:wait_panel_power_cycle] Wait for panel power cycle
[    5.076199] usb 1-8: New USB device found, idVendor=048d, idProduct=8386
[    5.076201] usb 1-8: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    5.076203] usb 1-8: Product: ITE Device(8386)
[    5.076205] usb 1-8: Manufacturer: ITE Tech. Inc.
[    5.600646] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
[    5.611657] [drm:wait_panel_status] Wait complete
[    5.611662] [drm:wait_panel_on] Wait for panel power on
[    5.611666] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
[    5.820757] [drm:wait_panel_status] Wait complete
[    5.820766] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[    5.820774] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
[    5.821858] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[    5.822484] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
[    5.823083] [drm:intel_dp_start_link_train] clock recovery OK
[    5.823990] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
[    5.824888] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
[    5.825123] [drm:intel_edp_backlight_on] 
[    5.825124] [drm:intel_panel_enable_backlight] pipe A
[    5.825129] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
[    5.825283] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
[    5.826757] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
[    5.826765] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[    5.841817] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable planes flush fb bits
[    5.841827] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
[    5.841830] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
[    5.841832] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
[    5.841834] [drm:check_crtc_state] [CRTC:20]
[    5.841842] [drm:check_crtc_state] [CRTC:24]
[    5.841843] [drm:check_crtc_state] [CRTC:28]
[    5.841845] [drm:check_shared_dpll_state] WRPLL 1
[    5.841846] [drm:check_shared_dpll_state] WRPLL 2
[    5.841876] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
[    5.841879] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
[    5.841881] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.841883] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.841885] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
[    5.841886] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
[    5.841887] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.841889] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.841892] [drm:drm_fb_helper_hotplug_event] 
[    5.841894] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[    5.841896] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[    5.842236] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[    5.842555] [drm:intel_dp_probe_oui] Branch OUI: 000000
[    5.842569] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[    5.842573] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[    5.842577] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.842579] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[    5.842581] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[    5.842582] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[    5.842806] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[    5.842808] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[    5.842811] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[    5.842815] [drm:drm_setup_crtcs] 
[    5.842817] [drm:drm_enable_connectors] connector 31 enabled? yes
[    5.842818] [drm:drm_enable_connectors] connector 40 enabled? no
[    5.842820] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1
[    5.842821] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0
[    5.842823] [drm:intel_fb_initial_config] connector eDP-1 on pipe A [CRTC:20]: 3200x1800
[    5.842824] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
[    5.842826] [drm:drm_setup_crtcs] desired mode 3200x1800 set on crtc 20 (0,0)
[    5.842853] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[    5.842879] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[    5.842881] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[    5.842883] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.842885] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    5.842887] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    5.842891] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    5.842897] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    5.842898] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    5.842900] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    5.842901] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    5.842902] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    5.842903] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    5.842905] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    5.842907] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    5.842908] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    5.842909] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    5.842910] [drm:intel_dump_pipe_config] requested mode:
[    5.842913] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.842913] [drm:intel_dump_pipe_config] adjusted mode:
[    5.842916] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.842918] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    5.842919] [drm:intel_dump_pipe_config] port clock: 540000
[    5.842920] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    5.842921] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    5.842922] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    5.842923] [drm:intel_dump_pipe_config] ips: 0
[    5.842924] [drm:intel_dump_pipe_config] double wide: 0
[    5.842925] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
[    5.842927] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
[    5.842929] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.842930] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.842931] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
[    5.842933] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
[    5.842934] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.842935] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.842944] Console: switching to colour frame buffer device 400x112
[    5.842951] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[    5.842953] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[    5.842954] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.842955] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    5.842956] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    5.842958] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    5.842962] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    5.842963] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    5.842964] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    5.842965] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    5.842966] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    5.842967] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    5.842968] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    5.842970] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    5.842972] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    5.842972] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    5.842973] [drm:intel_dump_pipe_config] requested mode:
[    5.842975] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.842976] [drm:intel_dump_pipe_config] adjusted mode:
[    5.842978] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.842980] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    5.842981] [drm:intel_dump_pipe_config] port clock: 540000
[    5.842982] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    5.842983] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    5.842984] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    5.842985] [drm:intel_dump_pipe_config] ips: 0
[    5.842986] [drm:intel_dump_pipe_config] double wide: 0
[    5.854255] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[    5.854255] i915 0000:00:02.0: registered panic notifier
[    5.854499] [drm:i915_gem_open] 
[    5.854528] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[    5.854542] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[    5.854544] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[    5.854545] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.854547] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    5.854548] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    5.854550] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    5.854554] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    5.854555] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    5.854556] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    5.854557] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    5.854558] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    5.854559] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    5.854560] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    5.854562] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    5.854563] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    5.854564] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    5.854565] [drm:intel_dump_pipe_config] requested mode:
[    5.854567] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.854567] [drm:intel_dump_pipe_config] adjusted mode:
[    5.854569] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.854571] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    5.854571] [drm:intel_dump_pipe_config] port clock: 540000
[    5.854572] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    5.854573] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    5.854574] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    5.854575] [drm:intel_dump_pipe_config] ips: 0
[    5.854576] [drm:intel_dump_pipe_config] double wide: 0
[    5.854577] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
[    5.854579] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
[    5.854580] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.854581] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.854582] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
[    5.854583] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
[    5.854584] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.854585] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[    5.854595] [drm:i915_gem_open] 
[    5.854637] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[    5.854639] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[    5.854643] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[    5.854644] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[    5.854645] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[    5.854982] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[    5.855294] [drm:intel_dp_probe_oui] Branch OUI: 000000
[    5.855302] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[    5.855306] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[    5.855309] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.855312] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[    5.855317] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[    5.868809] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[    5.868813] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[    5.868815] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[    5.869019] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[    5.869022] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[    5.869023] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[    5.869027] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[    5.869029] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[    5.869029] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[    5.869219] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[    5.869220] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[    5.869222] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[    5.869240] [drm:add_framebuffer_internal] [FB:43]
[    5.889765] [drm:add_framebuffer_internal] [FB:43]
[    5.889783] [drm:drm_mode_setcrtc] [CRTC:20]
[    5.889786] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
[    5.889788] [drm:intel_crtc_set_config] [CRTC:20] [FB:43] #connectors=1 (x y) (0 0)
[    5.889790] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
[    5.889791] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.889793] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    5.889795] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    5.889798] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    5.889802] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    5.889803] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    5.889805] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    5.889806] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    5.889807] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    5.889808] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    5.889809] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    5.889811] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    5.889812] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    5.889813] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    5.889813] [drm:intel_dump_pipe_config] requested mode:
[    5.889815] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.889816] [drm:intel_dump_pipe_config] adjusted mode:
[    5.889818] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.889820] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    5.889820] [drm:intel_dump_pipe_config] port clock: 540000
[    5.889821] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    5.889822] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    5.889823] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    5.889824] [drm:intel_dump_pipe_config] ips: 0
[    5.889825] [drm:intel_dump_pipe_config] double wide: 0
[    5.903381] [drm:ironlake_update_primary_plane] Writing base 00000000 00000000 0 0 12800
[    5.915765] [drm:drm_mode_setcrtc] [CRTC:20]
[    5.915770] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
[    5.915772] [drm:intel_crtc_set_config] [CRTC:20] [FB:43] #connectors=1 (x y) (0 0)
[    5.915775] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[    5.915776] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[    5.915778] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[    5.915780] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[    5.915783] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[    5.915787] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[    5.915788] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[    5.915790] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[    5.915791] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[    5.915792] [drm:intel_dump_pipe_config] cpu_transcoder: D
[    5.915793] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[    5.915794] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[    5.915796] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[    5.915797] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[    5.915798] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[    5.915799] [drm:intel_dump_pipe_config] requested mode:
[    5.915801] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.915802] [drm:intel_dump_pipe_config] adjusted mode:
[    5.915804] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[    5.915806] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[    5.915806] [drm:intel_dump_pipe_config] port clock: 540000
[    5.915807] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[    5.915809] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[    5.915810] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[    5.915811] [drm:intel_dump_pipe_config] ips: 0
[    5.915812] [drm:intel_dump_pipe_config] double wide: 0
[    6.731419] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
[    8.864649] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
[    8.864663] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
[  115.582006] usb 1-1: new high-speed USB device number 5 using xhci_hcd
[  115.747745] usb 1-1: New USB device found, idVendor=05e3, idProduct=0608
[  115.747751] usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[  115.747754] usb 1-1: Product: USB2.0 Hub
[  115.748760] hub 1-1:1.0: USB hub found
[  115.749245] hub 1-1:1.0: 4 ports detected
[  116.016565] usb 1-1.1: new full-speed USB device number 6 using xhci_hcd
[  116.103763] usb 1-1.1: New USB device found, idVendor=046d, idProduct=c52f
[  116.103769] usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  116.103772] usb 1-1.1: Product: USB Receiver
[  116.103774] usb 1-1.1: Manufacturer: Logitech
[  116.106777] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C52F.0002/input/input6
[  116.106977] hid-generic 0003:046D:C52F.0002: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input0
[  116.109429] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:046D:C52F.0003/input/input7
[  116.160727] hid-generic 0003:046D:C52F.0003: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input1
[  116.234701] usb 1-1.2: new full-speed USB device number 7 using xhci_hcd
[  116.322231] usb 1-1.2: New USB device found, idVendor=046d, idProduct=c52b
[  116.322237] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  116.322240] usb 1-1.2: Product: USB Receiver
[  116.322243] usb 1-1.2: Manufacturer: Logitech
[  116.324841] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:046D:C52B.0004/input/input8
[  116.375948] hid-generic 0003:046D:C52B.0004: input,hidraw2: USB HID v1.11 Keyboard [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input0
[  116.378732] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:046D:C52B.0005/input/input9
[  116.430109] hid-generic 0003:046D:C52B.0005: input,hiddev0,hidraw3: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input1
[  116.433135] hid-generic 0003:046D:C52B.0006: hiddev0,hidraw4: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input2
[  118.955965] random: nonblocking pool is initialized
[  121.089903] usb 1-1: USB disconnect, device number 5
[  121.089907] usb 1-1.1: USB disconnect, device number 6
[  121.131784] usb 1-1.2: USB disconnect, device number 7
[  123.490859] usb 1-1: new high-speed USB device number 8 using xhci_hcd
[  123.656551] usb 1-1: New USB device found, idVendor=05e3, idProduct=0608
[  123.656556] usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[  123.656559] usb 1-1: Product: USB2.0 Hub
[  123.657603] hub 1-1:1.0: USB hub found
[  123.658074] hub 1-1:1.0: 4 ports detected
[  123.925374] usb 1-1.1: new full-speed USB device number 9 using xhci_hcd
[  124.012611] usb 1-1.1: New USB device found, idVendor=046d, idProduct=c52f
[  124.012618] usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  124.012621] usb 1-1.1: Product: USB Receiver
[  124.012623] usb 1-1.1: Manufacturer: Logitech
[  124.015894] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C52F.0007/input/input10
[  124.016183] hid-generic 0003:046D:C52F.0007: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input0
[  124.018429] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:046D:C52F.0008/input/input11
[  124.069628] hid-generic 0003:046D:C52F.0008: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input1
[  124.143547] usb 1-1.2: new full-speed USB device number 10 using xhci_hcd
[  124.230974] usb 1-1.2: New USB device found, idVendor=046d, idProduct=c52b
[  124.230979] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  124.230982] usb 1-1.2: Product: USB Receiver
[  124.230985] usb 1-1.2: Manufacturer: Logitech
[  124.233547] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:046D:C52B.0009/input/input12
[  124.284649] hid-generic 0003:046D:C52B.0009: input,hidraw2: USB HID v1.11 Keyboard [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input0
[  124.287164] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:046D:C52B.000A/input/input13
[  124.337884] hid-generic 0003:046D:C52B.000A: input,hiddev0,hidraw3: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input1
[  124.340796] hid-generic 0003:046D:C52B.000B: hiddev0,hidraw4: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input2
[  136.049149] PM: Starting manual resume from disk
[  136.049155] PM: Hibernation image partition 253:1 present
[  136.049157] PM: Looking for hibernation image.
[  136.049349] PM: Image not found (code -22)
[  136.049353] PM: Hibernation image not present or could not be loaded.
[  136.096803] EXT4-fs (dm-2): mounted filesystem with ordered data mode. Opts: (null)
[  136.313190] systemd-journald[137]: Received SIGTERM from PID 1 (systemd).
[  136.402219] audit: type=1404 audit(1425412000.925:2): enforcing=1 old_enforcing=0 auid=4294967295 ses=4294967295
[  136.433263] SELinux: 2048 avtab hash slots, 104701 rules.
[  136.446612] SELinux: 2048 avtab hash slots, 104701 rules.
[  136.468341] SELinux:  8 users, 103 roles, 4987 types, 294 bools, 1 sens, 1024 cats
[  136.468344] SELinux:  83 classes, 104701 rules
[  136.471624] SELinux:  Permission audit_read in class capability2 not defined in policy.
[  136.471629] SELinux:  Class binder not defined in policy.
[  136.471629] SELinux: the above unknown classes and permissions will be allowed
[  136.471633] SELinux:  Completing initialization.
[  136.471634] SELinux:  Setting up existing superblocks.
[  136.477356] audit: type=1403 audit(1425412001.000:3): policy loaded auid=4294967295 ses=4294967295
[  136.483195] systemd[1]: Successfully loaded SELinux policy in 84.053ms.
[  136.515380] systemd[1]: Relabelled /dev and /run in 15.046ms.
[  136.543857] systemd-sysv-generator[2321]: Could not find init script for wl.service
[  136.544823] systemd-sysv-generator[2321]: Could not find init script for wl.service
[  136.546064] systemd-sysv-generator[2321]: Could not find init script for wl.service
[  136.547274] systemd-sysv-generator[2321]: Could not find init script for wl.service
[  136.821393] EXT4-fs (dm-2): re-mounted. Opts: (null)
[  136.835910] systemd-journald[2343]: Received request to flush runtime journal from PID 1
[  137.306667] ACPI Warning: SystemIO range 0x0000000000003040-0x000000000000305f conflicts with OpRegion 0x0000000000003040-0x000000000000304f (\_SB_.PCI0.SBUS.SMBI) (20150204/utaddress-258)
[  137.306675] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[  137.334351] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[  137.368092] ACPI Error: [\_SB_.PCI0.LPCB.H_EC.PMAX] Namespace lookup failure, AE_NOT_FOUND (20150204/psargs-359)
[  137.368101] ACPI Error: Method parse/execution failed [\_SB_.PCI0.B0D4._TMP] (Node ffff8802560e8370), AE_NOT_FOUND (20150204/psparse-536)
[  137.398527] dw_dmac INTL9C60:00: DesignWare DMA Controller, 8 channels
[  137.412694] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=46/937
[  137.412700] [drm:intel_panel_actually_set_backlight] set backlight PWM = 46
[  137.453248] wmi: Mapper loaded
[  137.558053] input: Ideapad extra buttons as /devices/pci0000:00/0000:00:1f.0/PNP0C09:00/VPC2004:00/input/input14
[  137.568494] media: Linux media interface: v0.10
[  137.644668] hid-rmi 0018:06CB:2714.000C: Scanning PDT...
[  137.646127] Linux video capture interface: v2.00
[  137.649064] hid-rmi 0018:06CB:2714.000C: Found F34 on page 0x00
[  137.652266] hid-rmi 0018:06CB:2714.000C: Found F01 on page 0x00
[  137.665656] iTCO_vendor_support: vendor-support=0
[  137.682127] input: ATML1000:00 03EB:8A0F as /devices/pci0000:00/INT3433:00/i2c-8/i2c-ATML1000:00/0018:03EB:8A0F.000D/input/input16
[  137.682341] hid-multitouch 0018:03EB:8A0F.000D: input,hidraw5: <UNKNOWN> HID v1.00 Device [ATML1000:00 03EB:8A0F] on 
[  137.688076] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[  137.688117] iTCO_wdt: Found a Wildcat Point_LP TCO device (Version=2, TCOBASE=0x1860)
[  137.689903] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[  137.715964] hid-rmi 0018:06CB:2714.000C: Found F11 on page 0x00
[  137.717316] Bluetooth: Core ver 2.20
[  137.717330] NET: Registered protocol family 31
[  137.717331] Bluetooth: HCI device and connection manager initialized
[  137.717334] Bluetooth: HCI socket layer initialized
[  137.717337] Bluetooth: L2CAP socket layer initialized
[  137.717345] Bluetooth: SCO socket layer initialized
[  137.722807] hid-rmi 0018:06CB:2714.000C: Found F54 on page 0x01
[  137.729080] hid-rmi 0018:06CB:2714.000C: Found F55 on page 0x02
[  137.760415] hid-rmi 0018:06CB:2714.000C: Found F30 on page 0x03
[  137.770631] usbcore: registered new interface driver btusb
[  137.774922] hid-rmi 0018:06CB:2714.000C: rmi_scan_pdt: Done with PDT scan.
[  137.779882] bluetooth hci0: Direct firmware load for brcm/BCM20702A0-0489-e07a.hcd failed with error -2
[  137.779887] Bluetooth: hci0: BCM: patch brcm/BCM20702A0-0489-e07a.hcd not found
[  137.805265] hid-rmi 0018:06CB:2714.000C: rmi_populate_f11: size in mm: 87 x 57
[  137.826582] input: SYNA2B22:00 06CB:2714 as /devices/pci0000:00/INT3432:00/i2c-7/i2c-SYNA2B22:00/0018:06CB:2714.000C/input/input15
[  137.832422] hid-rmi 0018:06CB:2714.000C: input,hidraw6: <UNKNOWN> HID v1.00 Mouse [SYNA2B22:00 06CB:2714] on 
[  137.833824] uvcvideo: Found UVC 1.00 device Lenovo EasyCamera (5986:0535)
[  137.837212] snd_hda_intel 0000:00:03.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
[  137.842323] input: Lenovo EasyCamera as /devices/pci0000:00/0000:00:14.0/usb1/1-7/1-7:1.0/input/input18
[  137.842648] usbcore: registered new interface driver uvcvideo
[  137.842651] USB Video Class driver (1.1.1)
[  137.864545] [drm:intel_display_power_get] enabling display
[  137.864550] [drm:hsw_set_power_well] Enabling power well
[  137.864934] Adding 8126460k swap on /dev/mapper/fedora-swap.  Priority:-1 extents:1 across:8126460k SSFS
[  137.867872] sound hdaudioC1D0: autoconfig for ALC286: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
[  137.867875] sound hdaudioC1D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[  137.867877] sound hdaudioC1D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
[  137.867878] sound hdaudioC1D0:    mono: mono_out=0x0
[  137.867879] sound hdaudioC1D0:    inputs:
[  137.867880] sound hdaudioC1D0:      Mic=0x18
[  137.867882] sound hdaudioC1D0:      Internal Mic=0x12
[  137.873853] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input19
[  137.873936] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input20
[  137.884732] input: HDA Intel HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input21
[  137.884838] input: HDA Intel HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/sound/card0/input22
[  137.884907] input: HDA Intel HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/sound/card0/input23
[  137.981311] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[  138.068391] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[  138.585942] audit: type=1305 audit(1425412003.107:4): audit_pid=2513 old=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:auditd_t:s0 res=1
[  138.892673] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[  138.892675] Bluetooth: BNEP filters: protocol multicast
[  138.892679] Bluetooth: BNEP socket layer initialized
[  139.960952] nf_conntrack version 0.5.0 (65536 buckets, 262144 max)
[  140.012795] ip6_tables: (C) 2000-2006 Netfilter Core Team
[  140.077293] Ebtables v2.0 registered
[  140.144169] bridge: automatic filtering via arp/ip/ip6tables has been deprecated. Update your scripts to load br_netfilter if you need this.
[  141.040977] cfg80211: Calling CRDA to update world regulatory domain
[  141.077106] cfg80211: World regulatory domain updated:
[  141.077110] cfg80211:  DFS Master region: unset
[  141.077111] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time)
[  141.077114] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[  141.077116] cfg80211:   (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[  141.077118] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A)
[  141.077120] cfg80211:   (5170000 KHz - 5250000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2000 mBm), (N/A)
[  141.077123] cfg80211:   (5250000 KHz - 5330000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2000 mBm), (0 s)
[  141.077124] cfg80211:   (5490000 KHz - 5730000 KHz @ 160000 KHz), (N/A, 2000 mBm), (0 s)
[  141.077126] cfg80211:   (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[  141.077128] cfg80211:   (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A)
[  141.089545] wl: module license 'unspecified' taints kernel.
[  141.089548] Disabling lock debugging due to kernel taint
[  141.091869] wl: module verification failed: signature and/or required key missing - tainting kernel
[  141.110881] eth0: Broadcom BCM43b1 802.11 Hybrid Wireless Controller 6.30.223.248 (r487574)
[  141.119248] wl 0000:01:00.0 wlp1s0: renamed from eth0
[  143.682861] ax88179_178a 2-2:1.0 enp0s20u2: ax88179 - Link status is: 1
[  149.219736] [drm:i915_gem_open] 
[  149.226854] [drm:i915_gem_open] 
[  149.226903] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.228616] [drm:i915_gem_open] 
[  149.228635] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.228639] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.229795] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.229813] [drm:add_framebuffer_internal] [FB:45]
[  149.230085] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.230089] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
[  149.230192] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  149.230202] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  149.230383] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  149.230389] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  149.292477] [drm:add_framebuffer_internal] [FB:45]
[  149.293567] [drm:drm_mode_setcrtc] [CRTC:20]
[  149.293573] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
[  149.293577] [drm:intel_crtc_set_config] [CRTC:20] [FB:45] #connectors=1 (x y) (0 0)
[  149.293580] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
[  149.293583] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  149.293586] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  149.293589] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  149.293592] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  149.293598] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  149.293600] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  149.293602] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  149.293605] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  149.293606] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  149.293608] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  149.293610] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  149.293613] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  149.293615] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  149.293616] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  149.293618] [drm:intel_dump_pipe_config] requested mode:
[  149.293621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x0 0xa
[  149.293622] [drm:intel_dump_pipe_config] adjusted mode:
[  149.293626] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  149.293629] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  149.293630] [drm:intel_dump_pipe_config] port clock: 540000
[  149.293632] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  149.293634] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  149.293635] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  149.293637] [drm:intel_dump_pipe_config] ips: 0
[  149.293638] [drm:intel_dump_pipe_config] double wide: 0
[  149.301207] [drm:ironlake_update_primary_plane] Writing base 02C8A000 00000000 0 0 12800
[  149.313709] [drm:drm_mode_setcrtc] [CRTC:24]
[  149.313714] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
[  149.313717] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
[  149.313719] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  149.313722] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[  149.313727] [drm:drm_mode_setcrtc] [CRTC:28]
[  149.313729] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
[  149.313731] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
[  149.313733] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  149.313734] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[  149.724716] usb 1-1: USB disconnect, device number 8
[  149.724743] usb 1-1.1: USB disconnect, device number 9
[  149.762849] usb 1-1.2: USB disconnect, device number 10
[  150.156927] [drm:i915_gem_open] 
[  150.178143] [drm:i915_gem_context_create_ioctl] HW context 1 created
[  150.180601] [drm:i915_gem_context_create_ioctl] HW context 2 created
[  150.181030] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
[  150.181772] [drm:i915_gem_context_create_ioctl] HW context 1 created
[  150.182051] [drm:i915_gem_context_destroy_ioctl] HW context 2 destroyed
[  150.182769] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
[  150.324751] [drm:add_framebuffer_internal] [FB:43]
[  151.194101] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.194105] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[  151.194107] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[  151.194113] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[  151.194119] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
[  151.204931] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[  151.205235] [drm:intel_dp_probe_oui] Branch OUI: 000000
[  151.205246] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[  151.205248] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[  151.205251] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  151.205252] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[  151.205261] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.205408] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  151.205410] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[  151.205411] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[  151.205567] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  151.205568] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[  151.205570] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[  151.210149] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.210153] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[  151.210155] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[  151.210470] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[  151.210776] [drm:intel_dp_probe_oui] Branch OUI: 000000
[  151.210784] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[  151.210787] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[  151.210789] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  151.210791] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[  151.210795] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.210871] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  151.210873] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[  151.210874] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[  151.211037] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  151.211040] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[  151.211042] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[  151.485886] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.485892] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[  151.485894] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[  151.497713] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[  151.498069] [drm:intel_dp_probe_oui] Branch OUI: 000000
[  151.498082] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[  151.498086] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[  151.498090] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  151.498093] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[  151.498107] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  151.498215] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  151.498217] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[  151.498219] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[  151.498380] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  151.498383] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[  151.498385] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[  151.680212] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=937/937
[  151.680215] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
[  152.129722] [drm:i915_gem_open] 
[  152.161756] [drm:i915_gem_context_create_ioctl] HW context 1 created
[  152.167491] [drm:i915_gem_open] 
[  152.212085] [drm:i915_gem_context_create_ioctl] HW context 1 created
[  152.219788] [drm:add_framebuffer_internal] [FB:46]
[  152.235002] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  152.235008] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
[  152.235010] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
[  152.235331] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
[  152.235642] [drm:intel_dp_probe_oui] Branch OUI: 000000
[  152.235651] [drm:drm_edid_to_eld] ELD: no CEA Extension found
[  152.235654] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
[  152.235656] [drm:drm_mode_debug_printmodeline] Modeline 32:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  152.235658] [drm:drm_mode_debug_printmodeline] Modeline 33:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
[  152.235662] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
[  152.235730] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
[  152.235731] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[  152.235733] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[  152.235893] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  152.235894] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
[  152.235896] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] disconnected
[  153.468010] usb 1-1: new high-speed USB device number 11 using xhci_hcd
[  153.633145] usb 1-1: New USB device found, idVendor=05e3, idProduct=0608
[  153.633149] usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[  153.633153] usb 1-1: Product: USB2.0 Hub
[  153.634461] hub 1-1:1.0: USB hub found
[  153.634732] hub 1-1:1.0: 4 ports detected
[  153.910468] usb 1-1.1: new full-speed USB device number 12 using xhci_hcd
[  153.996880] usb 1-1.1: New USB device found, idVendor=046d, idProduct=c52f
[  153.996884] usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  153.996887] usb 1-1.1: Product: USB Receiver
[  153.996889] usb 1-1.1: Manufacturer: Logitech
[  153.999133] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C52F.000E/input/input24
[  154.000146] hid-generic 0003:046D:C52F.000E: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input0
[  154.002202] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:046D:C52F.000F/input/input25
[  154.052915] hid-generic 0003:046D:C52F.000F: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input1
[  154.115596] usb 1-1.2: new full-speed USB device number 13 using xhci_hcd
[  154.202194] usb 1-1.2: New USB device found, idVendor=046d, idProduct=c52b
[  154.202198] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  154.202201] usb 1-1.2: Product: USB Receiver
[  154.202203] usb 1-1.2: Manufacturer: Logitech
[  154.204760] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:046D:C52B.0010/input/input26
[  154.255966] hid-generic 0003:046D:C52B.0010: input,hidraw2: USB HID v1.11 Keyboard [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input0
[  154.258110] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:046D:C52B.0011/input/input27
[  154.309382] hid-generic 0003:046D:C52B.0011: input,hiddev0,hidraw3: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input1
[  154.311771] hid-generic 0003:046D:C52B.0012: hiddev0,hidraw4: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input2
[  154.845639] [drm:add_framebuffer_internal] [FB:47]
[  155.197281] cfg80211: Calling CRDA for country: US
[  155.202942] cfg80211: Regulatory domain changed to country: US
[  155.202948] cfg80211:  DFS Master region: FCC
[  155.202950] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time)
[  155.202953] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 3000 mBm), (N/A)
[  155.202955] cfg80211:   (5170000 KHz - 5250000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 1700 mBm), (N/A)
[  155.202958] cfg80211:   (5250000 KHz - 5330000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2300 mBm), (0 s)
[  155.202960] cfg80211:   (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 3000 mBm), (N/A)
[  155.202962] cfg80211:   (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 4000 mBm), (N/A)
[  155.242095] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
[  155.242108] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
[  156.621755] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  156.621758] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
[  156.621760] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
[  156.621762] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.621764] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  156.621766] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  156.621770] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  156.621776] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  156.621777] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  156.621779] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  156.621781] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  156.621782] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  156.621783] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  156.621785] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  156.621786] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  156.621788] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  156.621789] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.621790] [drm:intel_dump_pipe_config] requested mode:
[  156.621793] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.621794] [drm:intel_dump_pipe_config] adjusted mode:
[  156.621796] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.621798] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  156.621799] [drm:intel_dump_pipe_config] port clock: 540000
[  156.621800] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  156.621801] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  156.621802] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.621803] [drm:intel_dump_pipe_config] ips: 0
[  156.621804] [drm:intel_dump_pipe_config] double wide: 0
[  156.621824] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[  156.665517] [drm:intel_fbdev_set_par] PSR FBDEV modeset
[  156.665534] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[  156.665548] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  156.665550] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[  156.665551] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.665553] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  156.665554] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  156.665556] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  156.665559] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  156.665560] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  156.665561] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  156.665561] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  156.665562] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  156.665562] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  156.665563] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  156.665564] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  156.665565] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  156.665565] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.665566] [drm:intel_dump_pipe_config] requested mode:
[  156.665567] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665568] [drm:intel_dump_pipe_config] adjusted mode:
[  156.665569] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665570] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  156.665571] [drm:intel_dump_pipe_config] port clock: 540000
[  156.665571] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  156.665572] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  156.665572] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.665573] [drm:intel_dump_pipe_config] ips: 0
[  156.665573] [drm:intel_dump_pipe_config] double wide: 0
[  156.665574] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
[  156.665575] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
[  156.665576] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.665576] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[  156.665577] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
[  156.665578] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
[  156.665578] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.665579] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
[  156.665582] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  156.665582] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[  156.665583] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.665583] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  156.665584] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  156.665585] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  156.665587] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  156.665587] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  156.665588] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  156.665588] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  156.665589] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  156.665589] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  156.665590] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  156.665591] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  156.665592] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  156.665592] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.665592] [drm:intel_dump_pipe_config] requested mode:
[  156.665593] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665594] [drm:intel_dump_pipe_config] adjusted mode:
[  156.665595] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665596] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  156.665596] [drm:intel_dump_pipe_config] port clock: 540000
[  156.665597] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  156.665597] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  156.665598] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.665598] [drm:intel_dump_pipe_config] ips: 0
[  156.665598] [drm:intel_dump_pipe_config] double wide: 0
[  156.665604] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  156.665605] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[  156.665605] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.665606] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  156.665606] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  156.665607] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  156.665609] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  156.665609] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  156.665610] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  156.665610] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  156.665611] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  156.665611] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  156.665612] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  156.665612] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  156.665613] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  156.665613] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.665614] [drm:intel_dump_pipe_config] requested mode:
[  156.665615] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665615] [drm:intel_dump_pipe_config] adjusted mode:
[  156.665616] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.665617] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  156.665618] [drm:intel_dump_pipe_config] port clock: 540000
[  156.665618] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  156.665619] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  156.665619] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.665619] [drm:intel_dump_pipe_config] ips: 0
[  156.665620] [drm:intel_dump_pipe_config] double wide: 0
[  156.676994] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  156.676997] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[  156.676999] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  156.677001] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  156.677003] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  156.677008] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  156.677013] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  156.677014] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  156.677016] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  156.677018] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  156.677018] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  156.677019] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  156.677020] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  156.677022] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  156.677023] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  156.677024] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  156.677024] [drm:intel_dump_pipe_config] requested mode:
[  156.677027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.677027] [drm:intel_dump_pipe_config] adjusted mode:
[  156.677029] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  156.677031] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  156.677031] [drm:intel_dump_pipe_config] port clock: 540000
[  156.677032] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  156.677033] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  156.677034] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  156.677034] [drm:intel_dump_pipe_config] ips: 0
[  156.677035] [drm:intel_dump_pipe_config] double wide: 0
[  157.722238] usb 1-1: USB disconnect, device number 11
[  157.722243] usb 1-1.1: USB disconnect, device number 12
[  157.769643] usb 1-1.2: USB disconnect, device number 13
[  158.122726] Bluetooth: RFCOMM TTY layer initialized
[  158.122735] Bluetooth: RFCOMM socket layer initialized
[  158.122811] Bluetooth: RFCOMM ver 1.11
[  158.217967] fuse init (API version 7.23)
[  217.790189] usb 1-1: new high-speed USB device number 14 using xhci_hcd
[  306.573885] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=469/937
[  306.573890] [drm:intel_panel_actually_set_backlight] set backlight PWM = 469
[  381.619819] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=117/937
[  381.619825] [drm:intel_panel_actually_set_backlight] set backlight PWM = 117
[  456.660275] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/937
[  456.660280] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  456.660289] [drm:intel_edp_backlight_power] panel power control backlight disable
[  759.232969] [drm:intel_fbdev_blank] PSR FBDEV blank normal
[  759.232987] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable planes flush fb bits
[  759.234949] [drm:intel_edp_backlight_off] 
[  759.436075] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
[  759.444088] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[  759.444098] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
[  759.444278] [drm:edp_panel_off] Turn eDP port A panel power off
[  759.444283] [drm:wait_panel_off] Wait for panel power off time
[  759.444288] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
[  759.499089] [drm:wait_panel_status] Wait complete
[  759.499103] [drm:intel_display_power_put] disabling always-on
[  759.499109] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
[  759.499110] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
[  759.499112] [drm:check_crtc_state] [CRTC:20]
[  759.499114] [drm:check_crtc_state] [CRTC:24]
[  759.499116] [drm:check_crtc_state] [CRTC:28]
[  759.499118] [drm:check_shared_dpll_state] WRPLL 1
[  759.499119] [drm:check_shared_dpll_state] WRPLL 2
[  895.750838] usb 1-1: new high-speed USB device number 15 using xhci_hcd
[  895.916547] usb 1-1: New USB device found, idVendor=05e3, idProduct=0608
[  895.916553] usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[  895.916556] usb 1-1: Product: USB2.0 Hub
[  895.918199] hub 1-1:1.0: USB hub found
[  895.918453] hub 1-1:1.0: 4 ports detected
[  896.185424] usb 1-1.1: new full-speed USB device number 16 using xhci_hcd
[  896.272655] usb 1-1.1: New USB device found, idVendor=046d, idProduct=c52f
[  896.272660] usb 1-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  896.272663] usb 1-1.1: Product: USB Receiver
[  896.272666] usb 1-1.1: Manufacturer: Logitech
[  896.275874] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.0/0003:046D:C52F.0013/input/input28
[  896.276647] hid-generic 0003:046D:C52F.0013: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input0
[  896.279103] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.1/1-1.1:1.1/0003:046D:C52F.0014/input/input29
[  896.331563] hid-generic 0003:046D:C52F.0014: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.1/input1
[  896.394529] usb 1-1.2: new full-speed USB device number 17 using xhci_hcd
[  896.481901] usb 1-1.2: New USB device found, idVendor=046d, idProduct=c52b
[  896.481907] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  896.481910] usb 1-1.2: Product: USB Receiver
[  896.481912] usb 1-1.2: Manufacturer: Logitech
[  896.485015] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:046D:C52B.0015/input/input30
[  896.535797] hid-generic 0003:046D:C52B.0015: input,hidraw2: USB HID v1.11 Keyboard [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input0
[  896.538314] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:046D:C52B.0016/input/input31
[  896.590311] hid-generic 0003:046D:C52B.0016: input,hiddev0,hidraw3: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input1
[  896.593265] hid-generic 0003:046D:C52B.0017: hiddev0,hidraw4: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:00:14.0-1.2/input2
[  897.313095] [drm:intel_fbdev_blank] PSR FBDEV unblank
[  897.313109] [drm:intel_display_power_get] enabling always-on
[  897.313112] [drm:intel_crtc_control] PSR FBDEV crtc enable planes
[  897.313139] [drm:edp_panel_on] Turn eDP port A panel power on
[  897.313142] [drm:wait_panel_power_cycle] Wait for panel power cycle
[  897.313148] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
[  897.313150] [drm:wait_panel_status] Wait complete
[  897.313155] [drm:wait_panel_on] Wait for panel power on
[  897.313159] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
[  897.521899] [drm:wait_panel_status] Wait complete
[  897.521908] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[  897.521916] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
[  897.523007] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[  897.523625] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
[  897.524224] [drm:intel_dp_start_link_train] clock recovery OK
[  897.525131] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
[  897.526031] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
[  897.526269] [drm:intel_edp_backlight_on] 
[  897.526270] [drm:intel_panel_enable_backlight] pipe A
[  897.526275] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
[  897.526431] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
[  897.527818] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
[  897.527824] [drm:ironlake_update_primary_plane] Writing base 01691000 00000000 0 0 12800
[  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable planes flush fb bits
[  897.542930] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
[  897.542932] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
[  897.542934] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
[  897.542936] [drm:check_crtc_state] [CRTC:20]
[  897.542945] [drm:check_crtc_state] [CRTC:24]
[  897.542947] [drm:check_crtc_state] [CRTC:28]
[  897.542949] [drm:check_shared_dpll_state] WRPLL 1
[  897.542950] [drm:check_shared_dpll_state] WRPLL 2
[  897.542954] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
[  897.542956] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
[  897.542957] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
[  897.542958] [drm:check_crtc_state] [CRTC:20]
[  897.542965] [drm:check_crtc_state] [CRTC:24]
[  897.542967] [drm:check_crtc_state] [CRTC:28]
[  897.542968] [drm:check_shared_dpll_state] WRPLL 1
[  897.542969] [drm:check_shared_dpll_state] WRPLL 2
[  897.542976] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=937/937
[  897.542977] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
[  897.542990] [drm:intel_crtc_set_config] [CRTC:20] [FB:44] #connectors=1 (x y) (0 0)
[  897.542994] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
[  897.542995] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
[  897.542998] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  897.543000] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
[  897.543003] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
[  897.543009] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
[  897.543010] [drm:intel_dp_compute_config] DP link bw required 867144 available 1728000
[  897.543012] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
[  897.543013] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
[  897.543014] [drm:intel_dump_pipe_config] cpu_transcoder: D
[  897.543015] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  897.543016] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  897.543018] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4209566, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
[  897.543020] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  897.543021] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[  897.543021] [drm:intel_dump_pipe_config] requested mode:
[  897.543024] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  897.543025] [drm:intel_dump_pipe_config] adjusted mode:
[  897.543027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
[  897.543030] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
[  897.543030] [drm:intel_dump_pipe_config] port clock: 540000
[  897.543031] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
[  897.543033] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  897.543034] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  897.543035] [drm:intel_dump_pipe_config] ips: 0
[  897.543035] [drm:intel_dump_pipe_config] double wide: 0
[  898.907266] usb 1-1: USB disconnect, device number 15
[  898.907271] usb 1-1.1: USB disconnect, device number 16
[  898.941848] usb 1-1.2: USB disconnect, device number 17
[  900.534735] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
[  900.534745] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
[  903.295547] nf_conntrack: automatic helper assignment is deprecated and it will be removed soon. Use the iptables CT target to attach helpers instead.

[-- Attachment #3: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Daniel Vetter]

On Tue, Mar 03, 2015 at 08:03:13PM +0000, Vivi, Rodrigo wrote:
> On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
> > On Mon, Mar 02, 2015 at 06:35:26PM +0000, Vivi, Rodrigo wrote:
> > > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> > > > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > > > > There are some cases like suspend/resume or dpms off/on sequences
> > > > > that can flush frontbuffer bits. In these cases features that relies
> > > > > on frontbuffer tracking can start working and user can stop getting
> > > > > screen updates on fbcon having impression the system is frozen.
> > > > > 
> > > > > So, let's make sure on fbcon write operation we also invalidate
> > > > > frontbuffer bits so we will be on the safest side with fbcon.
> > > > 
> > > > This is just a bandaid since you can always just directly access the
> > > > fbdev framebuffer. We really need to figure out why we have frontbuffer
> > > > bit flushes after we've invalidated them for fbcon and catch them all.
> > > 
> > > yeah, an ugly bandaid... Just to make PSR a bit more reliable without
> > > breaking fbcon environment when it gets enabled by default.
> > > 
> > > The issue is that on the logs I see:
> > > 
> > > 1.fbdev_blank dpms off
> > > 2. disable planes
> > > 3. flush frontbuffer bits
> > > --- blank stage ---
> > > 4. fbdev_blank dpms on
> > 
> > so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
> > Can you please attach full backtraces for steps 5&6?
> 
> [  156.665517] [drm:intel_fbdev_set_par] PSR FBDEV modeset
> [  759.232969] [drm:intel_fbdev_blank] PSR FBDEV blank normal
> [  759.232987] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable
> planes flush fb bits
> [  897.313095] [drm:intel_fbdev_blank] PSR FBDEV unblank
> [  897.313112] [drm:intel_crtc_control] PSR FBDEV crtc enable planes
> [  897.527818] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
> [  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable
> planes flush fb bits

I didn't mean the drm.debug log but the full backtrace for every time we
flush psr fb bits. I want to know who's the top-level function which
eventualy leads to the fb flush. I.e. something like

	WARN_ON(frontbuffer_bits);

in intel_psr_flush (after we've filtered out any already set bits and
other stuff that doesn't apply ofc).

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Rodrigo Vivi]

On Wed, Mar 4, 2015 at 6:30 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Mar 03, 2015 at 08:03:13PM +0000, Vivi, Rodrigo wrote:
>> On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
>> > On Mon, Mar 02, 2015 at 06:35:26PM +0000, Vivi, Rodrigo wrote:
>> > > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
>> > > > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
>> > > > > There are some cases like suspend/resume or dpms off/on sequences
>> > > > > that can flush frontbuffer bits. In these cases features that relies
>> > > > > on frontbuffer tracking can start working and user can stop getting
>> > > > > screen updates on fbcon having impression the system is frozen.
>> > > > >
>> > > > > So, let's make sure on fbcon write operation we also invalidate
>> > > > > frontbuffer bits so we will be on the safest side with fbcon.
>> > > >
>> > > > This is just a bandaid since you can always just directly access the
>> > > > fbdev framebuffer. We really need to figure out why we have frontbuffer
>> > > > bit flushes after we've invalidated them for fbcon and catch them all.
>> > >
>> > > yeah, an ugly bandaid... Just to make PSR a bit more reliable without
>> > > breaking fbcon environment when it gets enabled by default.
>> > >
>> > > The issue is that on the logs I see:
>> > >
>> > > 1.fbdev_blank dpms off
>> > > 2. disable planes
>> > > 3. flush frontbuffer bits
>> > > --- blank stage ---
>> > > 4. fbdev_blank dpms on
>> >
>> > so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
>> > Can you please attach full backtraces for steps 5&6?
>>
>> [  156.665517] [drm:intel_fbdev_set_par] PSR FBDEV modeset
>> [  759.232969] [drm:intel_fbdev_blank] PSR FBDEV blank normal
>> [  759.232987] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable
>> planes flush fb bits
>> [  897.313095] [drm:intel_fbdev_blank] PSR FBDEV unblank
>> [  897.313112] [drm:intel_crtc_control] PSR FBDEV crtc enable planes
>> [  897.527818] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
>> [  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable
>> planes flush fb bits
>
> I didn't mean the drm.debug log but the full backtrace for every time we
> flush psr fb bits. I want to know who's the top-level function which
> eventualy leads to the fb flush. I.e. something like
>
>         WARN_ON(frontbuffer_bits);
>
> in intel_psr_flush (after we've filtered out any already set bits and
> other stuff that doesn't apply ofc).

I'm not sure if I understood your request...
This [  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc
enable planes flush fb bits
is the point where frontbuffer bits will be flushed calling psr_flush
and psr gets back to life after the fbdev unblank.


>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 4/7] drm/i915: PSR VLV: Add single frame update.

[Pandiyan, Dhinakaran]

Reviewed by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Tested by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

The screen update lag that was earlier seen on BSW is fixed by this patch.
________________________________________
From: Vivi, Rodrigo
Sent: Friday, February 27, 2015 5:26 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; Pandiyan, Dhinakaran
Subject: [PATCH 4/7] drm/i915: PSR VLV: Add single frame update.

According to spec: "In PSR HW or SW mode, SW set this bit before writing
registers for a flip. It will be self-clear when it gets to the PSR
active state."

Some versions of spec mention that this is needed when in
"Persistent mode" but define it as same as "SW mode". Since this
fix the page flip case let's assume this is exactly what we need.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_frontbuffer.c |  2 ++
 drivers/gpu/drm/i915/intel_psr.c         | 42 ++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1fb1529..55ece8f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1182,6 +1182,7 @@ void intel_psr_invalidate(struct drm_device *dev,
 void intel_psr_flush(struct drm_device *dev,
                         unsigned frontbuffer_bits);
 void intel_psr_init(struct drm_device *dev);
+void intel_psr_single_frame_update(struct drm_device *dev);

 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 73cb6e0..2094c06 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -254,6 +254,8 @@ void intel_frontbuffer_flip_prepare(struct drm_device *dev,
        /* Remove stale busy bits due to the old buffer. */
        dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
        mutex_unlock(&dev_priv->fb_tracking.lock);
+
+       intel_psr_single_frame_update(dev);
 }

 /**
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d2ff87d..c1ca923 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -553,6 +553,48 @@ static void intel_psr_exit(struct drm_device *dev)
 }

 /**
+ * intel_psr_single_frame_update - Single Frame Update
+ * @dev: DRM device
+ *
+ * Some platforms support a single frame update feature that is used to
+ * send and update only one frame on Remote Frame Buffer.
+ * So far it is only implemented for Valleyview and Cherryview because
+ * hardware requires this to be done before a page flip.
+ */
+void intel_psr_single_frame_update(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_crtc *crtc;
+       enum pipe pipe;
+       u32 val;
+
+       /*
+        * Single frame update is already supported on BDW+ but it requires
+        * many W/A and it isn't really needed.
+        */
+       if (!IS_VALLEYVIEW(dev))
+               return;
+
+       mutex_lock(&dev_priv->psr.lock);
+       if (!dev_priv->psr.enabled) {
+               mutex_unlock(&dev_priv->psr.lock);
+               return;
+       }
+
+       crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
+       pipe = to_intel_crtc(crtc)->pipe;
+       val = I915_READ(VLV_PSRCTL(pipe));
+
+       /*
+        * We need to set this bit before writing registers for a flip.
+        * This bit will be self-clear when it gets to the PSR active state.
+        */
+       I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
+
+       mutex_unlock(&dev_priv->psr.lock);
+}
+
+/**
  * intel_psr_invalidate - Invalidade PSR
  * @dev: DRM device
  * @frontbuffer_bits: frontbuffer plane tracking bits
--
1.9.3

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Re: [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Daniel Vetter]

On Wed, Mar 04, 2015 at 03:05:11PM -0800, Rodrigo Vivi wrote:
> On Wed, Mar 4, 2015 at 6:30 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Tue, Mar 03, 2015 at 08:03:13PM +0000, Vivi, Rodrigo wrote:
> >> On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
> >> > On Mon, Mar 02, 2015 at 06:35:26PM +0000, Vivi, Rodrigo wrote:
> >> > > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> >> > > > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> >> > > > > There are some cases like suspend/resume or dpms off/on sequences
> >> > > > > that can flush frontbuffer bits. In these cases features that relies
> >> > > > > on frontbuffer tracking can start working and user can stop getting
> >> > > > > screen updates on fbcon having impression the system is frozen.
> >> > > > >
> >> > > > > So, let's make sure on fbcon write operation we also invalidate
> >> > > > > frontbuffer bits so we will be on the safest side with fbcon.
> >> > > >
> >> > > > This is just a bandaid since you can always just directly access the
> >> > > > fbdev framebuffer. We really need to figure out why we have frontbuffer
> >> > > > bit flushes after we've invalidated them for fbcon and catch them all.
> >> > >
> >> > > yeah, an ugly bandaid... Just to make PSR a bit more reliable without
> >> > > breaking fbcon environment when it gets enabled by default.
> >> > >
> >> > > The issue is that on the logs I see:
> >> > >
> >> > > 1.fbdev_blank dpms off
> >> > > 2. disable planes
> >> > > 3. flush frontbuffer bits
> >> > > --- blank stage ---
> >> > > 4. fbdev_blank dpms on
> >> >
> >> > so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
> >> > Can you please attach full backtraces for steps 5&6?
> >>
> >> [  156.665517] [drm:intel_fbdev_set_par] PSR FBDEV modeset
> >> [  759.232969] [drm:intel_fbdev_blank] PSR FBDEV blank normal
> >> [  759.232987] [drm:intel_crtc_disable_planes] PSR FBDEV crtc disable
> >> planes flush fb bits
> >> [  897.313095] [drm:intel_fbdev_blank] PSR FBDEV unblank
> >> [  897.313112] [drm:intel_crtc_control] PSR FBDEV crtc enable planes
> >> [  897.527818] [drm:haswell_crtc_enable] PSR FBDEV crtc enable planes
> >> [  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc enable
> >> planes flush fb bits
> >
> > I didn't mean the drm.debug log but the full backtrace for every time we
> > flush psr fb bits. I want to know who's the top-level function which
> > eventualy leads to the fb flush. I.e. something like
> >
> >         WARN_ON(frontbuffer_bits);
> >
> > in intel_psr_flush (after we've filtered out any already set bits and
> > other stuff that doesn't apply ofc).
> 
> I'm not sure if I understood your request...
> This [  897.542925] [drm:intel_crtc_enable_planes] PSR FBDEV crtc
> enable planes flush fb bits
> is the point where frontbuffer bits will be flushed calling psr_flush
> and psr gets back to life after the fbdev unblank.

I know, but I want the stacktrace for that point in time. The easiest way
to get that is a WARN_ON. If this would be userspace you could just use
the gdb backtrace command.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[PATCH] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Rodrigo Vivi]

There are some cases like suspend/resume or dpms off/on sequences
that can flush frontbuffer bits. In these cases features that relies
on frontbuffer tracking can start working and user can stop getting
screen updates on fbcon having impression the system is frozen.

So, let's make sure we also invalidate frontbuffer on fbdev blank.

v2: Daniel was right, backtrace didn't show other path than this blank
one so let's make sure frontbuffer bits gets invalidate here instead of
on random write operations that doesn't garantee we track all frontbuffer
writes.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_fbdev.c | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 234a699..324b160 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -71,6 +71,40 @@ static int intel_fbdev_set_par(struct fb_info *info)
 	return ret;
 }
 
+static int intel_fbdev_blank(int blank, struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct intel_fbdev *ifbdev =
+		container_of(fb_helper, struct intel_fbdev, helper);
+	int ret;
+
+	ret = drm_fb_helper_blank(blank, info);
+
+	if (ret == 0) {
+		/*
+		 * FIXME: After dpms off/on sequence on fbdev frontbuffer bits
+		 * gets flushed so, let's set to gtt domain again when
+		 * restoring the panel, at least while we don't have a
+		 * propper solution.
+		  */
+		mutex_lock(&fb_helper->dev->struct_mutex);
+
+		/*
+		 * There are some cases that can flush frontbuffer bits
+		 * while we are still on console. Like when planes gets
+		 * enabled/disabled on blank/unblank. So, let's be sure
+		 * the fb obj gets invalidated when touching blank function.
+		 * It is already on gtt domain, so we just invalidate it
+		 * making sure components trusting frontbuffer tracking
+		 * still gets invalidate after blank/unblank sequence.
+		 */
+		intel_fb_obj_invalidate(ifbdev->fb->obj, NULL, ORIGIN_GTT);
+		mutex_unlock(&fb_helper->dev->struct_mutex);
+	}
+
+	return ret;
+}
+
 static struct fb_ops intelfb_ops = {
 	.owner = THIS_MODULE,
 	.fb_check_var = drm_fb_helper_check_var,
@@ -79,7 +113,7 @@ static struct fb_ops intelfb_ops = {
 	.fb_copyarea = cfb_copyarea,
 	.fb_imageblit = cfb_imageblit,
 	.fb_pan_display = drm_fb_helper_pan_display,
-	.fb_blank = drm_fb_helper_blank,
+	.fb_blank = intel_fbdev_blank,
 	.fb_setcmap = drm_fb_helper_setcmap,
 	.fb_debug_enter = drm_fb_helper_debug_enter,
 	.fb_debug_leave = drm_fb_helper_debug_leave,
-- 
2.1.0

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Re: [PATCH] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5923
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/282              282/282
ILK                                  308/308              308/308
SNB                                  307/307              307/307
IVB                                  375/375              375/375
BYT                                  294/294              294/294
HSW                                  385/385              385/385
BDW                                  315/315              315/315
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Make sure we invalidate frontbuffer on fbcon.

[Daniel Vetter]

On Mon, Mar 09, 2015 at 05:57:07PM -0700, Rodrigo Vivi wrote:
> There are some cases like suspend/resume or dpms off/on sequences
> that can flush frontbuffer bits. In these cases features that relies
> on frontbuffer tracking can start working and user can stop getting
> screen updates on fbcon having impression the system is frozen.
> 
> So, let's make sure we also invalidate frontbuffer on fbdev blank.
> 
> v2: Daniel was right, backtrace didn't show other path than this blank
> one so let's make sure frontbuffer bits gets invalidate here instead of
> on random write operations that doesn't garantee we track all frontbuffer
> writes.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_fbdev.c | 36 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index 234a699..324b160 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -71,6 +71,40 @@ static int intel_fbdev_set_par(struct fb_info *info)
>  	return ret;
>  }
>  
> +static int intel_fbdev_blank(int blank, struct fb_info *info)
> +{
> +	struct drm_fb_helper *fb_helper = info->par;
> +	struct intel_fbdev *ifbdev =
> +		container_of(fb_helper, struct intel_fbdev, helper);
> +	int ret;
> +
> +	ret = drm_fb_helper_blank(blank, info);
> +
> +	if (ret == 0) {
> +		/*
> +		 * FIXME: After dpms off/on sequence on fbdev frontbuffer bits
> +		 * gets flushed so, let's set to gtt domain again when
> +		 * restoring the panel, at least while we don't have a
> +		 * propper solution.
> +		  */

No FIXME required, this imo _is_ the right fix. But we need a FIXME about
the panic locking inversion instead.

> +		mutex_lock(&fb_helper->dev->struct_mutex);
> +
> +		/*
> +		 * There are some cases that can flush frontbuffer bits
> +		 * while we are still on console. Like when planes gets
> +		 * enabled/disabled on blank/unblank. So, let's be sure
> +		 * the fb obj gets invalidated when touching blank function.
> +		 * It is already on gtt domain, so we just invalidate it
> +		 * making sure components trusting frontbuffer tracking
> +		 * still gets invalidate after blank/unblank sequence.
> +		 */

Since this mirros fbdev_set_par and we don't have a comment there I think
this one isn't needed. The commit message explains it all well already.

Merged the patche with the code comments exchanged, thanks.
-Daniel

> +		intel_fb_obj_invalidate(ifbdev->fb->obj, NULL, ORIGIN_GTT);
> +		mutex_unlock(&fb_helper->dev->struct_mutex);
> +	}
> +
> +	return ret;
> +}
> +
>  static struct fb_ops intelfb_ops = {
>  	.owner = THIS_MODULE,
>  	.fb_check_var = drm_fb_helper_check_var,
> @@ -79,7 +113,7 @@ static struct fb_ops intelfb_ops = {
>  	.fb_copyarea = cfb_copyarea,
>  	.fb_imageblit = cfb_imageblit,
>  	.fb_pan_display = drm_fb_helper_pan_display,
> -	.fb_blank = drm_fb_helper_blank,
> +	.fb_blank = intel_fbdev_blank,
>  	.fb_setcmap = drm_fb_helper_setcmap,
>  	.fb_debug_enter = drm_fb_helper_debug_enter,
>  	.fb_debug_leave = drm_fb_helper_debug_leave,
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 6/7] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Saturday, February 28, 2015 6:56 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 6/7] drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.
>
>Since active function on VLV immediately activate PSR let's give more
>time for idleness.
>
>v2: Rebase over intel_psr.c and fix typo.
>v3: Revival: Manual tests indicated that this is needed. With a short delay
>    there is a huge risk of getting blank screens when planes are being enabled.
>v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but
>    actually time for link training what we aren't doing, but with only 100 sec
>    in some cases kms_psr_sink_crc manual was showing blank screen,
>    so let's use this for now. Also changed comment by a FIXME.
>

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index c1ca923..3c1d2b3 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -648,6 +648,12 @@ void intel_psr_flush(struct drm_device *dev,
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct drm_crtc *crtc;
> 	enum pipe pipe;
>+	/* FIXME: kms_psr_sink_crc in manual mode shows black screen on
>+	 * the very first primary plane enabling. W/A is to delay
>+	 * the activate a bit more. On regular use 100 would be enough and
>+	 * better for good power savings.
>+	 */
>+	int delay = msecs_to_jiffies(HAS_DDI(dev) ? 100 : 500);
>
> 	mutex_lock(&dev_priv->psr.lock);
> 	if (!dev_priv->psr.enabled) {
>@@ -680,7 +686,7 @@ void intel_psr_flush(struct drm_device *dev,
>
> 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
> 		schedule_delayed_work(&dev_priv->psr.work,
>-				      msecs_to_jiffies(100));
>+				      msecs_to_jiffies(delay));
> 	mutex_unlock(&dev_priv->psr.lock);
> }
>
>--
>1.9.3
>
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Re: [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Saturday, February 28, 2015 6:56 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.
>
>This wrong logic and useless define came from first versions and
>came along with all rework. Just now I notice how ugly, wrong and
>useless this is.
>
>val is already defined as 0 anyway and logic is completelly wrong
>and useless. So let's starting the link_standby fix with this
>cleaning.
>

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h  | 1 -
> drivers/gpu/drm/i915/intel_psr.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 55143cb..b95554d 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2658,7 +2658,6 @@ enum skl_disp_power_wells {
> #define EDP_PSR_CTL(dev)			(EDP_PSR_BASE(dev) + 0)
> #define   EDP_PSR_ENABLE			(1<<31)
> #define   BDW_PSR_SINGLE_FRAME			(1<<30)
>-#define   EDP_PSR_LINK_DISABLE			(0<<27)
> #define   EDP_PSR_LINK_STANDBY			(1<<27)
> #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3<<25)
> #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0<<25)
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index b9f40c2..2e6831d 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -247,8 +247,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 		val |= EDP_PSR_TP1_TIME_0us;
> 		val |= EDP_PSR_SKIP_AUX_EXIT;
>-	} else
>-		val |= EDP_PSR_LINK_DISABLE;
>+	}
>
> 	I915_WRITE(EDP_PSR_CTL(dev), val |
> 		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
>--
>1.9.3
>
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Re: [PATCH 2/7] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Saturday, February 28, 2015 6:56 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Runyan, Arthur J; Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 2/7] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic
>
>Since the begining there is a missunderstanding on the meaning of this
>dpcd bit.
>This bit should'n indicate wheter to use link standby or not, but just

Shouldn't , whether

>be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
>since HW is the responsible one.
>
>Even with help of frontbuffer tracking to do exit HW tracking is still
>fully responsible for this exit logic with DP training or not.

I think it will be better to rephrase this as something like below:
"Even with help of frontbuffer tracking, HW is still fully responsible for
PSR exit logic with/without DP training"

>
>Cc: Arthur Runyan <arthur.j.runyan@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 2e6831d..6c8e9e0 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -242,8 +242,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 	uint32_t val = 0x0;
> 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
>-	if (dev_priv->psr.link_standby) {
>+	if (dev_priv->psr.link_standby)
> 		val |= EDP_PSR_LINK_STANDBY;
>+
>+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {

Shouldn't this 'if' check also include if (psr.link_standby) ?
Otherwise, even for link_disable cases we are configuring to 'skip
TPs'. Will this work ?

I see that in the next patch, you are removing this whole link_standby
thing. So, would leave it up to you to either add this check or not.

Thanks,
Durga

> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 		val |= EDP_PSR_TP1_TIME_0us;
> 		val |= EDP_PSR_SKIP_AUX_EXIT;
>@@ -354,8 +356,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> 	/* First we check VBT, but we must respect sink and source
> 	 * known restrictions */
> 	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>-	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
>-	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
>+	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
> 		dev_priv->psr.link_standby = true;
>
> 	dev_priv->psr.busy_frontbuffer_bits = 0;
>--
>1.9.3
>
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Re: [PATCH 3/7] drm/i915: PSR: deprecate link_standby support for core platforms.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Saturday, February 28, 2015 6:56 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 3/7] drm/i915: PSR: deprecate link_standby support for core platforms.
>
>On Haswell and Broadwell with link in standby when exit event happens
>between vblank and VSC packet, PSR exit on panel but DPA transmitter
>still sends black pixel. hen this condition hits, panel will intermittently

s/hen/when

>display black frame.
>
>The known W/A for this case involve the of single_frame update
>that isn't supported on Haswell and to be supported on Broadwell
>3 other workarounds would be required. So it is better and safe to
>just deprecate link_standby for now.
>
>Also, link fully off saves more power than link_standby and afwk
>no OEM is requesting link standby on VBT. There is no reason for that.
>
>For Skylake let's just consider it behaves like Broadwell until
>we prove otherwise.
>

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>Reference: HSD: bdwgfx/1912559
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
> drivers/gpu/drm/i915/i915_drv.h     |  1 -
> drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
> 3 files changed, 8 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>index 94b3984..756bf4e 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
> 		}
> 	seq_puts(m, "\n");
>
>-	seq_printf(m, "Link standby: %s\n",
>-		   yesno((bool)dev_priv->psr.link_standby));
>-
> 	/* CHV PSR has no kind of performance counter */
> 	if (HAS_PSR(dev) && HAS_DDI(dev)) {
> 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index a1dd8bc..dfd044f 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -863,7 +863,6 @@ struct i915_psr {
> 	bool active;
> 	struct delayed_work work;
> 	unsigned busy_frontbuffer_bits;
>-	bool link_standby;
> };
>
> enum intel_pch {
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 6c8e9e0..d2ff87d 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>
> 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>
>-	/* Enable PSR in sink */
>-	if (dev_priv->psr.link_standby)
>-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>-	else
>-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
>-
> 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> 				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
>@@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> 		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
> 	}
>+
>+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
> }
>
> static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>@@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 	uint32_t val = 0x0;
> 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
>-	if (dev_priv->psr.link_standby)
>-		val |= EDP_PSR_LINK_STANDBY;
>-
> 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
> 		val |= EDP_PSR_TP1_TIME_0us;
>@@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> 		return false;
> 	}
>
>+	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
>+				    (dig_port->port != PORT_A))){
>+		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not
>supported on this platform\n");
>+		return false;
>+	}
>+
> 	dev_priv->psr.source_ok = true;
> 	return true;
> }
>@@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> 	if (!intel_psr_match_conditions(intel_dp))
> 		goto unlock;
>
>-	/* First we check VBT, but we must respect sink and source
>-	 * known restrictions */
>-	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>-	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
>-		dev_priv->psr.link_standby = true;
>-
> 	dev_priv->psr.busy_frontbuffer_bits = 0;
>
> 	if (HAS_DDI(dev)) {
>--
>1.9.3
>
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>Sent: Saturday, February 28, 2015 6:56 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Enable PSR by default.
>
>With a reliable frontbuffer tracking and all instability corner cases solved
>let's re-enabled PSR by default on all supported platforms.
>

Finally ;)

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_params.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>index 44f2262..2c1a90e 100644
>--- a/drivers/gpu/drm/i915/i915_params.c
>+++ b/drivers/gpu/drm/i915/i915_params.c
>@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
> 	.enable_execlists = -1,
> 	.enable_hangcheck = true,
> 	.enable_ppgtt = -1,
>-	.enable_psr = 0,
>+	.enable_psr = 1,
> 	.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
> 	.disable_power_well = 1,
> 	.enable_ips = 1,
>@@ -127,7 +127,7 @@ MODULE_PARM_DESC(enable_execlists,
> 	"(-1=auto [default], 0=disabled, 1=enabled)");
>
> module_param_named(enable_psr, i915.enable_psr, int, 0600);
>-MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
>+MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
>
> module_param_named(preliminary_hw_support, i915.preliminary_hw_support, int, 0600);
> MODULE_PARM_DESC(preliminary_hw_support,
>--
>1.9.3
>
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[PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[Rodrigo Vivi]

Since the begining there is a missunderstanding on the meaning of this
dpcd bit.
This bit shouldn't indicate whether to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.

Even with help of frontbuffer tracking, HW is still fully responsible for
PSR exit logic with/without DP training.

v2: Fix and improve commit message (Durga).

Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e6831d..6c8e9e0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -242,8 +242,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby) {
+	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
+
+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
 		val |= EDP_PSR_SKIP_AUX_EXIT;
@@ -354,8 +356,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	/* First we check VBT, but we must respect sink and source
 	 * known restrictions */
 	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
-	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
+	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
 		dev_priv->psr.link_standby = true;
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
-- 
2.1.0

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[PATCH] drm/i915: PSR: deprecate link_standby support for core platforms.

[Rodrigo Vivi]

On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. When this condition hits, panel will intermittently
display black frame.

The known W/A for this case involve the of single_frame update
that isn't supported on Haswell and to be supported on Broadwell
3 other workarounds would be required. So it is better and safe to
just deprecate link_standby for now.

Also, link fully off saves more power than link_standby and afwk
no OEM is requesting link standby on VBT. There is no reason for that.

For Skylake let's just consider it behaves like Broadwell until
we prove otherwise.

Reference: HSD: bdwgfx/1912559
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
 drivers/gpu/drm/i915/i915_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a52d6a..1f7ec06 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		}
 	seq_puts(m, "\n");
 
-	seq_printf(m, "Link standby: %s\n",
-		   yesno((bool)dev_priv->psr.link_standby));
-
 	/* CHV PSR has no kind of performance counter */
 	if (HAS_DDI(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a80b15f..4a9ac62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -875,7 +875,6 @@ struct i915_psr {
 	bool active;
 	struct delayed_work work;
 	unsigned busy_frontbuffer_bits;
-	bool link_standby;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6c8e9e0..d2ff87d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
-	/* Enable PSR in sink */
-	if (dev_priv->psr.link_standby)
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-	else
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
-
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
 				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
@@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 	}
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby)
-		val |= EDP_PSR_LINK_STANDBY;
-
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
@@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
+	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
+				    (dig_port->port != PORT_A))){
+		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
+		return false;
+	}
+
 	dev_priv->psr.source_ok = true;
 	return true;
 }
@@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	if (!intel_psr_match_conditions(intel_dp))
 		goto unlock;
 
-	/* First we check VBT, but we must respect sink and source
-	 * known restrictions */
-	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
-		dev_priv->psr.link_standby = true;
-
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	if (HAS_DDI(dev)) {
-- 
2.1.0

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[PATCH] drm/i915: PSR: deprecate link_standby support for core platforms.

[Rodrigo Vivi]

On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. When this condition hits, panel will intermittently
display black frame.

The known W/A for this case involve the of single_frame update
that isn't supported on Haswell and to be supported on Broadwell
3 other workarounds would be required. So it is better and safe to
just deprecate link_standby for now.

Also, link fully off saves more power than link_standby and afwk
no OEM is requesting link standby on VBT. There is no reason for that.

For Skylake let's just consider it behaves like Broadwell until
we prove otherwise.

v2: Fix commit message (Durga).

Reference: HSD: bdwgfx/1912559
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  3 ---
 drivers/gpu/drm/i915/i915_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_psr.c    | 25 ++++++++-----------------
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1a52d6a..1f7ec06 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2281,9 +2281,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		}
 	seq_puts(m, "\n");
 
-	seq_printf(m, "Link standby: %s\n",
-		   yesno((bool)dev_priv->psr.link_standby));
-
 	/* CHV PSR has no kind of performance counter */
 	if (HAS_DDI(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a80b15f..4a9ac62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -875,7 +875,6 @@ struct i915_psr {
 	bool active;
 	struct delayed_work work;
 	unsigned busy_frontbuffer_bits;
-	bool link_standby;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6c8e9e0..d2ff87d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -157,14 +157,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 
 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
-	/* Enable PSR in sink */
-	if (dev_priv->psr.link_standby)
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-	else
-		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
-
 	aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
 				DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
 	aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
@@ -193,6 +185,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
 	}
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -242,9 +236,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby)
-		val |= EDP_PSR_LINK_STANDBY;
-
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 		val |= EDP_PSR_TP1_TIME_0us;
@@ -295,6 +286,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
+	if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
+				    (dig_port->port != PORT_A))){
+		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
+		return false;
+	}
+
 	dev_priv->psr.source_ok = true;
 	return true;
 }
@@ -353,12 +350,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	if (!intel_psr_match_conditions(intel_dp))
 		goto unlock;
 
-	/* First we check VBT, but we must respect sink and source
-	 * known restrictions */
-	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
-		dev_priv->psr.link_standby = true;
-
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	if (HAS_DDI(dev)) {
-- 
2.1.0

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Re: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5962
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  275/275              275/275
ILK                                  303/303              303/303
SNB                 -1              279/279              278/279
IVB                                  343/343              343/343
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_gem_persistent_relocs_forked-interruptible-thrash-inactive      PASS(3)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Rodrigo Vivi]

Hi Daniel,

Is something missing to enable it by default?

Thanks,
Rodrigo.

On Sun, Mar 15, 2015 at 10:31 PM, R, Durgadoss <durgadoss.r@intel.com> wrote:
>>-----Original Message-----
>>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>>Sent: Saturday, February 28, 2015 6:56 AM
>>To: intel-gfx@lists.freedesktop.org
>>Cc: Vivi, Rodrigo
>>Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Enable PSR by default.
>>
>>With a reliable frontbuffer tracking and all instability corner cases solved
>>let's re-enabled PSR by default on all supported platforms.
>>
>
> Finally ;)
>
> Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
>
> Thanks,
> Durga
>
>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>---
>> drivers/gpu/drm/i915/i915_params.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>>index 44f2262..2c1a90e 100644
>>--- a/drivers/gpu/drm/i915/i915_params.c
>>+++ b/drivers/gpu/drm/i915/i915_params.c
>>@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
>>       .enable_execlists = -1,
>>       .enable_hangcheck = true,
>>       .enable_ppgtt = -1,
>>-      .enable_psr = 0,
>>+      .enable_psr = 1,
>>       .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
>>       .disable_power_well = 1,
>>       .enable_ips = 1,
>>@@ -127,7 +127,7 @@ MODULE_PARM_DESC(enable_execlists,
>>       "(-1=auto [default], 0=disabled, 1=enabled)");
>>
>> module_param_named(enable_psr, i915.enable_psr, int, 0600);
>>-MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
>>+MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
>>
>> module_param_named(preliminary_hw_support, i915.preliminary_hw_support, int, 0600);
>> MODULE_PARM_DESC(preliminary_hw_support,
>>--
>>1.9.3
>>
>>_______________________________________________
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>>http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Daniel Vetter]

On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> Hi Daniel,
> 
> Is something missing to enable it by default?

Patch 1 has a small comment from me and latest version of patch 2 lacks an
r-b afaict. Hence why I didn't pull in the series yet. But it's also a
longer discussion, so ca you please resend the entire series with r-b tags
added to make sure I don't pick up the wrong versions?

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Chris Wilson]

On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > Hi Daniel,
> > 
> > Is something missing to enable it by default?
> 
> Patch 1 has a small comment from me and latest version of patch 2 lacks an
> r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> longer discussion, so ca you please resend the entire series with r-b tags
> added to make sure I don't pick up the wrong versions?

Do I yet have a method to tell when PSR is active on an output?
-Chris

-- 
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Re: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[Rodrigo Vivi]

Hi Durga, are you ok with this one?

Hi Art, do you believe there is any risk of avoiding TP when panel
tells DP_PSR_NO_TRAIN_ON_EXIT and link is disabled? I believe on the
other discussion we conluded that DP_PSR_NO_TRAIN_ON_EXIT was only
responsible for TP configurations regardless links standby or not,
right?

Thanks,
Rodrigo.

On Mon, Mar 16, 2015 at 10:35 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Since the begining there is a missunderstanding on the meaning of this
> dpcd bit.
> This bit shouldn't indicate whether to use link standby or not, but just
> be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
> since HW is the responsible one.
>
> Even with help of frontbuffer tracking, HW is still fully responsible for
> PSR exit logic with/without DP training.
>
> v2: Fix and improve commit message (Durga).
>
> Cc: Durgadoss R <durgadoss.r@intel.com>
> Cc: Arthur Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e6831d..6c8e9e0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -242,8 +242,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>         uint32_t val = 0x0;
>         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
> -       if (dev_priv->psr.link_standby) {
> +       if (dev_priv->psr.link_standby)
>                 val |= EDP_PSR_LINK_STANDBY;
> +
> +       if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>                 val |= EDP_PSR_TP2_TP3_TIME_0us;
>                 val |= EDP_PSR_TP1_TIME_0us;
>                 val |= EDP_PSR_SKIP_AUX_EXIT;
> @@ -354,8 +356,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>         /* First we check VBT, but we must respect sink and source
>          * known restrictions */
>         dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
> -       if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
> -           (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
> +       if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
>                 dev_priv->psr.link_standby = true;
>
>         dev_priv->psr.busy_frontbuffer_bits = 0;
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Vivi, Rodrigo]

On Tue, 2015-03-24 at 10:08 +0000, Chris Wilson wrote:
> On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> > On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > > Hi Daniel,
> > > 
> > > Is something missing to enable it by default?
> > 
> > Patch 1 has a small comment from me and latest version of patch 2 lacks an
> > r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> > longer discussion, so ca you please resend the entire series with r-b tags
> > added to make sure I don't pick up the wrong versions?
> 
> Do I yet have a method to tell when PSR is active on an output?

Is that pre computed pipe_config->psr_enabled enough or you mean the
immediate psr.active also exposed there on pipe_config?

> -Chris
> 

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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[chris]

On Tue, Mar 24, 2015 at 08:55:04PM +0000, Vivi, Rodrigo wrote:
> On Tue, 2015-03-24 at 10:08 +0000, Chris Wilson wrote:
> > On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> > > On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > > > Hi Daniel,
> > > > 
> > > > Is something missing to enable it by default?
> > > 
> > > Patch 1 has a small comment from me and latest version of patch 2 lacks an
> > > r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> > > longer discussion, so ca you please resend the entire series with r-b tags
> > > added to make sure I don't pick up the wrong versions?
> > 
> > Do I yet have a method to tell when PSR is active on an output?
> 
> Is that pre computed pipe_config->psr_enabled enough or you mean the
> immediate psr.active also exposed there on pipe_config?

I want a property exposed to userspace. Having a tristate that says
unsupported, disabled, active would be most useful.
-Chris

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Re: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[Runyan, Arthur J]

I think there may be a restriction that we cannot set 0us to all the training patterns.  I'll check on that. 

-----Original Message-----
From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com] 
Sent: Tuesday, March 24, 2015 8:30 AM
To: Vivi, Rodrigo
Cc: intel-gfx; Runyan, Arthur J
Subject: Re: [Intel-gfx] [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

Hi Durga, are you ok with this one?

Hi Art, do you believe there is any risk of avoiding TP when panel
tells DP_PSR_NO_TRAIN_ON_EXIT and link is disabled? I believe on the
other discussion we conluded that DP_PSR_NO_TRAIN_ON_EXIT was only
responsible for TP configurations regardless links standby or not,
right?

Thanks,
Rodrigo.

On Mon, Mar 16, 2015 at 10:35 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Since the begining there is a missunderstanding on the meaning of this
> dpcd bit.
> This bit shouldn't indicate whether to use link standby or not, but just
> be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
> since HW is the responsible one.
>
> Even with help of frontbuffer tracking, HW is still fully responsible for
> PSR exit logic with/without DP training.
>
> v2: Fix and improve commit message (Durga).
>
> Cc: Durgadoss R <durgadoss.r@intel.com>
> Cc: Arthur Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e6831d..6c8e9e0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -242,8 +242,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>         uint32_t val = 0x0;
>         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
> -       if (dev_priv->psr.link_standby) {
> +       if (dev_priv->psr.link_standby)
>                 val |= EDP_PSR_LINK_STANDBY;
> +
> +       if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>                 val |= EDP_PSR_TP2_TP3_TIME_0us;
>                 val |= EDP_PSR_TP1_TIME_0us;
>                 val |= EDP_PSR_SKIP_AUX_EXIT;
> @@ -354,8 +356,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>         /* First we check VBT, but we must respect sink and source
>          * known restrictions */
>         dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
> -       if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
> -           (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
> +       if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
>                 dev_priv->psr.link_standby = true;
>
>         dev_priv->psr.busy_frontbuffer_bits = 0;
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Daniel Vetter]

On Tue, Mar 24, 2015 at 10:05:03PM +0000, chris@chris-wilson.co.uk wrote:
> On Tue, Mar 24, 2015 at 08:55:04PM +0000, Vivi, Rodrigo wrote:
> > On Tue, 2015-03-24 at 10:08 +0000, Chris Wilson wrote:
> > > On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> > > > On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > > > > Hi Daniel,
> > > > > 
> > > > > Is something missing to enable it by default?
> > > > 
> > > > Patch 1 has a small comment from me and latest version of patch 2 lacks an
> > > > r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> > > > longer discussion, so ca you please resend the entire series with r-b tags
> > > > added to make sure I don't pick up the wrong versions?
> > > 
> > > Do I yet have a method to tell when PSR is active on an output?
> > 
> > Is that pre computed pipe_config->psr_enabled enough or you mean the
> > immediate psr.active also exposed there on pipe_config?
> 
> I want a property exposed to userspace. Having a tristate that says
> unsupported, disabled, active would be most useful.

Imo we should get the current behind-the-scenes psr support working
correctly first. Later on we can add userspace abi to expose this to
compositors, but that should be a separate step.
-Daniel
-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[Vivi, Rodrigo]

On Tue, 2015-03-24 at 22:05 +0000, chris@chris-wilson.co.uk wrote:
> On Tue, Mar 24, 2015 at 08:55:04PM +0000, Vivi, Rodrigo wrote:
> > On Tue, 2015-03-24 at 10:08 +0000, Chris Wilson wrote:
> > > On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> > > > On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > > > > Hi Daniel,
> > > > > 
> > > > > Is something missing to enable it by default?
> > > > 
> > > > Patch 1 has a small comment from me and latest version of patch 2 lacks an
> > > > r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> > > > longer discussion, so ca you please resend the entire series with r-b tags
> > > > added to make sure I don't pick up the wrong versions?
> > > 
> > > Do I yet have a method to tell when PSR is active on an output?
> > 
> > Is that pre computed pipe_config->psr_enabled enough or you mean the
> > immediate psr.active also exposed there on pipe_config?
> 
> I want a property exposed to userspace. Having a tristate that says
> unsupported, disabled, active would be most useful.

I got your patch that added that and rebased on currently intel_psr.c
changing transition and other small things and put here:

http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=intel_psr&id=b99147c4849668a04e794003746fa22708406f56

But even with PSR transitioning well from idle to active, xrandr prop
always shows me as idle:

Every 1.0s: cat /sys/kernel/debug/dri/0/i915_edp_psr_status
Wed Mar 25 12:26:13 2015

Sink_Support: yes
Source_OK: yes
Enabled: yes
Active: yes
Busy frontbuffer bits: 0x000
Re-enable work scheduled: no
HW Enabled & Active bit: yes


vivijim rdvivi-talin ~$ xrandr --prop | grep PSR
	PSR: Idle 
vivijim rdvivi-talin ~$ xrandr --prop | grep PSR
	PSR: Idle 
vivijim rdvivi-talin ~$ xrandr --prop | grep PSR
	PSR: Idle 
vivijim rdvivi-talin ~$ xrandr --prop | grep PSR
	PSR: Idle 
vivijim rdvivi-talin ~$ xrandr --prop | grep PSR
	PSR: Idle 


So, I'm not sure this is a proper way of checking this quickly
transitions as active/exit...


> -Chris
> 

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Re: [PATCH 7/7] drm/i915: Enable PSR by default.

[chris]

On Wed, Mar 25, 2015 at 07:27:35PM +0000, Vivi, Rodrigo wrote:
> On Tue, 2015-03-24 at 22:05 +0000, chris@chris-wilson.co.uk wrote:
> > On Tue, Mar 24, 2015 at 08:55:04PM +0000, Vivi, Rodrigo wrote:
> > > On Tue, 2015-03-24 at 10:08 +0000, Chris Wilson wrote:
> > > > On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
> > > > > On Mon, Mar 23, 2015 at 01:20:07PM -0700, Rodrigo Vivi wrote:
> > > > > > Hi Daniel,
> > > > > > 
> > > > > > Is something missing to enable it by default?
> > > > > 
> > > > > Patch 1 has a small comment from me and latest version of patch 2 lacks an
> > > > > r-b afaict. Hence why I didn't pull in the series yet. But it's also a
> > > > > longer discussion, so ca you please resend the entire series with r-b tags
> > > > > added to make sure I don't pick up the wrong versions?
> > > > 
> > > > Do I yet have a method to tell when PSR is active on an output?
> > > 
> > > Is that pre computed pipe_config->psr_enabled enough or you mean the
> > > immediate psr.active also exposed there on pipe_config?
> > 
> > I want a property exposed to userspace. Having a tristate that says
> > unsupported, disabled, active would be most useful.
> 
> I got your patch that added that and rebased on currently intel_psr.c
> changing transition and other small things and put here:
> 
> http://cgit.freedesktop.org/~vivijim/drm-intel/commit/?h=intel_psr&id=b99147c4849668a04e794003746fa22708406f56
> 
> But even with PSR transitioning well from idle to active, xrandr prop
> always shows me as idle:

You'll be falling foul of property caching. My immediate concern is
simply knowing when PSR is enabled on an output as a guide to knowing
when to avoid frontbuffer access. But IDLE/ACTIVE sound fun as well.
-Chris

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Re: [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[Matthew Garrett]

I've put this patchset on top of current Linus git. Switching to fbcon 
tends to result in rolling graphics, and turning the screen back on 
often gives me a static display or one that only updates every few 
seconds. This is with a Dell XPS 13 with Broadwell-U and a 3200x1800 
display.

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[PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[Rodrigo Vivi]

Since the beginning there is a missunderstanding on the meaning of this
dpcd bit.
This bit shouldn't indicate whether to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.

Even with help of frontbuffer tracking, HW is still fully responsible for
PSR exit logic with/without DP training.

DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the training, but
it doesn't tell to avoid TP patterns, so we will send minimal TP1 and avoid
TP2. It also means that sink itself can take up to 5 idle frames for training.
6 in our case since we might be off by 1. So we also increment idle_frames by 4
here.

v2: Fix and improve commit message (Durga).
v3: Use minimal TP1 time avoiding TP2 and increase idle frame.

Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db95b39..0e3b652 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -264,11 +264,17 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	uint32_t val = 0x0;
 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby) {
+	if (dev_priv->psr.link_standby)
 		val |= EDP_PSR_LINK_STANDBY;
+
+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
+		/* It doesn't mean we shouldn't send TPS patters, so let's
+		   send the minimal TP1 possible and skip TP2. */
+		val |= EDP_PSR_TP1_TIME_100us;
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
-		val |= EDP_PSR_TP1_TIME_0us;
 		val |= EDP_PSR_SKIP_AUX_EXIT;
+		/* Sink should be able to train with the 5 or 6 idle patterns */
+		idle_frames += 4;
 	}
 
 	I915_WRITE(EDP_PSR_CTL(dev), val |
@@ -381,8 +387,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	/* First we check VBT, but we must respect sink and source
 	 * known restrictions */
 	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
-	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
+	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
 		dev_priv->psr.link_standby = true;
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
-- 
2.1.0

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Re: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6179
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              276/276              274/276
ILK                                  301/301              301/301
SNB                 -1              316/316              315/316
IVB                                  328/328              328/328
BYT                                  285/285              285/285
HSW                                  394/394              394/394
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt@gen3_render_mixed_blits      FAIL(3)PASS(4)      FAIL(2)
 PNV  igt@gen3_render_tiledx_blits      FAIL(4)PASS(4)      FAIL(2)
*SNB  igt@kms_flip@dpms-vs-vblank-race      PASS(5)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:intel_dp_start_link_train[i915]]*ERROR*too_many_voltage_retries,give_up@too many voltage .* give up
drm:intel_dp_complete_link_train[i915]]*ERROR*failed_to_train_DP,aborting@failed to train .* aborting
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

[Rodrigo Vivi]

On Thu, Apr 9, 2015 at 10:42 AM, Matthew Garrett <mjg59@srcf.ucam.org> wrote:
> I've put this patchset on top of current Linus git. Switching to fbcon
> tends to result in rolling graphics, and turning the screen back on
> often gives me a static display or one that only updates every few
> seconds. This is with a Dell XPS 13 with Broadwell-U and a 3200x1800
> display.

Could you please boot this env with i915.enable_ips=0 and try to
reproduce the issue?

>
> --
> Matthew Garrett | mjg59@srcf.ucam.org
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic

[R, Durgadoss]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Friday, April 10, 2015 11:40 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo; R, Durgadoss; Runyan, Arthur J
>Subject: [PATCH] drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic
>
>Since the beginning there is a missunderstanding on the meaning of this
>dpcd bit.
>This bit shouldn't indicate whether to use link standby or not, but just
>be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
>since HW is the responsible one.
>
>Even with help of frontbuffer tracking, HW is still fully responsible for
>PSR exit logic with/without DP training.
>
>DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the training, but
>it doesn't tell to avoid TP patterns, so we will send minimal TP1 and avoid
>TP2. It also means that sink itself can take up to 5 idle frames for training.
>6 in our case since we might be off by 1. So we also increment idle_frames by 4
>here.
>
>v2: Fix and improve commit message (Durga).
>v3: Use minimal TP1 time avoiding TP2 and increase idle frame.
>
>Cc: Durgadoss R <durgadoss.r@intel.com>
>Cc: Arthur Runyan <arthur.j.runyan@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Durgadoss R <durgadoss.r@intel.com>

Thanks,
Durga

>---
> drivers/gpu/drm/i915/intel_psr.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index db95b39..0e3b652 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -264,11 +264,17 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 	uint32_t val = 0x0;
> 	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
>-	if (dev_priv->psr.link_standby) {
>+	if (dev_priv->psr.link_standby)
> 		val |= EDP_PSR_LINK_STANDBY;
>+
>+	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
>+		/* It doesn't mean we shouldn't send TPS patters, so let's
>+		   send the minimal TP1 possible and skip TP2. */
>+		val |= EDP_PSR_TP1_TIME_100us;
> 		val |= EDP_PSR_TP2_TP3_TIME_0us;
>-		val |= EDP_PSR_TP1_TIME_0us;
> 		val |= EDP_PSR_SKIP_AUX_EXIT;
>+		/* Sink should be able to train with the 5 or 6 idle patterns */
>+		idle_frames += 4;
> 	}
>
> 	I915_WRITE(EDP_PSR_CTL(dev), val |
>@@ -381,8 +387,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> 	/* First we check VBT, but we must respect sink and source
> 	 * known restrictions */
> 	dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>-	if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) ||
>-	    (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A))
>+	if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)
> 		dev_priv->psr.link_standby = true;
>
> 	dev_priv->psr.busy_frontbuffer_bits = 0;
>--
>2.1.0

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