* [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
@ 2011-06-22 6:41 ` Jingoo Han
0 siblings, 0 replies; 14+ messages in thread
From: Jingoo Han @ 2011-06-22 6:41 UTC (permalink / raw)
To: Kukjin Kim, Paul Mundt, linux-samsung-soc, linux-fbdev
Cc: Anand Kumar N, Thomas Abraham, Sylwester Nawrocki,
Marek Szyprowski, Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks,
Jonghun Han, Jingoo Han
From: Jonghun Han <jonghun.han@samsung.com>
This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
---
arch/arm/mach-exynos4/mach-smdkc210.c | 114 +++++++++++++++++++++++++++++++++
arch/arm/mach-exynos4/mach-smdkv310.c | 114 +++++++++++++++++++++++++++++++++
2 files changed, 228 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index e645f7a..360a50a 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,26 +9,33 @@
*/
#include <linux/serial_core.h>
+#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
#include <mach/map.h>
+#include <mach/regs-fb.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 1);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ /* fire nRESET on power up */
+ gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+ gpio_direction_output(EXYNOS4_GPX0(6), 1);
+ mdelay(100);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 0);
+ mdelay(10);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 1);
+ mdelay(10);
+
+ gpio_free(EXYNOS4_GPX0(6));
+ } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 0);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ }
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+ .set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+ .win_mode = {
+ .left_margin = 13,
+ .right_margin = 8,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+ .win[0] = &smdkc210_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &s5p_device_fimd0,
+ &smdkc210_lcd_lte480wv,
&smdkc210_smsc911x,
};
@@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+static int __init smdkc210_fimd0_setup_clock(void)
+{
+ struct clk *sclk = NULL;
+ struct clk *mout_mpll = NULL;
+
+ u32 rate = 0;
+
+ sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
+ if (IS_ERR(sclk)) {
+ printk(KERN_ERR "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ mout_mpll = clk_get(NULL, "mout_mpll");
+ if (IS_ERR(mout_mpll)) {
+ printk(KERN_ERR "failed to get mout_mpll\n");
+ goto err_clk1;
+ }
+
+ clk_set_parent(sclk, mout_mpll);
+ if (!rate)
+ rate = 134000000;
+
+ clk_set_rate(sclk, rate);
+
+ clk_put(sclk);
+ clk_put(mout_mpll);
+
+ return 0;
+
+err_clk1:
+ clk_put(mout_mpll);
+err_clk2:
+ clk_put(sclk);
+
+ return -EINVAL;
+}
+
static void __init smdkc210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -210,7 +320,11 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+ s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+ smdkc210_fimd0_setup_clock();
}
MACHINE_START(SMDKC210, "SMDKC210")
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 1526764..7bc12b5 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -9,28 +9,35 @@
*/
#include <linux/serial_core.h>
+#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/keypad.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
#include <mach/map.h>
+#include <mach/regs-fb.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -113,6 +120,69 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 1);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ /* fire nRESET on power up */
+ gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+ gpio_direction_output(EXYNOS4_GPX0(6), 1);
+ mdelay(100);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 0);
+ mdelay(10);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 1);
+ mdelay(10);
+
+ gpio_free(EXYNOS4_GPX0(6));
+ } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 0);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ }
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+ .set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+ .win_mode = {
+ .left_margin = 13,
+ .right_margin = 8,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+ .win[0] = &smdkv310_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct resource smdkv310_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@@ -187,6 +257,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &s5p_device_fimd0,
+ &smdkv310_lcd_lte480wv,
&smdkv310_smsc911x,
};
@@ -213,6 +285,44 @@ static void __init smdkv310_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+static int __init smdkv310_fimd0_setup_clock(void)
+{
+ struct clk *sclk = NULL;
+ struct clk *mout_mpll = NULL;
+
+ u32 rate = 0;
+
+ sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
+ if (IS_ERR(sclk)) {
+ printk(KERN_ERR "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ mout_mpll = clk_get(NULL, "mout_mpll");
+ if (IS_ERR(mout_mpll)) {
+ printk(KERN_ERR "failed to get mout_mpll\n");
+ goto err_clk1;
+ }
+
+ clk_set_parent(sclk, mout_mpll);
+ if (!rate)
+ rate = 134000000;
+
+ clk_set_rate(sclk, rate);
+
+ clk_put(sclk);
+ clk_put(mout_mpll);
+
+ return 0;
+
+err_clk1:
+ clk_put(mout_mpll);
+err_clk2:
+ clk_put(sclk);
+
+ return -EINVAL;
+}
+
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -232,9 +342,13 @@ static void __init smdkv310_machine_init(void)
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+ s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+
samsung_keypad_set_platdata(&smdkv310_keypad_data);
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+
+ smdkv310_fimd0_setup_clock();
}
MACHINE_START(SMDKV310, "SMDKV310")
--
1.7.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
@ 2011-06-22 6:41 ` Jingoo Han
0 siblings, 0 replies; 14+ messages in thread
From: Jingoo Han @ 2011-06-22 6:41 UTC (permalink / raw)
To: Kukjin Kim, Paul Mundt, linux-samsung-soc, linux-fbdev
Cc: Anand Kumar N, Thomas Abraham, Sylwester Nawrocki,
Marek Szyprowski, Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks,
Jonghun Han, Jingoo Han
From: Jonghun Han <jonghun.han@samsung.com>
This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
---
arch/arm/mach-exynos4/mach-smdkc210.c | 114 +++++++++++++++++++++++++++++++++
arch/arm/mach-exynos4/mach-smdkv310.c | 114 +++++++++++++++++++++++++++++++++
2 files changed, 228 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index e645f7a..360a50a 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,26 +9,33 @@
*/
#include <linux/serial_core.h>
+#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
#include <mach/map.h>
+#include <mach/regs-fb.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 1);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ /* fire nRESET on power up */
+ gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+ gpio_direction_output(EXYNOS4_GPX0(6), 1);
+ mdelay(100);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 0);
+ mdelay(10);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 1);
+ mdelay(10);
+
+ gpio_free(EXYNOS4_GPX0(6));
+ } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 0);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ }
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+ .set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+ .win_mode = {
+ .left_margin = 13,
+ .right_margin = 8,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+ .win[0] = &smdkc210_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &s5p_device_fimd0,
+ &smdkc210_lcd_lte480wv,
&smdkc210_smsc911x,
};
@@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+static int __init smdkc210_fimd0_setup_clock(void)
+{
+ struct clk *sclk = NULL;
+ struct clk *mout_mpll = NULL;
+
+ u32 rate = 0;
+
+ sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
+ if (IS_ERR(sclk)) {
+ printk(KERN_ERR "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ mout_mpll = clk_get(NULL, "mout_mpll");
+ if (IS_ERR(mout_mpll)) {
+ printk(KERN_ERR "failed to get mout_mpll\n");
+ goto err_clk1;
+ }
+
+ clk_set_parent(sclk, mout_mpll);
+ if (!rate)
+ rate = 134000000;
+
+ clk_set_rate(sclk, rate);
+
+ clk_put(sclk);
+ clk_put(mout_mpll);
+
+ return 0;
+
+err_clk1:
+ clk_put(mout_mpll);
+err_clk2:
+ clk_put(sclk);
+
+ return -EINVAL;
+}
+
static void __init smdkc210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -210,7 +320,11 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+ s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+
+ smdkc210_fimd0_setup_clock();
}
MACHINE_START(SMDKC210, "SMDKC210")
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 1526764..7bc12b5 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -9,28 +9,35 @@
*/
#include <linux/serial_core.h>
+#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/keypad.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
#include <mach/map.h>
+#include <mach/regs-fb.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -113,6 +120,69 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 1);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ /* fire nRESET on power up */
+ gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+ gpio_direction_output(EXYNOS4_GPX0(6), 1);
+ mdelay(100);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 0);
+ mdelay(10);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 1);
+ mdelay(10);
+
+ gpio_free(EXYNOS4_GPX0(6));
+ } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request(EXYNOS4_GPD0(1), "GPD0");
+ gpio_direction_output(EXYNOS4_GPD0(1), 0);
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ }
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+ .set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+ .win_mode = {
+ .left_margin = 13,
+ .right_margin = 8,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+ .win[0] = &smdkv310_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct resource smdkv310_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@@ -187,6 +257,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &s5p_device_fimd0,
+ &smdkv310_lcd_lte480wv,
&smdkv310_smsc911x,
};
@@ -213,6 +285,44 @@ static void __init smdkv310_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+static int __init smdkv310_fimd0_setup_clock(void)
+{
+ struct clk *sclk = NULL;
+ struct clk *mout_mpll = NULL;
+
+ u32 rate = 0;
+
+ sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
+ if (IS_ERR(sclk)) {
+ printk(KERN_ERR "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ mout_mpll = clk_get(NULL, "mout_mpll");
+ if (IS_ERR(mout_mpll)) {
+ printk(KERN_ERR "failed to get mout_mpll\n");
+ goto err_clk1;
+ }
+
+ clk_set_parent(sclk, mout_mpll);
+ if (!rate)
+ rate = 134000000;
+
+ clk_set_rate(sclk, rate);
+
+ clk_put(sclk);
+ clk_put(mout_mpll);
+
+ return 0;
+
+err_clk1:
+ clk_put(mout_mpll);
+err_clk2:
+ clk_put(sclk);
+
+ return -EINVAL;
+}
+
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -232,9 +342,13 @@ static void __init smdkv310_machine_init(void)
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+ s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+
samsung_keypad_set_platdata(&smdkv310_keypad_data);
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+
+ smdkv310_fimd0_setup_clock();
}
MACHINE_START(SMDKV310, "SMDKV310")
--
1.7.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD
2011-06-22 6:41 ` Jingoo Han
@ 2011-06-22 8:56 ` Sylwester Nawrocki
-1 siblings, 0 replies; 14+ messages in thread
From: Sylwester Nawrocki @ 2011-06-22 8:56 UTC (permalink / raw)
To: Jingoo Han
Cc: Kukjin Kim, Paul Mundt, linux-samsung-soc, linux-fbdev,
Jonghun Han, Anand Kumar N, Thomas Abraham, Marek Szyprowski,
Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks
Hello,
On 06/22/2011 08:41 AM, Jingoo Han wrote:
> From: Jonghun Han <jonghun.han@samsung.com>
>
> This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
>
> Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm/mach-exynos4/mach-smdkc210.c | 114 +++++++++++++++++++++++++++++++++
> arch/arm/mach-exynos4/mach-smdkv310.c | 114 +++++++++++++++++++++++++++++++++
> 2 files changed, 228 insertions(+), 0 deletions(-)
...
> +static int __init smdkc210_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
You don't need initialize to NULL here.
> +
> + u32 rate = 0;
Other than this variable is not really needed I would make it unsigned long.
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
You could just do:
return PTR_ERR(sclk);
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
134000000UL
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
clk_put is supposed to be used only for clocks that were successfully acquired.
> +err_clk2:
> + clk_put(sclk);
Ditto.
> +
> + return -EINVAL;
> +}
...
> +static int __init smdkv310_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
> +
> + u32 rate = 0;
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
> +err_clk2:
> + clk_put(sclk);
> +
> + return -EINVAL;
> +}
We have multiple copies of same function and I suspect other boards will try
to repeat this pattern which is not that good.
It would be worth to create common function for all boards if we really
must have that, e.g.
int __init exynos4_fimd_setup_clock(struct device *dev, const char *parent,
unsigned long clk_rate);
{
struct clk *clk_parent;
struct clk *sclk;
sclk = clk_get(dev, "sclk_fimd");
if (IS_ERR(sclk))
return PTR_ERR(sclk);
clk_parent = clk_get(NULL, parent);
if (IS_ERR(parent_clk)) {
clk_put(sclk);
return PTR_ERR(clk_parent);
}
clk_set_parent(sclk, clk_parent);
if (!rate)
rate = 134000000UL;
clk_set_rate(sclk, rate);
clk_put(sclk);
clk_put(clk_parent);
return 0;
}
But I have no idea where to put that...
Perhaps we should create common mach-exynos4/setup-fimd.c file for FIMD0, FIMD1.
But then it would contain ugly #ifdef for unused FIMD1 setup functions
("#ifdef CONFIG_DEV_FIMD0 ..") if only FIMD0 is used. Maybe someone else has
better idea.
Regards,
--
Sylwester Nawrocki
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
@ 2011-06-22 8:56 ` Sylwester Nawrocki
0 siblings, 0 replies; 14+ messages in thread
From: Sylwester Nawrocki @ 2011-06-22 8:56 UTC (permalink / raw)
To: Jingoo Han
Cc: Kukjin Kim, Paul Mundt, linux-samsung-soc, linux-fbdev,
Jonghun Han, Anand Kumar N, Thomas Abraham, Marek Szyprowski,
Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks
Hello,
On 06/22/2011 08:41 AM, Jingoo Han wrote:
> From: Jonghun Han <jonghun.han@samsung.com>
>
> This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
>
> Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm/mach-exynos4/mach-smdkc210.c | 114 +++++++++++++++++++++++++++++++++
> arch/arm/mach-exynos4/mach-smdkv310.c | 114 +++++++++++++++++++++++++++++++++
> 2 files changed, 228 insertions(+), 0 deletions(-)
...
> +static int __init smdkc210_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
You don't need initialize to NULL here.
> +
> + u32 rate = 0;
Other than this variable is not really needed I would make it unsigned long.
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
You could just do:
return PTR_ERR(sclk);
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
134000000UL
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
clk_put is supposed to be used only for clocks that were successfully acquired.
> +err_clk2:
> + clk_put(sclk);
Ditto.
> +
> + return -EINVAL;
> +}
...
> +static int __init smdkv310_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
> +
> + u32 rate = 0;
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
> +err_clk2:
> + clk_put(sclk);
> +
> + return -EINVAL;
> +}
We have multiple copies of same function and I suspect other boards will try
to repeat this pattern which is not that good.
It would be worth to create common function for all boards if we really
must have that, e.g.
int __init exynos4_fimd_setup_clock(struct device *dev, const char *parent,
unsigned long clk_rate);
{
struct clk *clk_parent;
struct clk *sclk;
sclk = clk_get(dev, "sclk_fimd");
if (IS_ERR(sclk))
return PTR_ERR(sclk);
clk_parent = clk_get(NULL, parent);
if (IS_ERR(parent_clk)) {
clk_put(sclk);
return PTR_ERR(clk_parent);
}
clk_set_parent(sclk, clk_parent);
if (!rate)
rate = 134000000UL;
clk_set_rate(sclk, rate);
clk_put(sclk);
clk_put(clk_parent);
return 0;
}
But I have no idea where to put that...
Perhaps we should create common mach-exynos4/setup-fimd.c file for FIMD0, FIMD1.
But then it would contain ugly #ifdef for unused FIMD1 setup functions
("#ifdef CONFIG_DEV_FIMD0 ..") if only FIMD0 is used. Maybe someone else has
better idea.
Regards,
--
Sylwester Nawrocki
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD
2011-06-22 6:41 ` Jingoo Han
@ 2011-06-22 9:47 ` Marek Szyprowski
-1 siblings, 0 replies; 14+ messages in thread
From: Marek Szyprowski @ 2011-06-22 9:47 UTC (permalink / raw)
To: 'Jingoo Han', 'Kukjin Kim', 'Paul Mundt',
linux-samsung-soc, linux-fbdev
Cc: 'Anand Kumar N', 'Thomas Abraham',
Sylwester Nawrocki, 'Kyungmin Park', 'Inki Dae',
'ARM Linux', 'Ben Dooks', 'Jonghun Han'
Hello,
On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
> From: Jonghun Han <jonghun.han@samsung.com>
>
> This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
>
> Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm/mach-exynos4/mach-smdkc210.c | 114
> +++++++++++++++++++++++++++++++++
> arch/arm/mach-exynos4/mach-smdkv310.c | 114
> +++++++++++++++++++++++++++++++++
> 2 files changed, 228 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-
> exynos4/mach-smdkc210.c
> index e645f7a..360a50a 100644
> --- a/arch/arm/mach-exynos4/mach-smdkc210.c
> +++ b/arch/arm/mach-exynos4/mach-smdkc210.c
> @@ -9,26 +9,33 @@
> */
>
> #include <linux/serial_core.h>
> +#include <linux/delay.h>
> #include <linux/gpio.h>
> +#include <linux/lcd.h>
> #include <linux/mmc/host.h>
> #include <linux/platform_device.h>
> #include <linux/smsc911x.h>
> #include <linux/io.h>
> #include <linux/i2c.h>
> +#include <linux/clk.h>
>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
>
> +#include <video/platform_lcd.h>
> +
> #include <plat/regs-serial.h>
> #include <plat/regs-srom.h>
> #include <plat/exynos4.h>
> #include <plat/cpu.h>
> #include <plat/devs.h>
> +#include <plat/fb.h>
> #include <plat/sdhci.h>
> #include <plat/iic.h>
> #include <plat/pd.h>
>
> #include <mach/map.h>
> +#include <mach/regs-fb.h>
>
> /* Following are default values for UCON, ULCON and UFCON UART registers
> */
> #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
> @@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata
> __initdata = {
> .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
> };
>
> +static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
> + unsigned int power)
> +{
> + if (power) {
> +#if !defined(CONFIG_BACKLIGHT_PWM)
> + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> + gpio_direction_output(EXYNOS4_GPD0(1), 1);
> + gpio_free(EXYNOS4_GPD0(1));
> +#endif
> + /* fire nRESET on power up */
> + gpio_request(EXYNOS4_GPX0(6), "GPX0");
> +
> + gpio_direction_output(EXYNOS4_GPX0(6), 1);
> + mdelay(100);
> +
> + gpio_set_value(EXYNOS4_GPX0(6), 0);
> + mdelay(10);
> +
> + gpio_set_value(EXYNOS4_GPX0(6), 1);
> + mdelay(10);
> +
> + gpio_free(EXYNOS4_GPX0(6));
> + } else {
> +#if !defined(CONFIG_BACKLIGHT_PWM)
> + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> + gpio_direction_output(EXYNOS4_GPD0(1), 0);
> + gpio_free(EXYNOS4_GPD0(1));
> +#endif
> + }
> +}
> +
> +static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
> + .set_power = lcd_lte480wv_set_power,
> +};
> +
> +static struct platform_device smdkc210_lcd_lte480wv = {
> + .name = "platform-lcd",
> + .dev.parent = &s5p_device_fimd0.dev,
> + .dev.platform_data = &smdkc210_lcd_lte480wv_data,
> +};
> +
> +static struct s3c_fb_pd_win smdkc210_fb_win0 = {
> + .win_mode = {
> + .left_margin = 13,
> + .right_margin = 8,
> + .upper_margin = 7,
> + .lower_margin = 5,
> + .hsync_len = 3,
> + .vsync_len = 1,
> + .xres = 800,
> + .yres = 480,
> + },
> + .max_bpp = 32,
> + .default_bpp = 24,
> +};
> +
> +static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
> + .win[0] = &smdkc210_fb_win0,
> + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
> +};
> +
> static struct resource smdkc210_smsc911x_resources[] = {
> [0] = {
> .start = EXYNOS4_PA_SROM_BANK(1),
> @@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[]
> __initdata = {
> &exynos4_device_pd[PD_GPS],
> &exynos4_device_sysmmu,
> &samsung_asoc_dma,
> + &s5p_device_fimd0,
> + &smdkc210_lcd_lte480wv,
> &smdkc210_smsc911x,
> };
>
> @@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
> (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
> }
>
> +static int __init smdkc210_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
> +
> + u32 rate = 0;
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
> +err_clk2:
> + clk_put(sclk);
> +
> + return -EINVAL;
> +}
> +
I'm not sure if mach-smdk*.c is the right place for the above code.
IMHO all the code that configures very low level, board specific parameters
(like clocks and their relations) should be performed in boot loarder.
(snipped)
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 14+ messages in thread* RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
@ 2011-06-22 9:47 ` Marek Szyprowski
0 siblings, 0 replies; 14+ messages in thread
From: Marek Szyprowski @ 2011-06-22 9:47 UTC (permalink / raw)
To: 'Jingoo Han', 'Kukjin Kim', 'Paul Mundt',
linux-samsung-soc, linux-fbdev
Cc: 'Anand Kumar N', 'Thomas Abraham',
Sylwester Nawrocki, 'Kyungmin Park', 'Inki Dae',
'ARM Linux', 'Ben Dooks', 'Jonghun Han'
Hello,
On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
> From: Jonghun Han <jonghun.han@samsung.com>
>
> This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
>
> Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> ---
> arch/arm/mach-exynos4/mach-smdkc210.c | 114
> +++++++++++++++++++++++++++++++++
> arch/arm/mach-exynos4/mach-smdkv310.c | 114
> +++++++++++++++++++++++++++++++++
> 2 files changed, 228 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-
> exynos4/mach-smdkc210.c
> index e645f7a..360a50a 100644
> --- a/arch/arm/mach-exynos4/mach-smdkc210.c
> +++ b/arch/arm/mach-exynos4/mach-smdkc210.c
> @@ -9,26 +9,33 @@
> */
>
> #include <linux/serial_core.h>
> +#include <linux/delay.h>
> #include <linux/gpio.h>
> +#include <linux/lcd.h>
> #include <linux/mmc/host.h>
> #include <linux/platform_device.h>
> #include <linux/smsc911x.h>
> #include <linux/io.h>
> #include <linux/i2c.h>
> +#include <linux/clk.h>
>
> #include <asm/mach/arch.h>
> #include <asm/mach-types.h>
>
> +#include <video/platform_lcd.h>
> +
> #include <plat/regs-serial.h>
> #include <plat/regs-srom.h>
> #include <plat/exynos4.h>
> #include <plat/cpu.h>
> #include <plat/devs.h>
> +#include <plat/fb.h>
> #include <plat/sdhci.h>
> #include <plat/iic.h>
> #include <plat/pd.h>
>
> #include <mach/map.h>
> +#include <mach/regs-fb.h>
>
> /* Following are default values for UCON, ULCON and UFCON UART registers
> */
> #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
> @@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata
> __initdata = {
> .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
> };
>
> +static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
> + unsigned int power)
> +{
> + if (power) {
> +#if !defined(CONFIG_BACKLIGHT_PWM)
> + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> + gpio_direction_output(EXYNOS4_GPD0(1), 1);
> + gpio_free(EXYNOS4_GPD0(1));
> +#endif
> + /* fire nRESET on power up */
> + gpio_request(EXYNOS4_GPX0(6), "GPX0");
> +
> + gpio_direction_output(EXYNOS4_GPX0(6), 1);
> + mdelay(100);
> +
> + gpio_set_value(EXYNOS4_GPX0(6), 0);
> + mdelay(10);
> +
> + gpio_set_value(EXYNOS4_GPX0(6), 1);
> + mdelay(10);
> +
> + gpio_free(EXYNOS4_GPX0(6));
> + } else {
> +#if !defined(CONFIG_BACKLIGHT_PWM)
> + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> + gpio_direction_output(EXYNOS4_GPD0(1), 0);
> + gpio_free(EXYNOS4_GPD0(1));
> +#endif
> + }
> +}
> +
> +static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
> + .set_power = lcd_lte480wv_set_power,
> +};
> +
> +static struct platform_device smdkc210_lcd_lte480wv = {
> + .name = "platform-lcd",
> + .dev.parent = &s5p_device_fimd0.dev,
> + .dev.platform_data = &smdkc210_lcd_lte480wv_data,
> +};
> +
> +static struct s3c_fb_pd_win smdkc210_fb_win0 = {
> + .win_mode = {
> + .left_margin = 13,
> + .right_margin = 8,
> + .upper_margin = 7,
> + .lower_margin = 5,
> + .hsync_len = 3,
> + .vsync_len = 1,
> + .xres = 800,
> + .yres = 480,
> + },
> + .max_bpp = 32,
> + .default_bpp = 24,
> +};
> +
> +static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
> + .win[0] = &smdkc210_fb_win0,
> + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
> +};
> +
> static struct resource smdkc210_smsc911x_resources[] = {
> [0] = {
> .start = EXYNOS4_PA_SROM_BANK(1),
> @@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[]
> __initdata = {
> &exynos4_device_pd[PD_GPS],
> &exynos4_device_sysmmu,
> &samsung_asoc_dma,
> + &s5p_device_fimd0,
> + &smdkc210_lcd_lte480wv,
> &smdkc210_smsc911x,
> };
>
> @@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
> (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
> }
>
> +static int __init smdkc210_fimd0_setup_clock(void)
> +{
> + struct clk *sclk = NULL;
> + struct clk *mout_mpll = NULL;
> +
> + u32 rate = 0;
> +
> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> + if (IS_ERR(sclk)) {
> + printk(KERN_ERR "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + mout_mpll = clk_get(NULL, "mout_mpll");
> + if (IS_ERR(mout_mpll)) {
> + printk(KERN_ERR "failed to get mout_mpll\n");
> + goto err_clk1;
> + }
> +
> + clk_set_parent(sclk, mout_mpll);
> + if (!rate)
> + rate = 134000000;
> +
> + clk_set_rate(sclk, rate);
> +
> + clk_put(sclk);
> + clk_put(mout_mpll);
> +
> + return 0;
> +
> +err_clk1:
> + clk_put(mout_mpll);
> +err_clk2:
> + clk_put(sclk);
> +
> + return -EINVAL;
> +}
> +
I'm not sure if mach-smdk*.c is the right place for the above code.
IMHO all the code that configures very low level, board specific parameters
(like clocks and their relations) should be performed in boot loarder.
(snipped)
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply [flat|nested] 14+ messages in thread[parent not found: <BANLkTimPjo+WefApQLe=HKbYLCwmo_gGRw@mail.gmail.com>]
* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
[not found] ` <BANLkTimPjo+WefApQLe=HKbYLCwmo_gGRw@mail.gmail.com>
@ 2011-06-22 13:37 ` Anand Kumar N
0 siblings, 0 replies; 14+ messages in thread
From: Anand Kumar N @ 2011-06-22 13:25 UTC (permalink / raw)
To: Marek Szyprowski
Cc: Jingoo Han, Kukjin Kim, Paul Mundt, linux-samsung-soc,
linux-fbdev, Jonghun Han, Thomas Abraham, Sylwester Nawrocki,
Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks
Hi Marek/Jingoo,
On Wed, Jun 22, 2011 at 3:17 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
>
>> From: Jonghun Han <jonghun.han@samsung.com>
(snipped)
Instead of hardcoding the parent clock in platform/bootloader code ,is
it not possible to select/set the
parent clock based on the pixel clk(plat data) having the least delta
with the 9 src clks.with this change I have checked it for WA101S.
These are the changes I am proposing..
arch/arm/mach-exynos4/clock.c
+struct clk *clkset_sclk_fimd0_list[] = {
+ [0] = &clk_sclk_xxti,
+ [1] = &clk_sclk_xusbxti,
+ [2] = &clk_sclk_hdmi27m,
+ [3] = &clk_sclk_usbphy0,
+ [4] = &clk_sclk_usbphy1,
+ [5] = &clk_sclk_hdmiphy,
+ [6] = &clk_mout_mpll.clk,
+ [7] = &clk_mout_epll.clk,
+ [8] = &clk_sclk_vpll.clk,
+};
arch/arm/mach-exynos4/mach-smdkv310.c
+static int fimd_s3c_consider_clock(struct device *sfb,int src
,unsigned int wanted)
+{
+ unsigned long rate = 0;
+ int div =1;
+ struct clk *mout_mpll = NULL;
+
+ if(clkset_sclk_fimd0_list[src]){
+ mout_mpll = clk_get(sfb,clkset_sclk_fimd0_list[src]->name);
+ if (IS_ERR(mout_mpll)) {
+ dev_err(sfb, "failed to clk_get
%s\n",clkset_sclk_fimd0_list[src]->name);
+ }
+
+ rate = clk_get_rate(mout_mpll);
+
+ for (div = 1; div < 256; div *= 2) {
+ if ((rate / div) <= wanted)
+ break;
+ }
+
+
+ }
+ return (wanted - (rate / div));
+}
+
+int exynos4_fimd0_find_clock(struct platform_device *pdev,struct clk
**lcd_clk,unsigned int clock(pixel clock needed for the lcd))
+{
+ int best = 0;
+ int delta = 0;
+ int best_src = 0;
+ int src;
+ struct clk *best_clk_src = NULL;
+ struct clk *clk = NULL;
+
+ if (clock == 0)
+ return 0;
+
+ for (src = 0; src < MAX_NUM_CLKS ;src++) {
+ delta = fimd_s3c_consider_clock(&pdev->dev,src,clock);
+ if (delta < best) {
+ best = delta;
+ best_src = src;
+ }
+ }
+ clk = clk_get(&pdev->dev, "sclk_fimd");
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ best_clk_src =
clk_get(&pdev->dev,clkset_sclk_fimd0_list[best_src]->name);
+ if (IS_ERR(best_clk_src)) {
+ dev_err(&pdev->dev, "failed to get best_src\n");
+ goto err_clk1;
+ }
+ clk_set_parent(clk,best_clk_src);
+ *lcd_clk = clk;
+ clk_put(best_clk_src);
+ clk_enable(clk);
+ dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", clock);
+
+err_clk1:
+ clk_put(best_clk_src);
+err_clk2:
+ clk_put(clk);
+
+ return -EINVAL;
+}
I have based these patches on the v1 version of this patch.I can base
these changes
on your latest changes(v6) and send as a patch.
>> +static int __init smdkc210_fimd0_setup_clock(void)
>> +{
>> + struct clk *sclk = NULL;
>> + struct clk *mout_mpll = NULL;
>> +
>> + u32 rate = 0;
>> +
>> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
>> + if (IS_ERR(sclk)) {
>> + printk(KERN_ERR "failed to get sclk for fimd\n");
>> + goto err_clk2;
>> + }
>> +
>> + mout_mpll = clk_get(NULL, "mout_mpll");
>> + if (IS_ERR(mout_mpll)) {
>> + printk(KERN_ERR "failed to get mout_mpll\n");
>> + goto err_clk1;
>> + }
>> +
>> + clk_set_parent(sclk, mout_mpll);
>> + if (!rate)
>> + rate = 134000000;
>> +
>> + clk_set_rate(sclk, rate);
>> +
>> + clk_put(sclk);
>> + clk_put(mout_mpll);
>> +
>> + return 0;
>> +
>> +err_clk1:
>> + clk_put(mout_mpll);
>> +err_clk2:
>> + clk_put(sclk);
>> +
>> + return -EINVAL;
>> +}
>> +
>
> I'm not sure if mach-smdk*.c is the right place for the above code.
> IMHO all the code that configures very low level, board specific parameters
> (like clocks and their relations) should be performed in boot loarder.
>
I feel pushing the clock enabling into the bootloader,will create an
unneccesary dependcy for the lcd on the u-boot.
> (snipped)
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
regards
anand
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD
@ 2011-06-22 13:37 ` Anand Kumar N
0 siblings, 0 replies; 14+ messages in thread
From: Anand Kumar N @ 2011-06-22 13:37 UTC (permalink / raw)
To: Marek Szyprowski
Cc: Jingoo Han, Kukjin Kim, Paul Mundt, linux-samsung-soc,
linux-fbdev, Jonghun Han, Thomas Abraham, Sylwester Nawrocki,
Kyungmin Park, Inki Dae, ARM Linux, Ben Dooks
Hi Marek/Jingoo,
On Wed, Jun 22, 2011 at 3:17 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hello,
>
> On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
>
>> From: Jonghun Han <jonghun.han@samsung.com>
(snipped)
Instead of hardcoding the parent clock in platform/bootloader code ,is
it not possible to select/set the
parent clock based on the pixel clk(plat data) having the least delta
with the 9 src clks.with this change I have checked it for WA101S.
These are the changes I am proposing..
arch/arm/mach-exynos4/clock.c
+struct clk *clkset_sclk_fimd0_list[] = {
+ [0] = &clk_sclk_xxti,
+ [1] = &clk_sclk_xusbxti,
+ [2] = &clk_sclk_hdmi27m,
+ [3] = &clk_sclk_usbphy0,
+ [4] = &clk_sclk_usbphy1,
+ [5] = &clk_sclk_hdmiphy,
+ [6] = &clk_mout_mpll.clk,
+ [7] = &clk_mout_epll.clk,
+ [8] = &clk_sclk_vpll.clk,
+};
arch/arm/mach-exynos4/mach-smdkv310.c
+static int fimd_s3c_consider_clock(struct device *sfb,int src
,unsigned int wanted)
+{
+ unsigned long rate = 0;
+ int div =1;
+ struct clk *mout_mpll = NULL;
+
+ if(clkset_sclk_fimd0_list[src]){
+ mout_mpll = clk_get(sfb,clkset_sclk_fimd0_list[src]->name);
+ if (IS_ERR(mout_mpll)) {
+ dev_err(sfb, "failed to clk_get
%s\n",clkset_sclk_fimd0_list[src]->name);
+ }
+
+ rate = clk_get_rate(mout_mpll);
+
+ for (div = 1; div < 256; div *= 2) {
+ if ((rate / div) <= wanted)
+ break;
+ }
+
+
+ }
+ return (wanted - (rate / div));
+}
+
+int exynos4_fimd0_find_clock(struct platform_device *pdev,struct clk
**lcd_clk,unsigned int clock(pixel clock needed for the lcd))
+{
+ int best = 0;
+ int delta = 0;
+ int best_src = 0;
+ int src;
+ struct clk *best_clk_src = NULL;
+ struct clk *clk = NULL;
+
+ if (clock = 0)
+ return 0;
+
+ for (src = 0; src < MAX_NUM_CLKS ;src++) {
+ delta = fimd_s3c_consider_clock(&pdev->dev,src,clock);
+ if (delta < best) {
+ best = delta;
+ best_src = src;
+ }
+ }
+ clk = clk_get(&pdev->dev, "sclk_fimd");
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get sclk for fimd\n");
+ goto err_clk2;
+ }
+
+ best_clk_src clk_get(&pdev->dev,clkset_sclk_fimd0_list[best_src]->name);
+ if (IS_ERR(best_clk_src)) {
+ dev_err(&pdev->dev, "failed to get best_src\n");
+ goto err_clk1;
+ }
+ clk_set_parent(clk,best_clk_src);
+ *lcd_clk = clk;
+ clk_put(best_clk_src);
+ clk_enable(clk);
+ dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", clock);
+
+err_clk1:
+ clk_put(best_clk_src);
+err_clk2:
+ clk_put(clk);
+
+ return -EINVAL;
+}
I have based these patches on the v1 version of this patch.I can base
these changes
on your latest changes(v6) and send as a patch.
>> +static int __init smdkc210_fimd0_setup_clock(void)
>> +{
>> + struct clk *sclk = NULL;
>> + struct clk *mout_mpll = NULL;
>> +
>> + u32 rate = 0;
>> +
>> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
>> + if (IS_ERR(sclk)) {
>> + printk(KERN_ERR "failed to get sclk for fimd\n");
>> + goto err_clk2;
>> + }
>> +
>> + mout_mpll = clk_get(NULL, "mout_mpll");
>> + if (IS_ERR(mout_mpll)) {
>> + printk(KERN_ERR "failed to get mout_mpll\n");
>> + goto err_clk1;
>> + }
>> +
>> + clk_set_parent(sclk, mout_mpll);
>> + if (!rate)
>> + rate = 134000000;
>> +
>> + clk_set_rate(sclk, rate);
>> +
>> + clk_put(sclk);
>> + clk_put(mout_mpll);
>> +
>> + return 0;
>> +
>> +err_clk1:
>> + clk_put(mout_mpll);
>> +err_clk2:
>> + clk_put(sclk);
>> +
>> + return -EINVAL;
>> +}
>> +
>
> I'm not sure if mach-smdk*.c is the right place for the above code.
> IMHO all the code that configures very low level, board specific parameters
> (like clocks and their relations) should be performed in boot loarder.
>
I feel pushing the clock enabling into the bootloader,will create an
unneccesary dependcy for the lcd on the u-boot.
> (snipped)
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
regards
anand
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD
2011-06-22 13:37 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD Anand Kumar N
@ 2011-06-22 20:33 ` Sylwester Nawrocki
-1 siblings, 0 replies; 14+ messages in thread
From: Sylwester Nawrocki @ 2011-06-22 20:33 UTC (permalink / raw)
To: Anand Kumar N
Cc: Marek Szyprowski, Jingoo Han, Kukjin Kim, Paul Mundt,
linux-samsung-soc, linux-fbdev, Jonghun Han, Thomas Abraham,
Sylwester Nawrocki, Kyungmin Park, Inki Dae, ARM Linux,
Ben Dooks
On 06/22/2011 03:25 PM, Anand Kumar N wrote:
> Instead of hardcoding the parent clock in platform/bootloader code ,is
> it not possible to select/set the
> parent clock based on the pixel clk(plat data) having the least delta
> with the 9 src clks.with this change I have checked it for WA101S.
While at first sight this may look as an awesome idea I don't really
believe it is. There might be other criteria that need to be considered,
like continuous clock availability or frequency stability.
That said we could possibly have the driver setting sclk_fimd frequency
based on display planes' properties (this was my initial suggestion)
but sclk_fimd parent should be fixed either by bootloader or board
initialization code.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
@ 2011-06-22 20:33 ` Sylwester Nawrocki
0 siblings, 0 replies; 14+ messages in thread
From: Sylwester Nawrocki @ 2011-06-22 20:33 UTC (permalink / raw)
To: Anand Kumar N
Cc: Marek Szyprowski, Jingoo Han, Kukjin Kim, Paul Mundt,
linux-samsung-soc, linux-fbdev, Jonghun Han, Thomas Abraham,
Sylwester Nawrocki, Kyungmin Park, Inki Dae, ARM Linux,
Ben Dooks
On 06/22/2011 03:25 PM, Anand Kumar N wrote:
> Instead of hardcoding the parent clock in platform/bootloader code ,is
> it not possible to select/set the
> parent clock based on the pixel clk(plat data) having the least delta
> with the 9 src clks.with this change I have checked it for WA101S.
While at first sight this may look as an awesome idea I don't really
believe it is. There might be other criteria that need to be considered,
like continuous clock availability or frequency stability.
That said we could possibly have the driver setting sclk_fimd frequency
based on display planes' properties (this was my initial suggestion)
but sclk_fimd parent should be fixed either by bootloader or board
initialization code.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
2011-06-22 6:41 ` Jingoo Han
@ 2011-06-23 1:09 ` JinGoo Han
-1 siblings, 0 replies; 14+ messages in thread
From: JinGoo Han @ 2011-06-23 1:09 UTC (permalink / raw)
To: ANAND KUMAR N, Marek Szyprowski
Cc: JinGoo Han, Kukjin Kim, Paul Mundt, linux-samsung-soc,
linux-fbdev, Jong-Hun Han, THOMAS P ABRAHAM, Sylwester Nawrocki,
Kyungmin Park, In-Ki Dae, ARM Linux, Ben Dooks
Hi, Anand.
> -----Original Message-----
> From: linux-samsung-soc-owner@vger.kernel.org [mailto:linux-samsung-soc-
> owner@vger.kernel.org] On Behalf Of Anand Kumar N
> Sent: Wednesday, June 22, 2011 10:25 PM
> To: Marek Szyprowski
> Cc: Jingoo Han; Kukjin Kim; Paul Mundt; linux-samsung-soc@vger.kernel.org;
> linux-fbdev@vger.kernel.org; Jonghun Han; Thomas Abraham; Sylwester
> Nawrocki; Kyungmin Park; Inki Dae; ARM Linux; Ben Dooks
> Subject: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
> FIMD and LTE480WV platform-lcd
>
> Hi Marek/Jingoo,
>
> On Wed, Jun 22, 2011 at 3:17 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
> >
> >> From: Jonghun Han <jonghun.han@samsung.com>
> (snipped)
> Instead of hardcoding the parent clock in platform/bootloader code ,is
> it not possible to select/set the
> parent clock based on the pixel clk(plat data) having the least delta
> with the 9 src clks.with this change I have checked it for WA101S.
> These are the changes I am proposing..
>
> arch/arm/mach-exynos4/clock.c
> +struct clk *clkset_sclk_fimd0_list[] = {
> + [0] = &clk_sclk_xxti,
> + [1] = &clk_sclk_xusbxti,
> + [2] = &clk_sclk_hdmi27m,
> + [3] = &clk_sclk_usbphy0,
> + [4] = &clk_sclk_usbphy1,
> + [5] = &clk_sclk_hdmiphy,
> + [6] = &clk_mout_mpll.clk,
> + [7] = &clk_mout_epll.clk,
> + [8] = &clk_sclk_vpll.clk,
> +};
As Sylwester Nawrocki mentioned, there would be criteria that should be considered
such as continuous clock availability or frequency stability.
For instance, when EPLL '[7] = &clk_mout_epll.clk,' is selected, there is posibility
that EPLL frequency will be changed by other devices.
However, Exynos4 FIMD can use a range of clocks as source clock, 'mout_mpll' is
most useful and can cover almost LCD pixel clock, because 'mout_mpll' is 800 MHz
and max frequency of 'sclk_fimd' can be set as 800MHz.
However, other clocks are very low. For example, HDMI PHY, VPLL are 54MHz,
USB PHY is 48MHz.
> arch/arm/mach-exynos4/mach-smdkv310.c
> +static int fimd_s3c_consider_clock(struct device *sfb,int src
> ,unsigned int wanted)
> +{
> + unsigned long rate = 0;
> + int div =1;
> + struct clk *mout_mpll = NULL;
> +
> + if(clkset_sclk_fimd0_list[src]){
> + mout_mpll = clk_get(sfb,clkset_sclk_fimd0_list[src]->name);
> + if (IS_ERR(mout_mpll)) {
> + dev_err(sfb, "failed to clk_get
> %s\n",clkset_sclk_fimd0_list[src]->name);
> + }
> +
> + rate = clk_get_rate(mout_mpll);
> +
> + for (div = 1; div < 256; div *= 2) {
> + if ((rate / div) <= wanted)
> + break;
> + }
> +
> +
> + }
> + return (wanted - (rate / div));
> +}
> +
> +int exynos4_fimd0_find_clock(struct platform_device *pdev,struct clk
> **lcd_clk,unsigned int clock(pixel clock needed for the lcd))
> +{
> + int best = 0;
> + int delta = 0;
> + int best_src = 0;
> + int src;
> + struct clk *best_clk_src = NULL;
> + struct clk *clk = NULL;
> +
> + if (clock == 0)
> + return 0;
> +
> + for (src = 0; src < MAX_NUM_CLKS ;src++) {
> + delta = fimd_s3c_consider_clock(&pdev->dev,src,clock);
> + if (delta < best) {
> + best = delta;
> + best_src = src;
> + }
> + }
> + clk = clk_get(&pdev->dev, "sclk_fimd");
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + best_clk_src =
> clk_get(&pdev->dev,clkset_sclk_fimd0_list[best_src]->name);
> + if (IS_ERR(best_clk_src)) {
> + dev_err(&pdev->dev, "failed to get best_src\n");
> + goto err_clk1;
> + }
> + clk_set_parent(clk,best_clk_src);
> + *lcd_clk = clk;
> + clk_put(best_clk_src);
> + clk_enable(clk);
> + dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", clock);
> +
> +err_clk1:
> + clk_put(best_clk_src);
> +err_clk2:
> + clk_put(clk);
> +
> + return -EINVAL;
> +}
> I have based these patches on the v1 version of this patch.I can base
> these changes
> on your latest changes(v6) and send as a patch.
>
> >> +static int __init smdkc210_fimd0_setup_clock(void)
> >> +{
> >> + struct clk *sclk = NULL;
> >> + struct clk *mout_mpll = NULL;
> >> +
> >> + u32 rate = 0;
> >> +
> >> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> >> + if (IS_ERR(sclk)) {
> >> + printk(KERN_ERR "failed to get sclk for fimd\n");
> >> + goto err_clk2;
> >> + }
> >> +
> >> + mout_mpll = clk_get(NULL, "mout_mpll");
> >> + if (IS_ERR(mout_mpll)) {
> >> + printk(KERN_ERR "failed to get mout_mpll\n");
> >> + goto err_clk1;
> >> + }
> >> +
> >> + clk_set_parent(sclk, mout_mpll);
> >> + if (!rate)
> >> + rate = 134000000;
> >> +
> >> + clk_set_rate(sclk, rate);
> >> +
> >> + clk_put(sclk);
> >> + clk_put(mout_mpll);
> >> +
> >> + return 0;
> >> +
> >> +err_clk1:
> >> + clk_put(mout_mpll);
> >> +err_clk2:
> >> + clk_put(sclk);
> >> +
> >> + return -EINVAL;
> >> +}
> >> +
> >
> > I'm not sure if mach-smdk*.c is the right place for the above code.
> > IMHO all the code that configures very low level, board specific
> parameters
> > (like clocks and their relations) should be performed in boot loarder.
> >
>
> I feel pushing the clock enabling into the bootloader,will create an
> unneccesary dependcy for the lcd on the u-boot.
>
> > (snipped)
> >
> > Best regards
> > --
> > Marek Szyprowski
> > Samsung Poland R&D Center
> >
> >
> >
> regards
> anand
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-
> soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-i
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
@ 2011-06-23 1:09 ` JinGoo Han
0 siblings, 0 replies; 14+ messages in thread
From: JinGoo Han @ 2011-06-23 1:09 UTC (permalink / raw)
To: ANAND KUMAR N, Marek Szyprowski
Cc: JinGoo Han, Kukjin Kim, Paul Mundt, linux-samsung-soc,
linux-fbdev, Jong-Hun Han, THOMAS P ABRAHAM, Sylwester Nawrocki,
Kyungmin Park, In-Ki Dae, ARM Linux, Ben Dooks
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="windows-1254", Size: 6229 bytes --]
Hi, Anand.
> -----Original Message-----
> From: linux-samsung-soc-owner@vger.kernel.org [mailto:linux-samsung-soc-
> owner@vger.kernel.org] On Behalf Of Anand Kumar N
> Sent: Wednesday, June 22, 2011 10:25 PM
> To: Marek Szyprowski
> Cc: Jingoo Han; Kukjin Kim; Paul Mundt; linux-samsung-soc@vger.kernel.org;
> linux-fbdev@vger.kernel.org; Jonghun Han; Thomas Abraham; Sylwester
> Nawrocki; Kyungmin Park; Inki Dae; ARM Linux; Ben Dooks
> Subject: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
> FIMD and LTE480WV platform-lcd
>
> Hi Marek/Jingoo,
>
> On Wed, Jun 22, 2011 at 3:17 PM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
> >
> >> From: Jonghun Han <jonghun.han@samsung.com>
> (snipped)
> Instead of hardcoding the parent clock in platform/bootloader code ,is
> it not possible to select/set the
> parent clock based on the pixel clk(plat data) having the least delta
> with the 9 src clks.with this change I have checked it for WA101S.
> These are the changes I am proposing..
>
> arch/arm/mach-exynos4/clock.c
> +struct clk *clkset_sclk_fimd0_list[] = {
> + [0] = &clk_sclk_xxti,
> + [1] = &clk_sclk_xusbxti,
> + [2] = &clk_sclk_hdmi27m,
> + [3] = &clk_sclk_usbphy0,
> + [4] = &clk_sclk_usbphy1,
> + [5] = &clk_sclk_hdmiphy,
> + [6] = &clk_mout_mpll.clk,
> + [7] = &clk_mout_epll.clk,
> + [8] = &clk_sclk_vpll.clk,
> +};
As Sylwester Nawrocki mentioned, there would be criteria that should be considered
such as continuous clock availability or frequency stability.
For instance, when EPLL '[7] = &clk_mout_epll.clk,' is selected, there is posibility
that EPLL frequency will be changed by other devices.
However, Exynos4 FIMD can use a range of clocks as source clock, 'mout_mpll' is
most useful and can cover almost LCD pixel clock, because 'mout_mpll' is 800 MHz
and max frequency of 'sclk_fimd' can be set as 800MHz.
However, other clocks are very low. For example, HDMI PHY, VPLL are 54MHz,
USB PHY is 48MHz.
> arch/arm/mach-exynos4/mach-smdkv310.c
> +static int fimd_s3c_consider_clock(struct device *sfb,int src
> ,unsigned int wanted)
> +{
> + unsigned long rate = 0;
> + int div =1;
> + struct clk *mout_mpll = NULL;
> +
> + if(clkset_sclk_fimd0_list[src]){
> + mout_mpll = clk_get(sfb,clkset_sclk_fimd0_list[src]->name);
> + if (IS_ERR(mout_mpll)) {
> + dev_err(sfb, "failed to clk_get
> %s\n",clkset_sclk_fimd0_list[src]->name);
> + }
> +
> + rate = clk_get_rate(mout_mpll);
> +
> + for (div = 1; div < 256; div *= 2) {
> + if ((rate / div) <= wanted)
> + break;
> + }
> +
> +
> + }
> + return (wanted - (rate / div));
> +}
> +
> +int exynos4_fimd0_find_clock(struct platform_device *pdev,struct clk
> **lcd_clk,unsigned int clock(pixel clock needed for the lcd))
> +{
> + int best = 0;
> + int delta = 0;
> + int best_src = 0;
> + int src;
> + struct clk *best_clk_src = NULL;
> + struct clk *clk = NULL;
> +
> + if (clock = 0)
> + return 0;
> +
> + for (src = 0; src < MAX_NUM_CLKS ;src++) {
> + delta = fimd_s3c_consider_clock(&pdev->dev,src,clock);
> + if (delta < best) {
> + best = delta;
> + best_src = src;
> + }
> + }
> + clk = clk_get(&pdev->dev, "sclk_fimd");
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "failed to get sclk for fimd\n");
> + goto err_clk2;
> + }
> +
> + best_clk_src > clk_get(&pdev->dev,clkset_sclk_fimd0_list[best_src]->name);
> + if (IS_ERR(best_clk_src)) {
> + dev_err(&pdev->dev, "failed to get best_src\n");
> + goto err_clk1;
> + }
> + clk_set_parent(clk,best_clk_src);
> + *lcd_clk = clk;
> + clk_put(best_clk_src);
> + clk_enable(clk);
> + dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", clock);
> +
> +err_clk1:
> + clk_put(best_clk_src);
> +err_clk2:
> + clk_put(clk);
> +
> + return -EINVAL;
> +}
> I have based these patches on the v1 version of this patch.I can base
> these changes
> on your latest changes(v6) and send as a patch.
>
> >> +static int __init smdkc210_fimd0_setup_clock(void)
> >> +{
> >> + struct clk *sclk = NULL;
> >> + struct clk *mout_mpll = NULL;
> >> +
> >> + u32 rate = 0;
> >> +
> >> + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> >> + if (IS_ERR(sclk)) {
> >> + printk(KERN_ERR "failed to get sclk for fimd\n");
> >> + goto err_clk2;
> >> + }
> >> +
> >> + mout_mpll = clk_get(NULL, "mout_mpll");
> >> + if (IS_ERR(mout_mpll)) {
> >> + printk(KERN_ERR "failed to get mout_mpll\n");
> >> + goto err_clk1;
> >> + }
> >> +
> >> + clk_set_parent(sclk, mout_mpll);
> >> + if (!rate)
> >> + rate = 134000000;
> >> +
> >> + clk_set_rate(sclk, rate);
> >> +
> >> + clk_put(sclk);
> >> + clk_put(mout_mpll);
> >> +
> >> + return 0;
> >> +
> >> +err_clk1:
> >> + clk_put(mout_mpll);
> >> +err_clk2:
> >> + clk_put(sclk);
> >> +
> >> + return -EINVAL;
> >> +}
> >> +
> >
> > I'm not sure if mach-smdk*.c is the right place for the above code.
> > IMHO all the code that configures very low level, board specific
> parameters
> > (like clocks and their relations) should be performed in boot loarder.
> >
>
> I feel pushing the clock enabling into the bootloader,will create an
> unneccesary dependcy for the lcd on the u-boot.
>
> > (snipped)
> >
> > Best regards
> > --
> > Marek Szyprowski
> > Samsung Poland R&D Center
> >
> >
> >
> regards
> anand
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-
> soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-i
ÿôèº{.nÇ+‰·Ÿ®‰†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±ýöÝzÿâžØ^n‡r¡ö¦zË\x1aëh™¨èÚ&£ûàz¿äz¹Þ—ú+€Ê+zf£¢·hšˆ§~††Ûiÿÿïêÿ‘êçz_è®\x0fæj:+v‰¨þ)ߣøm
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd
2011-06-22 6:41 ` Jingoo Han
@ 2011-06-23 6:44 ` JinGoo Han
-1 siblings, 0 replies; 14+ messages in thread
From: JinGoo Han @ 2011-06-23 6:44 UTC (permalink / raw)
To: Marek Szyprowski
Cc: JinGoo Han, Kukjin Kim, 'Paul Mundt',
linux-samsung-soc, linux-fbdev, Jong-Hun Han, ANAND KUMAR N,
THOMAS P ABRAHAM, Sylwester Nawrocki, 'Kyungmin Park',
In-Ki Dae, 'ARM Linux', 'Ben Dooks'
Hi, Marek.
> -----Original Message-----
> From: linux-fbdev-owner@vger.kernel.org [mailto:linux-fbdev-
> owner@vger.kernel.org] On Behalf Of Marek Szyprowski
> Sent: Wednesday, June 22, 2011 6:47 PM
> To: 'Jingoo Han'; 'Kukjin Kim'; 'Paul Mundt'; linux-samsung-
> soc@vger.kernel.org; linux-fbdev@vger.kernel.org; 'Jonghun Han'
> Cc: 'Anand Kumar N'; 'Thomas Abraham'; Sylwester Nawrocki; 'Kyungmin Park';
> 'Inki Dae'; 'ARM Linux'; 'Ben Dooks'; 'Jonghun Han'
> Subject: RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
> FIMD and LTE480WV platform-lcd
>
> Hello,
>
> On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
>
> > From: Jonghun Han <jonghun.han@samsung.com>
> >
> > This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
> >
> > Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> > Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> > ---
> > arch/arm/mach-exynos4/mach-smdkc210.c | 114
> > +++++++++++++++++++++++++++++++++
> > arch/arm/mach-exynos4/mach-smdkv310.c | 114
> > +++++++++++++++++++++++++++++++++
> > 2 files changed, 228 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-
> > exynos4/mach-smdkc210.c
> > index e645f7a..360a50a 100644
> > --- a/arch/arm/mach-exynos4/mach-smdkc210.c
> > +++ b/arch/arm/mach-exynos4/mach-smdkc210.c
> > @@ -9,26 +9,33 @@
> > */
> >
> > #include <linux/serial_core.h>
> > +#include <linux/delay.h>
> > #include <linux/gpio.h>
> > +#include <linux/lcd.h>
> > #include <linux/mmc/host.h>
> > #include <linux/platform_device.h>
> > #include <linux/smsc911x.h>
> > #include <linux/io.h>
> > #include <linux/i2c.h>
> > +#include <linux/clk.h>
> >
> > #include <asm/mach/arch.h>
> > #include <asm/mach-types.h>
> >
> > +#include <video/platform_lcd.h>
> > +
> > #include <plat/regs-serial.h>
> > #include <plat/regs-srom.h>
> > #include <plat/exynos4.h>
> > #include <plat/cpu.h>
> > #include <plat/devs.h>
> > +#include <plat/fb.h>
> > #include <plat/sdhci.h>
> > #include <plat/iic.h>
> > #include <plat/pd.h>
> >
> > #include <mach/map.h>
> > +#include <mach/regs-fb.h>
> >
> > /* Following are default values for UCON, ULCON and UFCON UART
> registers
> > */
> > #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
> > @@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata
> smdkc210_hsmmc3_pdata
> > __initdata = {
> > .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
> > };
> >
> > +static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
> > + unsigned int power)
> > +{
> > + if (power) {
> > +#if !defined(CONFIG_BACKLIGHT_PWM)
> > + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> > + gpio_direction_output(EXYNOS4_GPD0(1), 1);
> > + gpio_free(EXYNOS4_GPD0(1));
> > +#endif
> > + /* fire nRESET on power up */
> > + gpio_request(EXYNOS4_GPX0(6), "GPX0");
> > +
> > + gpio_direction_output(EXYNOS4_GPX0(6), 1);
> > + mdelay(100);
> > +
> > + gpio_set_value(EXYNOS4_GPX0(6), 0);
> > + mdelay(10);
> > +
> > + gpio_set_value(EXYNOS4_GPX0(6), 1);
> > + mdelay(10);
> > +
> > + gpio_free(EXYNOS4_GPX0(6));
> > + } else {
> > +#if !defined(CONFIG_BACKLIGHT_PWM)
> > + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> > + gpio_direction_output(EXYNOS4_GPD0(1), 0);
> > + gpio_free(EXYNOS4_GPD0(1));
> > +#endif
> > + }
> > +}
> > +
> > +static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
> > + .set_power = lcd_lte480wv_set_power,
> > +};
> > +
> > +static struct platform_device smdkc210_lcd_lte480wv = {
> > + .name = "platform-lcd",
> > + .dev.parent = &s5p_device_fimd0.dev,
> > + .dev.platform_data = &smdkc210_lcd_lte480wv_data,
> > +};
> > +
> > +static struct s3c_fb_pd_win smdkc210_fb_win0 = {
> > + .win_mode = {
> > + .left_margin = 13,
> > + .right_margin = 8,
> > + .upper_margin = 7,
> > + .lower_margin = 5,
> > + .hsync_len = 3,
> > + .vsync_len = 1,
> > + .xres = 800,
> > + .yres = 480,
> > + },
> > + .max_bpp = 32,
> > + .default_bpp = 24,
> > +};
> > +
> > +static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
> > + .win[0] = &smdkc210_fb_win0,
> > + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> > + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> > + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
> > +};
> > +
> > static struct resource smdkc210_smsc911x_resources[] = {
> > [0] = {
> > .start = EXYNOS4_PA_SROM_BANK(1),
> > @@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[]
> > __initdata = {
> > &exynos4_device_pd[PD_GPS],
> > &exynos4_device_sysmmu,
> > &samsung_asoc_dma,
> > + &s5p_device_fimd0,
> > + &smdkc210_lcd_lte480wv,
> > &smdkc210_smsc911x,
> > };
> >
> > @@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
> > (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
> > }
> >
> > +static int __init smdkc210_fimd0_setup_clock(void)
> > +{
> > + struct clk *sclk = NULL;
> > + struct clk *mout_mpll = NULL;
> > +
> > + u32 rate = 0;
> > +
> > + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> > + if (IS_ERR(sclk)) {
> > + printk(KERN_ERR "failed to get sclk for fimd\n");
> > + goto err_clk2;
> > + }
> > +
> > + mout_mpll = clk_get(NULL, "mout_mpll");
> > + if (IS_ERR(mout_mpll)) {
> > + printk(KERN_ERR "failed to get mout_mpll\n");
> > + goto err_clk1;
> > + }
> > +
> > + clk_set_parent(sclk, mout_mpll);
> > + if (!rate)
> > + rate = 134000000;
> > +
> > + clk_set_rate(sclk, rate);
> > +
> > + clk_put(sclk);
> > + clk_put(mout_mpll);
> > +
> > + return 0;
> > +
> > +err_clk1:
> > + clk_put(mout_mpll);
> > +err_clk2:
> > + clk_put(sclk);
> > +
> > + return -EINVAL;
> > +}
> > +
>
> I'm not sure if mach-smdk*.c is the right place for the above code.
> IMHO all the code that configures very low level, board specific
> parameters
> (like clocks and their relations) should be performed in boot loarder.
I agree with your suggestion.
I will remove the parent clock setting from the machine as fimc does.
I will send V7 patches, soon.
I really appreciate your review. Thank you.
>
> (snipped)
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
@ 2011-06-23 6:44 ` JinGoo Han
0 siblings, 0 replies; 14+ messages in thread
From: JinGoo Han @ 2011-06-23 6:44 UTC (permalink / raw)
To: Marek Szyprowski
Cc: JinGoo Han, Kukjin Kim, 'Paul Mundt',
linux-samsung-soc, linux-fbdev, Jong-Hun Han, ANAND KUMAR N,
THOMAS P ABRAHAM, Sylwester Nawrocki, 'Kyungmin Park',
In-Ki Dae, 'ARM Linux', 'Ben Dooks'
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="windows-1254", Size: 6516 bytes --]
Hi, Marek.
> -----Original Message-----
> From: linux-fbdev-owner@vger.kernel.org [mailto:linux-fbdev-
> owner@vger.kernel.org] On Behalf Of Marek Szyprowski
> Sent: Wednesday, June 22, 2011 6:47 PM
> To: 'Jingoo Han'; 'Kukjin Kim'; 'Paul Mundt'; linux-samsung-
> soc@vger.kernel.org; linux-fbdev@vger.kernel.org; 'Jonghun Han'
> Cc: 'Anand Kumar N'; 'Thomas Abraham'; Sylwester Nawrocki; 'Kyungmin Park';
> 'Inki Dae'; 'ARM Linux'; 'Ben Dooks'; 'Jonghun Han'
> Subject: RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4
> FIMD and LTE480WV platform-lcd
>
> Hello,
>
> On Wednesday, June 22, 2011 8:42 AM Jingoo Han wrote:
>
> > From: Jonghun Han <jonghun.han@samsung.com>
> >
> > This patch adds support EXYNOS4 FIMD0 and LTE480WV LCD pannel.
> >
> > Signed-off-by: Jonghun Han <jonghun.han@samsung.com>
> > Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> > ---
> > arch/arm/mach-exynos4/mach-smdkc210.c | 114
> > +++++++++++++++++++++++++++++++++
> > arch/arm/mach-exynos4/mach-smdkv310.c | 114
> > +++++++++++++++++++++++++++++++++
> > 2 files changed, 228 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-
> > exynos4/mach-smdkc210.c
> > index e645f7a..360a50a 100644
> > --- a/arch/arm/mach-exynos4/mach-smdkc210.c
> > +++ b/arch/arm/mach-exynos4/mach-smdkc210.c
> > @@ -9,26 +9,33 @@
> > */
> >
> > #include <linux/serial_core.h>
> > +#include <linux/delay.h>
> > #include <linux/gpio.h>
> > +#include <linux/lcd.h>
> > #include <linux/mmc/host.h>
> > #include <linux/platform_device.h>
> > #include <linux/smsc911x.h>
> > #include <linux/io.h>
> > #include <linux/i2c.h>
> > +#include <linux/clk.h>
> >
> > #include <asm/mach/arch.h>
> > #include <asm/mach-types.h>
> >
> > +#include <video/platform_lcd.h>
> > +
> > #include <plat/regs-serial.h>
> > #include <plat/regs-srom.h>
> > #include <plat/exynos4.h>
> > #include <plat/cpu.h>
> > #include <plat/devs.h>
> > +#include <plat/fb.h>
> > #include <plat/sdhci.h>
> > #include <plat/iic.h>
> > #include <plat/pd.h>
> >
> > #include <mach/map.h>
> > +#include <mach/regs-fb.h>
> >
> > /* Following are default values for UCON, ULCON and UFCON UART
> registers
> > */
> > #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
> > @@ -111,6 +118,69 @@ static struct s3c_sdhci_platdata
> smdkc210_hsmmc3_pdata
> > __initdata = {
> > .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
> > };
> >
> > +static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
> > + unsigned int power)
> > +{
> > + if (power) {
> > +#if !defined(CONFIG_BACKLIGHT_PWM)
> > + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> > + gpio_direction_output(EXYNOS4_GPD0(1), 1);
> > + gpio_free(EXYNOS4_GPD0(1));
> > +#endif
> > + /* fire nRESET on power up */
> > + gpio_request(EXYNOS4_GPX0(6), "GPX0");
> > +
> > + gpio_direction_output(EXYNOS4_GPX0(6), 1);
> > + mdelay(100);
> > +
> > + gpio_set_value(EXYNOS4_GPX0(6), 0);
> > + mdelay(10);
> > +
> > + gpio_set_value(EXYNOS4_GPX0(6), 1);
> > + mdelay(10);
> > +
> > + gpio_free(EXYNOS4_GPX0(6));
> > + } else {
> > +#if !defined(CONFIG_BACKLIGHT_PWM)
> > + gpio_request(EXYNOS4_GPD0(1), "GPD0");
> > + gpio_direction_output(EXYNOS4_GPD0(1), 0);
> > + gpio_free(EXYNOS4_GPD0(1));
> > +#endif
> > + }
> > +}
> > +
> > +static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
> > + .set_power = lcd_lte480wv_set_power,
> > +};
> > +
> > +static struct platform_device smdkc210_lcd_lte480wv = {
> > + .name = "platform-lcd",
> > + .dev.parent = &s5p_device_fimd0.dev,
> > + .dev.platform_data = &smdkc210_lcd_lte480wv_data,
> > +};
> > +
> > +static struct s3c_fb_pd_win smdkc210_fb_win0 = {
> > + .win_mode = {
> > + .left_margin = 13,
> > + .right_margin = 8,
> > + .upper_margin = 7,
> > + .lower_margin = 5,
> > + .hsync_len = 3,
> > + .vsync_len = 1,
> > + .xres = 800,
> > + .yres = 480,
> > + },
> > + .max_bpp = 32,
> > + .default_bpp = 24,
> > +};
> > +
> > +static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
> > + .win[0] = &smdkc210_fb_win0,
> > + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> > + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> > + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
> > +};
> > +
> > static struct resource smdkc210_smsc911x_resources[] = {
> > [0] = {
> > .start = EXYNOS4_PA_SROM_BANK(1),
> > @@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[]
> > __initdata = {
> > &exynos4_device_pd[PD_GPS],
> > &exynos4_device_sysmmu,
> > &samsung_asoc_dma,
> > + &s5p_device_fimd0,
> > + &smdkc210_lcd_lte480wv,
> > &smdkc210_smsc911x,
> > };
> >
> > @@ -191,6 +263,44 @@ static void __init smdkc210_smsc911x_init(void)
> > (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
> > }
> >
> > +static int __init smdkc210_fimd0_setup_clock(void)
> > +{
> > + struct clk *sclk = NULL;
> > + struct clk *mout_mpll = NULL;
> > +
> > + u32 rate = 0;
> > +
> > + sclk = clk_get(&s5p_device_fimd0.dev, "sclk_fimd");
> > + if (IS_ERR(sclk)) {
> > + printk(KERN_ERR "failed to get sclk for fimd\n");
> > + goto err_clk2;
> > + }
> > +
> > + mout_mpll = clk_get(NULL, "mout_mpll");
> > + if (IS_ERR(mout_mpll)) {
> > + printk(KERN_ERR "failed to get mout_mpll\n");
> > + goto err_clk1;
> > + }
> > +
> > + clk_set_parent(sclk, mout_mpll);
> > + if (!rate)
> > + rate = 134000000;
> > +
> > + clk_set_rate(sclk, rate);
> > +
> > + clk_put(sclk);
> > + clk_put(mout_mpll);
> > +
> > + return 0;
> > +
> > +err_clk1:
> > + clk_put(mout_mpll);
> > +err_clk2:
> > + clk_put(sclk);
> > +
> > + return -EINVAL;
> > +}
> > +
>
> I'm not sure if mach-smdk*.c is the right place for the above code.
> IMHO all the code that configures very low level, board specific
> parameters
> (like clocks and their relations) should be performed in boot loarder.
I agree with your suggestion.
I will remove the parent clock setting from the machine as fimc does.
I will send V7 patches, soon.
I really appreciate your review. Thank you.
>
> (snipped)
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2011-06-23 6:44 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-06-22 6:41 [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd Jingoo Han
2011-06-22 6:41 ` Jingoo Han
2011-06-22 8:56 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD Sylwester Nawrocki
2011-06-22 8:56 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd Sylwester Nawrocki
2011-06-22 9:47 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD Marek Szyprowski
2011-06-22 9:47 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd Marek Szyprowski
[not found] ` <BANLkTimPjo+WefApQLe=HKbYLCwmo_gGRw@mail.gmail.com>
2011-06-22 13:25 ` Anand Kumar N
2011-06-22 13:37 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD Anand Kumar N
2011-06-22 20:33 ` Sylwester Nawrocki
2011-06-22 20:33 ` [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd Sylwester Nawrocki
2011-06-23 1:09 JinGoo Han
2011-06-23 1:09 ` Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 JinGoo Han
2011-06-23 6:44 RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd JinGoo Han
2011-06-23 6:44 ` RE: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 JinGoo Han
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