[PATCH/RFC 0/2] Couple of Tegra2 PCIe fixes(?)

[PATCH/RFC 0/2] Couple of Tegra2 PCIe fixes(?)

[Dmitry Artamonow]

These are more of RFC, because I can't test if 1/2 is really fixes anything,
and not sure how much 2/2 is needed - maybe error it fixes happens just in
my setup (and also I'm not sure if 2 seconds is a good value for timeout,
because I have no idea, how much time it takes for PLL to lock when everything)
But anyway...

While trying to make PCIe work on Harmony board, I've noticed
that pinmux groups for PCIe related signals are tristated, which 
looked suspicious. So I fixed that - that's the patch 1/2.

Sadly, even with this fix and 3.3v regulator patch[1] applied, PCIe still
doesn't work for me. Usually driver just loops infinitely in PLL lock
waiting code (that was the reason for writing patch 2/2 in this
mini-series). Couple of times I observed that after about 20-30 seconds of
waiting it passed PLL lock test and continue further, but then it failed to
detect a link with PCIe card. And I can't even reproduce this anymore.

Does anyone have working PCIe on Harmony? Can you please share the details
of your setup - what bootloader are you using, which version of kernel,
some additional patches maybe? Is there some secret tricks which are needed?
I've tried several combinations of different kernels and bootloaders, but
still can't find even a one which works.

[1] http://www.spinics.net/lists/linux-tegra/msg04148.html

Dmitry Artamonow (2):
  arm/tegra: fix harmony pinmux for PCIe
  arm/tegra: add timeout to PCIe PLL lock detection loop

 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 arch/arm/mach-tegra/pcie.c                 |   14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

-- 
1.7.5.1.300.gc565c

[PATCH/RFC 0/2] Couple of Tegra2 PCIe fixes(?)

[Dmitry Artamonow]

These are more of RFC, because I can't test if 1/2 is really fixes anything,
and not sure how much 2/2 is needed - maybe error it fixes happens just in
my setup (and also I'm not sure if 2 seconds is a good value for timeout,
because I have no idea, how much time it takes for PLL to lock when everything)
But anyway...

While trying to make PCIe work on Harmony board, I've noticed
that pinmux groups for PCIe related signals are tristated, which 
looked suspicious. So I fixed that - that's the patch 1/2.

Sadly, even with this fix and 3.3v regulator patch[1] applied, PCIe still
doesn't work for me. Usually driver just loops infinitely in PLL lock
waiting code (that was the reason for writing patch 2/2 in this
mini-series). Couple of times I observed that after about 20-30 seconds of
waiting it passed PLL lock test and continue further, but then it failed to
detect a link with PCIe card. And I can't even reproduce this anymore.

Does anyone have working PCIe on Harmony? Can you please share the details
of your setup - what bootloader are you using, which version of kernel,
some additional patches maybe? Is there some secret tricks which are needed?
I've tried several combinations of different kernels and bootloaders, but
still can't find even a one which works.

[1] http://www.spinics.net/lists/linux-tegra/msg04148.html

Dmitry Artamonow (2):
  arm/tegra: fix harmony pinmux for PCIe
  arm/tegra: add timeout to PCIe PLL lock detection loop

 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 arch/arm/mach-tegra/pcie.c                 |   14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

-- 
1.7.5.1.300.gc565c

[PATCH/RFC 0/2] Couple of Tegra2 PCIe fixes(?)

[Dmitry Artamonow]

These are more of RFC, because I can't test if 1/2 is really fixes anything,
and not sure how much 2/2 is needed - maybe error it fixes happens just in
my setup (and also I'm not sure if 2 seconds is a good value for timeout,
because I have no idea, how much time it takes for PLL to lock when everything)
But anyway...

While trying to make PCIe work on Harmony board, I've noticed
that pinmux groups for PCIe related signals are tristated, which 
looked suspicious. So I fixed that - that's the patch 1/2.

Sadly, even with this fix and 3.3v regulator patch[1] applied, PCIe still
doesn't work for me. Usually driver just loops infinitely in PLL lock
waiting code (that was the reason for writing patch 2/2 in this
mini-series). Couple of times I observed that after about 20-30 seconds of
waiting it passed PLL lock test and continue further, but then it failed to
detect a link with PCIe card. And I can't even reproduce this anymore.

Does anyone have working PCIe on Harmony? Can you please share the details
of your setup - what bootloader are you using, which version of kernel,
some additional patches maybe? Is there some secret tricks which are needed?
I've tried several combinations of different kernels and bootloaders, but
still can't find even a one which works.

[1] http://www.spinics.net/lists/linux-tegra/msg04148.html

Dmitry Artamonow (2):
  arm/tegra: fix harmony pinmux for PCIe
  arm/tegra: add timeout to PCIe PLL lock detection loop

 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 arch/arm/mach-tegra/pcie.c                 |   14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

-- 
1.7.5.1.300.gc565c

[PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Dmitry Artamonow]

Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
removed runtime tri-state toggling for PCIe related pinmux groups,
but it seems that the fact that all of them are tri-state by default
has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..1af85bccc 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-- 
1.7.5.1.300.gc565c

[PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Dmitry Artamonow]

Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
removed runtime tri-state toggling for PCIe related pinmux groups,
but it seems that the fact that all of them are tri-state by default
has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..1af85bccc 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-- 
1.7.5.1.300.gc565c

[PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Dmitry Artamonow]

Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
removed runtime tri-state toggling for PCIe related pinmux groups,
but it seems that the fact that all of them are tri-state by default
has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..1af85bccc 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-- 
1.7.5.1.300.gc565c

Re: [PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
> removed runtime tri-state toggling for PCIe related pinmux groups,
> but it seems that the fact that all of them are tri-state by default
> has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

Crap, why didn't I check that? Anyway,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

[PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
> removed runtime tri-state toggling for PCIe related pinmux groups,
> but it seems that the fact that all of them are tri-state by default
> has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

Crap, why didn't I check that? Anyway,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Re: [PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
> removed runtime tri-state toggling for PCIe related pinmux groups,
> but it seems that the fact that all of them are tri-state by default
> has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

Crap, why didn't I check that? Anyway,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (as PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..ffdfdd4 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		mdelay(1);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (as PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..ffdfdd4 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		mdelay(1);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (as PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..ffdfdd4 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		mdelay(1);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Andi]

Hi,

On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org> wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
>
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
>
> Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
> ---
>  arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
>  1 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> index 14b29ab..ffdfdd4 100644
> --- a/arch/arm/mach-tegra/pcie.c
> +++ b/arch/arm/mach-tegra/pcie.c
> @@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
>        afi_writel(0, AFI_MSI_BAR_SZ);
>  }
>
> -static void tegra_pcie_enable_controller(void)
> +static int tegra_pcie_enable_controller(void)
>  {
>        u32 val, reg;
> -       int i;
> +       int i, timeout;
>
>        /* Enable slot clock and pulse the reset signals */
>        for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>        pads_writel(0xfa5cfa5c, 0xc8);
>
>        /* Wait for the PLL to lock */
> +       timeout = 2000;
>        do {
>                val = pads_readl(PADS_PLL_CTL);
> +               mdelay(1);

why are you using an mdelay? If you need to sleep 1ms just use
usleep_range or similar

Andi

> +               if (--timeout == 0) {
> +                       pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +                       return -EBUSY;
> +               }
>        } while (!(val & PADS_PLL_CTL_LOCKDET));
>
>        /* turn off IDDQ override */
> @@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
>        if (err)
>                return err;
>
> -       tegra_pcie_enable_controller();
> +       err = tegra_pcie_enable_controller();
> +       if (err)
> +               return err;
>
>        /* setup the AFI address translations */
>        tegra_pcie_setup_translations();
> --
> 1.7.5.1.300.gc565c
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Andi]

Hi,

On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
>
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
>
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> ---
> ?arch/arm/mach-tegra/pcie.c | ? 14 +++++++++++---
> ?1 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> index 14b29ab..ffdfdd4 100644
> --- a/arch/arm/mach-tegra/pcie.c
> +++ b/arch/arm/mach-tegra/pcie.c
> @@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
> ? ? ? ?afi_writel(0, AFI_MSI_BAR_SZ);
> ?}
>
> -static void tegra_pcie_enable_controller(void)
> +static int tegra_pcie_enable_controller(void)
> ?{
> ? ? ? ?u32 val, reg;
> - ? ? ? int i;
> + ? ? ? int i, timeout;
>
> ? ? ? ?/* Enable slot clock and pulse the reset signals */
> ? ? ? ?for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
> ? ? ? ?pads_writel(0xfa5cfa5c, 0xc8);
>
> ? ? ? ?/* Wait for the PLL to lock */
> + ? ? ? timeout = 2000;
> ? ? ? ?do {
> ? ? ? ? ? ? ? ?val = pads_readl(PADS_PLL_CTL);
> + ? ? ? ? ? ? ? mdelay(1);

why are you using an mdelay? If you need to sleep 1ms just use
usleep_range or similar

Andi

> + ? ? ? ? ? ? ? if (--timeout == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> + ? ? ? ? ? ? ? ? ? ? ? return -EBUSY;
> + ? ? ? ? ? ? ? }
> ? ? ? ?} while (!(val & PADS_PLL_CTL_LOCKDET));
>
> ? ? ? ?/* turn off IDDQ override */
> @@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
> ? ? ? ?if (err)
> ? ? ? ? ? ? ? ?return err;
>
> - ? ? ? tegra_pcie_enable_controller();
> + ? ? ? err = tegra_pcie_enable_controller();
> + ? ? ? if (err)
> + ? ? ? ? ? ? ? return err;
>
> ? ? ? ?/* setup the AFI address translations */
> ? ? ? ?tegra_pcie_setup_translations();
> --
> 1.7.5.1.300.gc565c
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Andi]

Hi,

On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
>
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
>
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> ---
>  arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
>  1 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> index 14b29ab..ffdfdd4 100644
> --- a/arch/arm/mach-tegra/pcie.c
> +++ b/arch/arm/mach-tegra/pcie.c
> @@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
>        afi_writel(0, AFI_MSI_BAR_SZ);
>  }
>
> -static void tegra_pcie_enable_controller(void)
> +static int tegra_pcie_enable_controller(void)
>  {
>        u32 val, reg;
> -       int i;
> +       int i, timeout;
>
>        /* Enable slot clock and pulse the reset signals */
>        for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>        pads_writel(0xfa5cfa5c, 0xc8);
>
>        /* Wait for the PLL to lock */
> +       timeout = 2000;
>        do {
>                val = pads_readl(PADS_PLL_CTL);
> +               mdelay(1);

why are you using an mdelay? If you need to sleep 1ms just use
usleep_range or similar

Andi

> +               if (--timeout == 0) {
> +                       pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +                       return -EBUSY;
> +               }
>        } while (!(val & PADS_PLL_CTL_LOCKDET));
>
>        /* turn off IDDQ override */
> @@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
>        if (err)
>                return err;
>
> -       tegra_pcie_enable_controller();
> +       err = tegra_pcie_enable_controller();
> +       if (err)
> +               return err;
>
>        /* setup the AFI address translations */
>        tegra_pcie_setup_translations();
> --
> 1.7.5.1.300.gc565c
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 10:38 Tue 06 Mar     , Andi wrote:
> Hi,
> 
> On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org> wrote:
> >        /* Wait for the PLL to lock */
> > +       timeout = 2000;
> >        do {
> >                val = pads_readl(PADS_PLL_CTL);
> > +               mdelay(1);
> 
> why are you using an mdelay? If you need to sleep 1ms just use
> usleep_range or similar

This driver uses mdelay(1) in other places, so I just used it for the sake
of consistency. And as this code runs just one time on boot, there's not
really much harm in doing delay with busy loop instead of sleeping.

Anyway, I agree that sleeping is better than busy waiting in general, so
I can respin this patch using usleep_range, or else prepare incremental
patch on top of this, which will change all mdelay in driver to usleep_range.

-- 
Best regards,
Dmitry "MAD" Artamonow

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 10:38 Tue 06 Mar     , Andi wrote:
> Hi,
> 
> On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> > ? ? ? ?/* Wait for the PLL to lock */
> > + ? ? ? timeout = 2000;
> > ? ? ? ?do {
> > ? ? ? ? ? ? ? ?val = pads_readl(PADS_PLL_CTL);
> > + ? ? ? ? ? ? ? mdelay(1);
> 
> why are you using an mdelay? If you need to sleep 1ms just use
> usleep_range or similar

This driver uses mdelay(1) in other places, so I just used it for the sake
of consistency. And as this code runs just one time on boot, there's not
really much harm in doing delay with busy loop instead of sleeping.

Anyway, I agree that sleeping is better than busy waiting in general, so
I can respin this patch using usleep_range, or else prepare incremental
patch on top of this, which will change all mdelay in driver to usleep_range.

-- 
Best regards,
Dmitry "MAD" Artamonow

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 10:38 Tue 06 Mar     , Andi wrote:
> Hi,
> 
> On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> >        /* Wait for the PLL to lock */
> > +       timeout = 2000;
> >        do {
> >                val = pads_readl(PADS_PLL_CTL);
> > +               mdelay(1);
> 
> why are you using an mdelay? If you need to sleep 1ms just use
> usleep_range or similar

This driver uses mdelay(1) in other places, so I just used it for the sake
of consistency. And as this code runs just one time on boot, there's not
really much harm in doing delay with busy loop instead of sleeping.

Anyway, I agree that sleeping is better than busy waiting in general, so
I can respin this patch using usleep_range, or else prepare incremental
patch on top of this, which will change all mdelay in driver to usleep_range.

-- 
Best regards,
Dmitry "MAD" Artamonow

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 354 bytes --]

* Dmitry Artamonow wrote:
[...]
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
[...]
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>  	pads_writel(0xfa5cfa5c, 0xc8);
>  
>  	/* Wait for the PLL to lock */
> +	timeout = 2000;

FWIW, the Vibrante kernel uses 300 for the timeout value.

Thierry

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[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

* Dmitry Artamonow wrote:
[...]
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
[...]
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>  	pads_writel(0xfa5cfa5c, 0xc8);
>  
>  	/* Wait for the PLL to lock */
> +	timeout = 2000;

FWIW, the Vibrante kernel uses 300 for the timeout value.

Thierry
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Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 354 bytes --]

* Dmitry Artamonow wrote:
[...]
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
[...]
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>  	pads_writel(0xfa5cfa5c, 0xc8);
>  
>  	/* Wait for the PLL to lock */
> +	timeout = 2000;

FWIW, the Vibrante kernel uses 300 for the timeout value.

Thierry

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Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

That seems reasonable. So once the mdelay discussion is resolved,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Any idea why the PLL doesn't lock sometimes?

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

That seems reasonable. So once the mdelay discussion is resolved,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Any idea why the PLL doesn't lock sometimes?

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

That seems reasonable. So once the mdelay discussion is resolved,

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Any idea why the PLL doesn't lock sometimes?

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 797 bytes --]

* Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
> 
> Any idea why the PLL doesn't lock sometimes?

I've seen this happen when the 1.05V regulator (GPIO#2 of the PMU on Harmony)
isn't enabled.

Thierry

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[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

* Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?

I've seen this happen when the 1.05V regulator (GPIO#2 of the PMU on Harmony)
isn't enabled.

Thierry
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Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 751 bytes --]

* Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?

I've seen this happen when the 1.05V regulator (GPIO#2 of the PMU on Harmony)
isn't enabled.

Thierry

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Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 09:58 Tue 06 Mar     , Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
> 
> Any idea why the PLL doesn't lock sometimes?


Please dismiss this patch - I forgot to turn 'return' to 'return 0' at
the end of the function, while converting it's type from void to int,
and it causes driver to fail always now. I'll send updated version shortly.

Also I've managed to get another Harmony board today, and it doesn't have
problems with PLL locking (PLL locks on it in about 2ms), so probably the
issue I've seen is caused by some hardware fault on the first board,
or is specific to some particular revision of the board and/or Tegra2 chip.

I'll do more testing tomorrow and re-spin the patches.
-- 
Best regards,
Dmitry "MAD" Artamonow

[PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 09:58 Tue 06 Mar     , Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?


Please dismiss this patch - I forgot to turn 'return' to 'return 0' at
the end of the function, while converting it's type from void to int,
and it causes driver to fail always now. I'll send updated version shortly.

Also I've managed to get another Harmony board today, and it doesn't have
problems with PLL locking (PLL locks on it in about 2ms), so probably the
issue I've seen is caused by some hardware fault on the first board,
or is specific to some particular revision of the board and/or Tegra2 chip.

I'll do more testing tomorrow and re-spin the patches.
-- 
Best regards,
Dmitry "MAD" Artamonow

Re: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 09:58 Tue 06 Mar     , Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?


Please dismiss this patch - I forgot to turn 'return' to 'return 0' at
the end of the function, while converting it's type from void to int,
and it causes driver to fail always now. I'll send updated version shortly.

Also I've managed to get another Harmony board today, and it doesn't have
problems with PLL locking (PLL locks on it in about 2ms), so probably the
issue I've seen is caused by some hardware fault on the first board,
or is specific to some particular revision of the board and/or Tegra2 chip.

I'll do more testing tomorrow and re-spin the patches.
-- 
Best regards,
Dmitry "MAD" Artamonow

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
---
Changes v1 -> v2:
* msleep is changed to usleep_range
* function now returns 0 on success instead of undefined value

 arch/arm/mach-tegra/pcie.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..90f85eb 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		usleep_range(1000, 1000);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
Changes v1 -> v2:
* msleep is changed to usleep_range
* function now returns 0 on success instead of undefined value

 arch/arm/mach-tegra/pcie.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..90f85eb 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		usleep_range(1000, 1000);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
Changes v1 -> v2:
* msleep is changed to usleep_range
* function now returns 0 on success instead of undefined value

 arch/arm/mach-tegra/pcie.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..90f85eb 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		usleep_range(1000, 1000);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/09/2012 03:09 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>

> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c

>  	/* Wait for the PLL to lock */
> +	timeout = 2000;
>  	do {
>  		val = pads_readl(PADS_PLL_CTL);
> +		usleep_range(1000, 1000);
> +		if (--timeout == 0) {
> +			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +			return -EBUSY;
> +		}
>  	} while (!(val & PADS_PLL_CTL_LOCKDET));

Thierry pointed out that one of NVIDIA's downstream kernels uses a
timeout of 300 here, rather than 2000 above. Do you see a specific need
for this timeout for be 2000 rather than 300? It might be nice to be
consistent.

Olof, I notice you've already applied V1 of this, which has the return
statement issue. Can you replace it with this, or should Dmitry send an
incremental patch?

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/09/2012 03:09 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c

>  	/* Wait for the PLL to lock */
> +	timeout = 2000;
>  	do {
>  		val = pads_readl(PADS_PLL_CTL);
> +		usleep_range(1000, 1000);
> +		if (--timeout == 0) {
> +			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +			return -EBUSY;
> +		}
>  	} while (!(val & PADS_PLL_CTL_LOCKDET));

Thierry pointed out that one of NVIDIA's downstream kernels uses a
timeout of 300 here, rather than 2000 above. Do you see a specific need
for this timeout for be 2000 rather than 300? It might be nice to be
consistent.

Olof, I notice you've already applied V1 of this, which has the return
statement issue. Can you replace it with this, or should Dmitry send an
incremental patch?

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Stephen Warren]

On 03/09/2012 03:09 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c

>  	/* Wait for the PLL to lock */
> +	timeout = 2000;
>  	do {
>  		val = pads_readl(PADS_PLL_CTL);
> +		usleep_range(1000, 1000);
> +		if (--timeout == 0) {
> +			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +			return -EBUSY;
> +		}
>  	} while (!(val & PADS_PLL_CTL_LOCKDET));

Thierry pointed out that one of NVIDIA's downstream kernels uses a
timeout of 300 here, rather than 2000 above. Do you see a specific need
for this timeout for be 2000 rather than 300? It might be nice to be
consistent.

Olof, I notice you've already applied V1 of this, which has the return
statement issue. Can you replace it with this, or should Dmitry send an
incremental patch?

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 12:09 Mon 12 Mar     , Stephen Warren wrote:
> Thierry pointed out that one of NVIDIA's downstream kernels uses a
> timeout of 300 here, rather than 2000 above. Do you see a specific need
> for this timeout for be 2000 rather than 300? It might be nice to be
> consistent.
No, there's no specific need for it to be 2000 - it may as well be 300.
I just wanted to stay on the safe side, but I think 300 should be still
more than enough time for PLL to lock.

> 
> Olof, I notice you've already applied V1 of this, which has the return
> statement issue. Can you replace it with this, or should Dmitry send an
> incremental patch?

Yes, V1 breaks more things than it fixes, so it would be nice if
it can be replaced with fixed version (I hope it's not too late yet).
BTW, regarding timeout discussion above - should I resend patch with
adjusted timeout, or can you change it while applying? (of course,
if we settle on incremental patch, I'll roll this change in)

-- 
Best regards,
Dmitry "MAD" Artamonow

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 12:09 Mon 12 Mar     , Stephen Warren wrote:
> Thierry pointed out that one of NVIDIA's downstream kernels uses a
> timeout of 300 here, rather than 2000 above. Do you see a specific need
> for this timeout for be 2000 rather than 300? It might be nice to be
> consistent.
No, there's no specific need for it to be 2000 - it may as well be 300.
I just wanted to stay on the safe side, but I think 300 should be still
more than enough time for PLL to lock.

> 
> Olof, I notice you've already applied V1 of this, which has the return
> statement issue. Can you replace it with this, or should Dmitry send an
> incremental patch?

Yes, V1 breaks more things than it fixes, so it would be nice if
it can be replaced with fixed version (I hope it's not too late yet).
BTW, regarding timeout discussion above - should I resend patch with
adjusted timeout, or can you change it while applying? (of course,
if we settle on incremental patch, I'll roll this change in)

-- 
Best regards,
Dmitry "MAD" Artamonow

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Dmitry Artamonow]

On 12:09 Mon 12 Mar     , Stephen Warren wrote:
> Thierry pointed out that one of NVIDIA's downstream kernels uses a
> timeout of 300 here, rather than 2000 above. Do you see a specific need
> for this timeout for be 2000 rather than 300? It might be nice to be
> consistent.
No, there's no specific need for it to be 2000 - it may as well be 300.
I just wanted to stay on the safe side, but I think 300 should be still
more than enough time for PLL to lock.

> 
> Olof, I notice you've already applied V1 of this, which has the return
> statement issue. Can you replace it with this, or should Dmitry send an
> incremental patch?

Yes, V1 breaks more things than it fixes, so it would be nice if
it can be replaced with fixed version (I hope it's not too late yet).
BTW, regarding timeout discussion above - should I resend patch with
adjusted timeout, or can you change it while applying? (of course,
if we settle on incremental patch, I'll roll this change in)

-- 
Best regards,
Dmitry "MAD" Artamonow

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Olof Johansson]

On Mon, Mar 12, 2012 at 12:30 PM, Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org> wrote:
> On 12:09 Mon 12 Mar     , Stephen Warren wrote:
>> Thierry pointed out that one of NVIDIA's downstream kernels uses a
>> timeout of 300 here, rather than 2000 above. Do you see a specific need
>> for this timeout for be 2000 rather than 300? It might be nice to be
>> consistent.
> No, there's no specific need for it to be 2000 - it may as well be 300.
> I just wanted to stay on the safe side, but I think 300 should be still
> more than enough time for PLL to lock.
>
>>
>> Olof, I notice you've already applied V1 of this, which has the return
>> statement issue. Can you replace it with this, or should Dmitry send an
>> incremental patch?
>
> Yes, V1 breaks more things than it fixes, so it would be nice if
> it can be replaced with fixed version (I hope it's not too late yet).
> BTW, regarding timeout discussion above - should I resend patch with
> adjusted timeout, or can you change it while applying? (of course,
> if we settle on incremental patch, I'll roll this change in)

Please send an incremental patch which also solves the above question. :)


-Olof

[PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Olof Johansson]

On Mon, Mar 12, 2012 at 12:30 PM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> On 12:09 Mon 12 Mar ? ? , Stephen Warren wrote:
>> Thierry pointed out that one of NVIDIA's downstream kernels uses a
>> timeout of 300 here, rather than 2000 above. Do you see a specific need
>> for this timeout for be 2000 rather than 300? It might be nice to be
>> consistent.
> No, there's no specific need for it to be 2000 - it may as well be 300.
> I just wanted to stay on the safe side, but I think 300 should be still
> more than enough time for PLL to lock.
>
>>
>> Olof, I notice you've already applied V1 of this, which has the return
>> statement issue. Can you replace it with this, or should Dmitry send an
>> incremental patch?
>
> Yes, V1 breaks more things than it fixes, so it would be nice if
> it can be replaced with fixed version (I hope it's not too late yet).
> BTW, regarding timeout discussion above - should I resend patch with
> adjusted timeout, or can you change it while applying? (of course,
> if we settle on incremental patch, I'll roll this change in)

Please send an incremental patch which also solves the above question. :)


-Olof

Re: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop

[Olof Johansson]

On Mon, Mar 12, 2012 at 12:30 PM, Dmitry Artamonow <mad_soft@inbox.ru> wrote:
> On 12:09 Mon 12 Mar     , Stephen Warren wrote:
>> Thierry pointed out that one of NVIDIA's downstream kernels uses a
>> timeout of 300 here, rather than 2000 above. Do you see a specific need
>> for this timeout for be 2000 rather than 300? It might be nice to be
>> consistent.
> No, there's no specific need for it to be 2000 - it may as well be 300.
> I just wanted to stay on the safe side, but I think 300 should be still
> more than enough time for PLL to lock.
>
>>
>> Olof, I notice you've already applied V1 of this, which has the return
>> statement issue. Can you replace it with this, or should Dmitry send an
>> incremental patch?
>
> Yes, V1 breaks more things than it fixes, so it would be nice if
> it can be replaced with fixed version (I hope it's not too late yet).
> BTW, regarding timeout discussion above - should I resend patch with
> adjusted timeout, or can you change it while applying? (of course,
> if we settle on incremental patch, I'll roll this change in)

Please send an incremental patch which also solves the above question. :)


-Olof

[PATCH] arm/tegra: pcie: fix return value of function

[Dmitry Artamonow]

In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
tegra_pcie_enable_controller() function type has been changed from
void to int, but the last return statement wasn't converted, so
function returns undefined value. Fix it.

Also while at it, address couple of minor concerns raised by reviewers:
use usleep_range for delay, and lower the value of timeout to 300ms
to be consistent with Nvidia Vibrante kernel.

Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
---
 arch/arm/mach-tegra/pcie.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7313059..54a816f 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -639,10 +639,10 @@ static int tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
-	timeout = 2000;
+	timeout = 300;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
-		mdelay(1);
+		usleep_range(1000, 1000);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
 			return -EBUSY;
@@ -677,7 +677,7 @@ static int tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
-- 
1.7.5.1.300.gc565c

[PATCH] arm/tegra: pcie: fix return value of function

[Dmitry Artamonow]

In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
tegra_pcie_enable_controller() function type has been changed from
void to int, but the last return statement wasn't converted, so
function returns undefined value. Fix it.

Also while at it, address couple of minor concerns raised by reviewers:
use usleep_range for delay, and lower the value of timeout to 300ms
to be consistent with Nvidia Vibrante kernel.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7313059..54a816f 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -639,10 +639,10 @@ static int tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
-	timeout = 2000;
+	timeout = 300;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
-		mdelay(1);
+		usleep_range(1000, 1000);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
 			return -EBUSY;
@@ -677,7 +677,7 @@ static int tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
-- 
1.7.5.1.300.gc565c

[PATCH] arm/tegra: pcie: fix return value of function

[Dmitry Artamonow]

In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
tegra_pcie_enable_controller() function type has been changed from
void to int, but the last return statement wasn't converted, so
function returns undefined value. Fix it.

Also while at it, address couple of minor concerns raised by reviewers:
use usleep_range for delay, and lower the value of timeout to 300ms
to be consistent with Nvidia Vibrante kernel.

Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7313059..54a816f 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -639,10 +639,10 @@ static int tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
-	timeout = 2000;
+	timeout = 300;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
-		mdelay(1);
+		usleep_range(1000, 1000);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
 			return -EBUSY;
@@ -677,7 +677,7 @@ static int tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
-- 
1.7.5.1.300.gc565c

Re: [PATCH] arm/tegra: pcie: fix return value of function

[Stephen Warren]

On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> tegra_pcie_enable_controller() function type has been changed from
> void to int, but the last return statement wasn't converted, so
> function returns undefined value. Fix it.
> 
> Also while at it, address couple of minor concerns raised by reviewers:
> use usleep_range for delay, and lower the value of timeout to 300ms
> to be consistent with Nvidia Vibrante kernel.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>

Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>

[PATCH] arm/tegra: pcie: fix return value of function

[Stephen Warren]

On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> tegra_pcie_enable_controller() function type has been changed from
> void to int, but the last return statement wasn't converted, so
> function returns undefined value. Fix it.
> 
> Also while at it, address couple of minor concerns raised by reviewers:
> use usleep_range for delay, and lower the value of timeout to 300ms
> to be consistent with Nvidia Vibrante kernel.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Re: [PATCH] arm/tegra: pcie: fix return value of function

[Stephen Warren]

On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> tegra_pcie_enable_controller() function type has been changed from
> void to int, but the last return statement wasn't converted, so
> function returns undefined value. Fix it.
> 
> Also while at it, address couple of minor concerns raised by reviewers:
> use usleep_range for delay, and lower the value of timeout to 300ms
> to be consistent with Nvidia Vibrante kernel.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Re: [PATCH] arm/tegra: pcie: fix return value of function

[Olof Johansson]

On Tue, Mar 13, 2012 at 01:36:27PM -0600, Stephen Warren wrote:
> On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> > In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> > tegra_pcie_enable_controller() function type has been changed from
> > void to int, but the last return statement wasn't converted, so
> > function returns undefined value. Fix it.
> > 
> > Also while at it, address couple of minor concerns raised by reviewers:
> > use usleep_range for delay, and lower the value of timeout to 300ms
> > to be consistent with Nvidia Vibrante kernel.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft-aPYA7nAdAYY@public.gmane.org>
> 
> Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>

Thanks, applied to for-3.4/cleanups-and-fixes


-Olof

[PATCH] arm/tegra: pcie: fix return value of function

[Olof Johansson]

On Tue, Mar 13, 2012 at 01:36:27PM -0600, Stephen Warren wrote:
> On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> > In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> > tegra_pcie_enable_controller() function type has been changed from
> > void to int, but the last return statement wasn't converted, so
> > function returns undefined value. Fix it.
> > 
> > Also while at it, address couple of minor concerns raised by reviewers:
> > use usleep_range for delay, and lower the value of timeout to 300ms
> > to be consistent with Nvidia Vibrante kernel.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Thanks, applied to for-3.4/cleanups-and-fixes


-Olof

Re: [PATCH] arm/tegra: pcie: fix return value of function

[Olof Johansson]

On Tue, Mar 13, 2012 at 01:36:27PM -0600, Stephen Warren wrote:
> On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> > In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> > tegra_pcie_enable_controller() function type has been changed from
> > void to int, but the last return statement wasn't converted, so
> > function returns undefined value. Fix it.
> > 
> > Also while at it, address couple of minor concerns raised by reviewers:
> > use usleep_range for delay, and lower the value of timeout to 300ms
> > to be consistent with Nvidia Vibrante kernel.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru>
> 
> Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Thanks, applied to for-3.4/cleanups-and-fixes


-Olof