* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
The series adds minimal OMAP5 support.
OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
hence large part of the peripherals are re-used.
OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.
Series is generated against the 3.4-rc5. This has been rebased on
top of the OMAP2+ cleanup series [1]
To get the boot working with omap2plus_defconfig,
OMAP5 hwmod/clock/prm/cm database needs to be added.
The data and the integrated tree are available in the
below git repository
OMAP5_DATA:
git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
omap5_data
OMAP5_INTEGRATED:
git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
omap5_dt_integrated
The series is boot tested on OMAP5430 ES1.0.
OMAP2/3/4 build and boot is tested as well to avoid any breakage
because of the series.
Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
can be dropped once rebased against [2]
Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
temporary and can be dropped once rebased against [3]
[1] http://www.spinics.net/lists/linux-omap/msg69233.html
[2] http://www.spinics.net/lists/linux-omap/msg69013.html
[3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
R Sricharan (10):
ARM: OMAP5: id: Add cpu id for ES versions
ARM: OMAP5: Add minimal support for OMAP5430 SOC
TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks.
ARM: OMAP5: timer: Add clocksource, clockevent support
TEMP: ARM: OMAP5: Update the base address of the 32k-counter.
ARM: OMAP5: gpmc: Update gpmc_init()
ARM: OMAP5: l3: Add l3 error handler support for omap5.
ARM: OMAP5: board-generic: Add device tree support.
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: Add the build support
Santosh Shilimkar (2):
ARM: OMAP5: Add the WakeupGen IP updates.
ARM: OMAP5: Add SMP support.
Tarun Kanti DebBarma (1):
ARM: Kconfig update to support additional GPIOs in OMAP5
.../devicetree/bindings/arm/omap/omap.txt | 3 +
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/omap5-evm.dts | 20 ++
arch/arm/boot/dts/omap5.dtsi | 201 ++++++++++++++++++++
arch/arm/configs/omap2plus_defconfig | 2 +
arch/arm/mach-omap2/Kconfig | 13 ++-
arch/arm/mach-omap2/Makefile | 27 ++-
arch/arm/mach-omap2/board-generic.c | 39 +++--
arch/arm/mach-omap2/clock.c | 3 +-
arch/arm/mach-omap2/cminst44xx.h | 2 +-
arch/arm/mach-omap2/common.c | 24 +++
arch/arm/mach-omap2/common.h | 15 ++
arch/arm/mach-omap2/control.h | 4 +
arch/arm/mach-omap2/devices.c | 2 +-
arch/arm/mach-omap2/gpmc.c | 3 +-
arch/arm/mach-omap2/id.c | 47 +++++
arch/arm/mach-omap2/include/mach/debug-macro.S | 8 +-
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
arch/arm/mach-omap2/io.c | 44 +++++
arch/arm/mach-omap2/iomap.h | 27 +++
arch/arm/mach-omap2/irq.c | 11 +
arch/arm/mach-omap2/omap-headsmp.S | 21 ++
arch/arm/mach-omap2/omap-hotplug.c | 24 ++-
arch/arm/mach-omap2/omap-smp.c | 58 +++++--
arch/arm/mach-omap2/omap-wakeupgen.c | 110 ++++++++---
arch/arm/mach-omap2/omap4-common.c | 14 ++
arch/arm/mach-omap2/omap4-sar-layout.h | 12 +-
arch/arm/mach-omap2/omap_hwmod.c | 15 +-
arch/arm/mach-omap2/omap_l3_noc.h | 22 ++-
arch/arm/mach-omap2/prcm.c | 2 +-
arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 +-
arch/arm/mach-omap2/timer.c | 5 +
arch/arm/plat-omap/Kconfig | 4 +-
arch/arm/plat-omap/Makefile | 4 +-
arch/arm/plat-omap/counter_32k.c | 2 +
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 4 +-
arch/arm/plat-omap/include/plat/cpu.h | 23 ++-
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/multi.h | 9 +
arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++
arch/arm/plat-omap/include/plat/serial.h | 10 +
arch/arm/plat-omap/include/plat/uncompress.h | 6 +
arch/arm/plat-omap/sram.c | 11 +-
44 files changed, 796 insertions(+), 101 deletions(-)
create mode 100644 arch/arm/boot/dts/omap5-evm.dts
create mode 100644 arch/arm/boot/dts/omap5.dtsi
create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
detection support.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/control.h | 4 +++
arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
3 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd0..9daac6f 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -246,6 +246,10 @@
/* TI81XX CONTROL_DEVCONF register offsets */
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS 0x134
+#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0e79b7b..d2ec323 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -50,6 +50,11 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+ } else if (cpu_is_omap54xx()) {
+ val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+ val &= OMAP5_DEVICETYPE_MASK;
+ val >>= 6;
+ goto out;
} else {
pr_err("Cannot detect omap type!\n");
goto out;
@@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
+void __init omap5xxx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xb942:
+ switch (rev) {
+ case 0:
+ omap_revision = OMAP5430_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = OMAP5430_REV_ES2_0;
+ break;
+ default:
+ omap_revision = OMAP5430_REV_ES1_0;
+ }
+ break;
+
+ case 0xb998:
+ switch (rev) {
+ case 0:
+ omap_revision = OMAP5432_REV_ES1_0;
+ break;
+ default:
+ omap_revision = OMAP5432_REV_ES1_0;
+ }
+ break;
+
+ default:
+ /* Unknown default to latest silicon rev as default*/
+ omap_revision = OMAP5430_REV_ES2_0;
+ }
+
+ pr_info("OMAP%04x ES%d.0\n",
+ omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index dc6a86b..5e57732 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
- * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
+ * cpu_is_omap543x(): True for OMAP5430, OMAP5432
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@@ -121,6 +122,7 @@ IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
+IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
@@ -132,6 +134,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
@@ -154,6 +157,8 @@ IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
+#define cpu_is_omap54xx() 0
+#define cpu_is_omap543x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
@@ -299,6 +304,7 @@ IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap3517() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap3630() 0
+#define cpu_is_omap5430() 0
/*
* Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -393,11 +399,18 @@ IS_OMAP_TYPE(3517, 0x3517)
# define cpu_is_omap447x() is_omap447x()
# endif
+# if defined(CONFIG_ARCH_OMAP5)
+# undef cpu_is_omap54xx
+# undef cpu_is_omap543x
+# define cpu_is_omap54xx() is_omap54xx()
+# define cpu_is_omap543x() is_omap543x()
+#endif
+
/* Macros to detect if we have OMAP1 or OMAP2 */
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
cpu_is_omap16xx())
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
- cpu_is_omap44xx())
+ cpu_is_omap44xx() || cpu_is_omap54xx())
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
@@ -449,9 +462,15 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
+#define OMAP54XX_CLASS 0x54000054
+#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
+#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
void omap4xxx_check_features(void);
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
detection support.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/control.h | 4 +++
arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
3 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd0..9daac6f 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -246,6 +246,10 @@
/* TI81XX CONTROL_DEVCONF register offsets */
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS 0x134
+#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0e79b7b..d2ec323 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -50,6 +50,11 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+ } else if (cpu_is_omap54xx()) {
+ val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+ val &= OMAP5_DEVICETYPE_MASK;
+ val >>= 6;
+ goto out;
} else {
pr_err("Cannot detect omap type!\n");
goto out;
@@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
+void __init omap5xxx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xb942:
+ switch (rev) {
+ case 0:
+ omap_revision = OMAP5430_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = OMAP5430_REV_ES2_0;
+ break;
+ default:
+ omap_revision = OMAP5430_REV_ES1_0;
+ }
+ break;
+
+ case 0xb998:
+ switch (rev) {
+ case 0:
+ omap_revision = OMAP5432_REV_ES1_0;
+ break;
+ default:
+ omap_revision = OMAP5432_REV_ES1_0;
+ }
+ break;
+
+ default:
+ /* Unknown default to latest silicon rev as default*/
+ omap_revision = OMAP5430_REV_ES2_0;
+ }
+
+ pr_info("OMAP%04x ES%d.0\n",
+ omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index dc6a86b..5e57732 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
- * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
+ * cpu_is_omap543x(): True for OMAP5430, OMAP5432
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@@ -121,6 +122,7 @@ IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
+IS_OMAP_CLASS(54xx, 0x54)
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
@@ -132,6 +134,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
@@ -154,6 +157,8 @@ IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
+#define cpu_is_omap54xx() 0
+#define cpu_is_omap543x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
@@ -299,6 +304,7 @@ IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap3517() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap3630() 0
+#define cpu_is_omap5430() 0
/*
* Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -393,11 +399,18 @@ IS_OMAP_TYPE(3517, 0x3517)
# define cpu_is_omap447x() is_omap447x()
# endif
+# if defined(CONFIG_ARCH_OMAP5)
+# undef cpu_is_omap54xx
+# undef cpu_is_omap543x
+# define cpu_is_omap54xx() is_omap54xx()
+# define cpu_is_omap543x() is_omap543x()
+#endif
+
/* Macros to detect if we have OMAP1 or OMAP2 */
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
cpu_is_omap16xx())
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
- cpu_is_omap44xx())
+ cpu_is_omap44xx() || cpu_is_omap54xx())
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
@@ -449,9 +462,15 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP447X_CLASS 0x44700044
#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
+#define OMAP54XX_CLASS 0x54000054
+#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
+#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
void omap4xxx_check_features(void);
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
2012-05-03 7:26 ` R Sricharan
@ 2012-05-10 11:18 ` Roger Quadros
-1 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:18 UTC (permalink / raw)
To: R Sricharan
Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, tony, b-cousson
Hi,
\
On 05/03/2012 10:26 AM, R Sricharan wrote:
> Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
> detection support.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 4 +++
> arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
> 3 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a406fd0..9daac6f 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -246,6 +246,10 @@
> /* TI81XX CONTROL_DEVCONF register offsets */
> #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
>
> +/* OMAP54XX CONTROL STATUS register */
> +#define OMAP5XXX_CONTROL_STATUS 0x134
> +#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
> +
> /*
> * REVISIT: This list of registers is not comprehensive - there are more
> * that should be added.
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 0e79b7b..d2ec323 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -50,6 +50,11 @@ int omap_type(void)
> val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> } else if (cpu_is_omap44xx()) {
> val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> + } else if (cpu_is_omap54xx()) {
> + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
> + val &= OMAP5_DEVICETYPE_MASK;
> + val >>= 6;
> + goto out;
> } else {
> pr_err("Cannot detect omap type!\n");
> goto out;
> @@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
> ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
> }
>
> +void __init omap5xxx_check_revision(void)
> +{
> + u32 idcode;
> + u16 hawkeye;
> + u8 rev;
> +
> + idcode = read_tap_reg(OMAP_TAP_IDCODE);
> + hawkeye = (idcode >> 12) & 0xffff;
> + rev = (idcode >> 28) & 0xff;
> + switch (hawkeye) {
> + case 0xb942:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5430_REV_ES1_0;
> + break;
> + case 1:
> + omap_revision = OMAP5430_REV_ES2_0;
> + break;
> + default:
> + omap_revision = OMAP5430_REV_ES1_0;
Default should always be the latest version supported. i.e. in this case
it should be OMAP5430_REV_ES2_0
> + }
> + break;
> +
> + case 0xb998:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5432_REV_ES1_0;
> + break;
> + default:
> + omap_revision = OMAP5432_REV_ES1_0;
> + }
> + break;
> +
> + default:
> + /* Unknown default to latest silicon rev as default*/
> + omap_revision = OMAP5430_REV_ES2_0;
> + }
> +
> + pr_info("OMAP%04x ES%d.0\n",
> + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
> +}
> +
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
@ 2012-05-10 11:18 ` Roger Quadros
0 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
\
On 05/03/2012 10:26 AM, R Sricharan wrote:
> Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
> detection support.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 4 +++
> arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
> 3 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a406fd0..9daac6f 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -246,6 +246,10 @@
> /* TI81XX CONTROL_DEVCONF register offsets */
> #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
>
> +/* OMAP54XX CONTROL STATUS register */
> +#define OMAP5XXX_CONTROL_STATUS 0x134
> +#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
> +
> /*
> * REVISIT: This list of registers is not comprehensive - there are more
> * that should be added.
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 0e79b7b..d2ec323 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -50,6 +50,11 @@ int omap_type(void)
> val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> } else if (cpu_is_omap44xx()) {
> val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> + } else if (cpu_is_omap54xx()) {
> + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
> + val &= OMAP5_DEVICETYPE_MASK;
> + val >>= 6;
> + goto out;
> } else {
> pr_err("Cannot detect omap type!\n");
> goto out;
> @@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
> ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
> }
>
> +void __init omap5xxx_check_revision(void)
> +{
> + u32 idcode;
> + u16 hawkeye;
> + u8 rev;
> +
> + idcode = read_tap_reg(OMAP_TAP_IDCODE);
> + hawkeye = (idcode >> 12) & 0xffff;
> + rev = (idcode >> 28) & 0xff;
> + switch (hawkeye) {
> + case 0xb942:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5430_REV_ES1_0;
> + break;
> + case 1:
> + omap_revision = OMAP5430_REV_ES2_0;
> + break;
> + default:
> + omap_revision = OMAP5430_REV_ES1_0;
Default should always be the latest version supported. i.e. in this case
it should be OMAP5430_REV_ES2_0
> + }
> + break;
> +
> + case 0xb998:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5432_REV_ES1_0;
> + break;
> + default:
> + omap_revision = OMAP5432_REV_ES1_0;
> + }
> + break;
> +
> + default:
> + /* Unknown default to latest silicon rev as default*/
> + omap_revision = OMAP5430_REV_ES2_0;
> + }
> +
> + pr_info("OMAP%04x ES%d.0\n",
> + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
> +}
> +
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
2012-05-10 11:18 ` Roger Quadros
@ 2012-05-10 11:22 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 11:22 UTC (permalink / raw)
To: Roger Quadros
Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, tony, b-cousson
Hi Roger,
>> +void __init omap5xxx_check_revision(void)
>> +{
>> + u32 idcode;
>> + u16 hawkeye;
>> + u8 rev;
>> +
>> + idcode = read_tap_reg(OMAP_TAP_IDCODE);
>> + hawkeye = (idcode >> 12) & 0xffff;
>> + rev = (idcode >> 28) & 0xff;
>> + switch (hawkeye) {
>> + case 0xb942:
>> + switch (rev) {
>> + case 0:
>> + omap_revision = OMAP5430_REV_ES1_0;
>> + break;
>> + case 1:
>> + omap_revision = OMAP5430_REV_ES2_0;
>> + break;
>> + default:
>> + omap_revision = OMAP5430_REV_ES1_0;
>
> Default should always be the latest version supported. i.e. in this case
> it should be OMAP5430_REV_ES2_0
>
ok thanks, will correct it.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
@ 2012-05-10 11:22 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 11:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi Roger,
>> +void __init omap5xxx_check_revision(void)
>> +{
>> + ? ? u32 idcode;
>> + ? ? u16 hawkeye;
>> + ? ? u8 rev;
>> +
>> + ? ? idcode = read_tap_reg(OMAP_TAP_IDCODE);
>> + ? ? hawkeye = (idcode >> 12) & 0xffff;
>> + ? ? rev = (idcode >> 28) & 0xff;
>> + ? ? switch (hawkeye) {
>> + ? ? case 0xb942:
>> + ? ? ? ? ? ? switch (rev) {
>> + ? ? ? ? ? ? case 0:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? case 1:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES2_0;
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? default:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;
>
> Default should always be the latest version supported. i.e. in this case
> it should be OMAP5430_REV_ES2_0
>
ok thanks, will correct it.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
2012-05-03 7:26 ` R Sricharan
@ 2012-05-10 13:06 ` Jean-Christophe PLAGNIOL-VILLARD
-1 siblings, 0 replies; 126+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-05-10 13:06 UTC (permalink / raw)
To: R Sricharan
Cc: tony, linux-omap, santosh.shilimkar, b-cousson, linux-arm-kernel
On 12:56 Thu 03 May , R Sricharan wrote:
> Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
> detection support.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 4 +++
> arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
> 3 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a406fd0..9daac6f 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -246,6 +246,10 @@
> /* TI81XX CONTROL_DEVCONF register offsets */
> #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
>
> +/* OMAP54XX CONTROL STATUS register */
> +#define OMAP5XXX_CONTROL_STATUS 0x134
> +#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
> +
> /*
> * REVISIT: This list of registers is not comprehensive - there are more
> * that should be added.
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 0e79b7b..d2ec323 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -50,6 +50,11 @@ int omap_type(void)
> val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> } else if (cpu_is_omap44xx()) {
> val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> + } else if (cpu_is_omap54xx()) {
> + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
> + val &= OMAP5_DEVICETYPE_MASK;
> + val >>= 6;
> + goto out;
> } else {
> pr_err("Cannot detect omap type!\n");
> goto out;
> @@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
> ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
> }
>
> +void __init omap5xxx_check_revision(void)
> +{
> + u32 idcode;
> + u16 hawkeye;
> + u8 rev;
> +
> + idcode = read_tap_reg(OMAP_TAP_IDCODE);
> + hawkeye = (idcode >> 12) & 0xffff;
> + rev = (idcode >> 28) & 0xff;
> + switch (hawkeye) {
> + case 0xb942:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5430_REV_ES1_0;
why do you duplicate this
> + break;
> + case 1:
> + omap_revision = OMAP5430_REV_ES2_0;
> + break;
do this
case 0:
> + default:
> + omap_revision = OMAP5430_REV_ES1_0;
> + }
> + break;
> +
> + case 0xb998:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5432_REV_ES1_0;
> + break;
> + default:
ditto here
> + omap_revision = OMAP5432_REV_ES1_0;
> + }
Best Regards,
J.
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
@ 2012-05-10 13:06 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 126+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-05-10 13:06 UTC (permalink / raw)
To: linux-arm-kernel
On 12:56 Thu 03 May , R Sricharan wrote:
> Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
> detection support.
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 4 +++
> arch/arm/mach-omap2/id.c | 47 +++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/include/plat/cpu.h | 23 ++++++++++++++-
> 3 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index a406fd0..9daac6f 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -246,6 +246,10 @@
> /* TI81XX CONTROL_DEVCONF register offsets */
> #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
>
> +/* OMAP54XX CONTROL STATUS register */
> +#define OMAP5XXX_CONTROL_STATUS 0x134
> +#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
> +
> /*
> * REVISIT: This list of registers is not comprehensive - there are more
> * that should be added.
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 0e79b7b..d2ec323 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -50,6 +50,11 @@ int omap_type(void)
> val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> } else if (cpu_is_omap44xx()) {
> val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> + } else if (cpu_is_omap54xx()) {
> + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
> + val &= OMAP5_DEVICETYPE_MASK;
> + val >>= 6;
> + goto out;
> } else {
> pr_err("Cannot detect omap type!\n");
> goto out;
> @@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
> ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
> }
>
> +void __init omap5xxx_check_revision(void)
> +{
> + u32 idcode;
> + u16 hawkeye;
> + u8 rev;
> +
> + idcode = read_tap_reg(OMAP_TAP_IDCODE);
> + hawkeye = (idcode >> 12) & 0xffff;
> + rev = (idcode >> 28) & 0xff;
> + switch (hawkeye) {
> + case 0xb942:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5430_REV_ES1_0;
why do you duplicate this
> + break;
> + case 1:
> + omap_revision = OMAP5430_REV_ES2_0;
> + break;
do this
case 0:
> + default:
> + omap_revision = OMAP5430_REV_ES1_0;
> + }
> + break;
> +
> + case 0xb998:
> + switch (rev) {
> + case 0:
> + omap_revision = OMAP5432_REV_ES1_0;
> + break;
> + default:
ditto here
> + omap_revision = OMAP5432_REV_ES1_0;
> + }
Best Regards,
J.
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
2012-05-10 13:06 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2012-05-10 13:15 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 13:15 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD
Cc: linux-omap, tony, santosh.shilimkar, b-cousson, linux-arm-kernel
Hi J,
> why do you duplicate this
>> + break;
>> + case 1:
>> + omap_revision = OMAP5430_REV_ES2_0;
>> + break;
> do this
>
> case 0:
>> + default:
>> + omap_revision = OMAP5430_REV_ES1_0;
>> + }
>> + break;
>> +
>> + case 0xb998:
>> + switch (rev) {
>> + case 0:
>> + omap_revision = OMAP5432_REV_ES1_0;
>> + break;
>> + default:
> ditto here
Agree. Will correct the redundancy.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 01/13] ARM: OMAP5: id: Add cpu id for ES versions
@ 2012-05-10 13:15 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 13:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi J,
> why do you duplicate this
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? case 1:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES2_0;
>> + ? ? ? ? ? ? ? ? ? ? break;
> do this
>
> ? ? ? ? ? ? ? ?case 0:
>> + ? ? ? ? ? ? default:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;
>> + ? ? ? ? ? ? }
>> + ? ? ? ? ? ? break;
>> +
>> + ? ? case 0xb998:
>> + ? ? ? ? ? ? switch (rev) {
>> + ? ? ? ? ? ? case 0:
>> + ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5432_REV_ES1_0;
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? default:
> ditto here
Agree. Will correct the redundancy.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
architecture. It's a dual core SOC with GIC used for interrupt
handling and with an integrated L2 cache controller.
OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.
Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/Makefile | 26 ++++++++++----
arch/arm/mach-omap2/clock.c | 3 +-
arch/arm/mach-omap2/cminst44xx.h | 2 +-
arch/arm/mach-omap2/common.c | 24 +++++++++++++
arch/arm/mach-omap2/common.h | 11 ++++++
arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--
arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++
arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++
arch/arm/mach-omap2/prcm.c | 2 +-
arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 ++-
arch/arm/plat-omap/Makefile | 4 +--
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 4 ++-
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/multi.h | 9 +++++
arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++
arch/arm/plat-omap/include/plat/serial.h | 10 +++++
arch/arm/plat-omap/include/plat/uncompress.h | 6 +++
arch/arm/plat-omap/sram.c | 11 +++++-
19 files changed, 208 insertions(+), 22 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 669e2b1..fbb6b3d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
@@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
+omap-4-5-common = omap4-common.o omap-wakeupgen.o \
+ sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
@@ -87,9 +91,11 @@ obj-y += prm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
+omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
+ prcm_mpu44xx.o prminst44xx.o \
+ vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
@@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
+omap-clock-4-5-common = clockdomain.o \
+ clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
+obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931..c589bb8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
/* OMAP3/4 non-CORE DPLL clkops */
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+ defined(CONFIG_ARCH_OMAP5)
const struct clkops clkops_omap3_noncore_dpll_ops = {
.enable = omap3_noncore_dpll_enable,
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a018a73..da67e08 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-# ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8a6953a..a0e74b9 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -182,3 +182,27 @@ void __init omap4_map_io(void)
}
#endif
+#if defined(CONFIG_ARCH_OMAP5)
+static struct omap_globals omap5_globals = {
+ .class = OMAP54XX_CLASS,
+ .tap = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
+ .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP543x_CTRL_BASE),
+ .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
+ .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
+ .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
+ .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
+};
+
+void __init omap2_set_globals_543x(void)
+{
+ omap2_set_globals_tap(&omap5_globals);
+ omap2_set_globals_control(&omap5_globals);
+ omap2_set_globals_prcm(&omap5_globals);
+}
+
+void __init omap5_map_io(void)
+{
+ omap5_map_common_io();
+}
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0672fc5..797dda7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+extern void omap5_map_common_io(void);
+#else
+static inline void omap5_map_common_io(void)
+{
+}
+#endif
+
extern void omap2_init_common_infrastructure(void);
extern struct sys_timer omap2_timer;
@@ -94,6 +102,7 @@ void omap3_init_early(void); /* Do not use this one */
void am35xx_init_early(void);
void ti81xx_init_early(void);
void omap4430_init_early(void);
+void omap5_init_early(void);
void omap_prcm_restart(char, const char *);
/*
@@ -118,6 +127,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
+void omap2_set_globals_543x(void);
void omap2_set_globals_ti81xx(void);
void omap2_set_globals_am33xx(void);
@@ -132,6 +142,7 @@ void omap243x_map_io(void);
void omap3_map_io(void);
void am33xx_map_io(void);
void omap4_map_io(void);
+void omap5_map_io(void);
void ti81xx_map_io(void);
void omap_barriers_init(void);
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cdfc2a1..6ef5898 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -60,12 +60,12 @@ omap_uart_lsr: .word 0
beq 23f @ configure OMAP2UART3
cmp \rp, #OMAP3UART3 @ only on 34xx
beq 33f @ configure OMAP3UART3
- cmp \rp, #OMAP4UART3 @ only on 44xx
- beq 43f @ configure OMAP4UART3
+ cmp \rp, #OMAP4UART3 @ only on 44xx/54xx
+ beq 43f @ configure OMAP4/5UART3
cmp \rp, #OMAP3UART4 @ only on 36xx
beq 34f @ configure OMAP3UART4
- cmp \rp, #OMAP4UART4 @ only on 44xx
- beq 44f @ configure OMAP4UART4
+ cmp \rp, #OMAP4UART4 @ only on 44xx/54xx
+ beq 44f @ configure OMAP4/5UART4
cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 595a5dd..b3f0c3c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -232,6 +232,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
+#ifdef CONFIG_ARCH_OMAP5
+static struct map_desc omap54xx_io_desc[] __initdata = {
+ {
+ .virtual = L3_54XX_VIRT,
+ .pfn = __phys_to_pfn(L3_54XX_PHYS),
+ .length = L3_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_54XX_PHYS),
+ .length = L4_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_WK_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
+ .length = L4_WK_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_PER_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
+ .length = L4_PER_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+#endif
+
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
@@ -277,6 +306,12 @@ void __init omap44xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+void __init omap5_map_common_io(void)
+{
+ iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+}
+#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@@ -454,6 +489,15 @@ void __init omap4430_init_early(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+void __init omap5_init_early(void)
+{
+ omap2_set_globals_543x();
+ omap5xxx_check_revision();
+ omap_common_init_early();
+}
+#endif
+
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 80b8892..cce2b65 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,6 +1,14 @@
/*
* IO mappings for OMAP2+
*
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@@ -166,4 +174,23 @@
/* 0x49000000 --> 0xfb000000 */
#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_ABE_44XX_SIZE SZ_1M
+/*
+ * ----------------------------------------------------------------------------
+ * Omap5 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */
+#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
+#define L3_54XX_SIZE SZ_1M
+
+#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */
+#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_54XX_SIZE SZ_4M
+
+#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
+#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_WK_54XX_SIZE SZ_2M
+#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_PER_54XX_SIZE SZ_4M
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 480f40a..904b494 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -159,7 +159,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
if (omap2_globals->prcm_mpu)
prcm_mpu_base = omap2_globals->prcm_mpu;
- if (cpu_is_omap44xx()) {
+ if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
omap_prm_base_init();
omap_cm_base_init();
}
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a1..85fa808 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -232,8 +232,9 @@
* Stub omap2xxx/omap3xxx functions so that common files
* continue to build when custom builds are used
*/
-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
- defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
WARN(1, "prm: omap2xxx/omap3xxx specific function and "
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index c0fe275..e6d7287 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -13,9 +13,7 @@ obj- :=
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
# omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index b299b8d..d939599 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_446X (1 << 13)
+#define CK_54XX (1 << 14)
#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c..41858f4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -61,6 +61,7 @@ struct clkops {
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
+#define RATE_IN_54XX (1 << 10)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -156,7 +157,8 @@ struct dpll_data {
u8 min_divider;
u16 max_divider;
u8 modes;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
+ || defined(CONFIG_ARCH_OMAP5)
void __iomem *autoidle_reg;
void __iomem *idlest_reg;
u32 autoidle_mask;
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978..ddbde38 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
#include <plat/omap44xx.h>
#include <plat/ti81xx.h>
#include <plat/am33xx.h>
+#include <plat/omap54xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba..9117af9 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,13 @@
# endif
#endif
+#ifdef CONFIG_ARCH_OMAP5
+# ifdef OMAP_NAME
+# undef MULTI_OMAP2
+# define MULTI_OMAP2
+# else
+# define OMAP_NAME omap5
+# endif
+#endif
+
#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 0000000..823873f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP54XX_H
+#define __ASM_ARCH_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE 0x4a000000
+#define L4_WK_54XX_BASE 0x4ae00000
+#define L4_PER_54XX_BASE 0x48000000
+#define L3_54XX_BASE 0x44000000
+#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
+#define OMAP54XX_CM_CORE_BASE 0x4a008000
+#define OMAP54XX_PRM_BASE 0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE 0x48243000
+#define OMAP543x_SCM_BASE 0x4a002000
+#define OMAP543x_CTRL_BASE 0x4a002800
+
+#endif /* __ASM_ARCH_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f..c317f22 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,14 @@
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE 0x48066000
+#define OMAP5_UART6_BASE 0x48068000
+
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@@ -93,6 +101,8 @@
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
+#define OMAP5UART3 OMAP4UART3
+#define OMAP5UART4 OMAP4UART4
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11b..42d6f72 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
_DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
OMAP4UART##p)
+#define DEBUG_LL_OMAP5(p, mach) \
+ _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ OMAP5UART##p)
/* Zoom2/3 shift is different for UART1 and external port */
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -173,6 +176,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_OMAP4(3, omap_4430sdp);
DEBUG_LL_OMAP4(3, omap4_panda);
+ /* omap5 based boards using UART3 */
+ DEBUG_LL_OMAP5(3, omap5_sevm);
+
/* zoom2/3 external uart */
DEBUG_LL_ZOOM(omap_zoom2);
DEBUG_LL_ZOOM(omap_zoom3);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index f9a8c53..a7b6df2 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
#else
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#endif
+#define OMAP5_SRAM_PA 0x40300000
#if defined(CONFIG_ARCH_OMAP2PLUS)
#define SRAM_BOOTLOADER_SZ 0x00
@@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
+ } else if (cpu_is_omap54xx()) {
+ omap_sram_start = OMAP5_SRAM_PA;
+ omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0xe000; /* 56K */
+ } else if (cpu_is_omap54xx()) {
+ omap_sram_start = OMAP5_SRAM_PA;
+ omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
architecture. It's a dual core SOC with GIC used for interrupt
handling and with an integrated L2 cache controller.
OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.
Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/Makefile | 26 ++++++++++----
arch/arm/mach-omap2/clock.c | 3 +-
arch/arm/mach-omap2/cminst44xx.h | 2 +-
arch/arm/mach-omap2/common.c | 24 +++++++++++++
arch/arm/mach-omap2/common.h | 11 ++++++
arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--
arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++
arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++
arch/arm/mach-omap2/prcm.c | 2 +-
arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 ++-
arch/arm/plat-omap/Makefile | 4 +--
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 4 ++-
arch/arm/plat-omap/include/plat/hardware.h | 1 +
arch/arm/plat-omap/include/plat/multi.h | 9 +++++
arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++
arch/arm/plat-omap/include/plat/serial.h | 10 +++++
arch/arm/plat-omap/include/plat/uncompress.h | 6 +++
arch/arm/plat-omap/sram.c | 11 +++++-
19 files changed, 208 insertions(+), 22 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 669e2b1..fbb6b3d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
@@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
+omap-4-5-common = omap4-common.o omap-wakeupgen.o \
+ sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
@@ -87,9 +91,11 @@ obj-y += prm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
+omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
+ prcm_mpu44xx.o prminst44xx.o \
+ vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
# PRCM clockdomain control
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
@@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
+omap-clock-4-5-common = clockdomain.o \
+ clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
+obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931..c589bb8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
/* OMAP3/4 non-CORE DPLL clkops */
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+ defined(CONFIG_ARCH_OMAP5)
const struct clkops clkops_omap3_noncore_dpll_ops = {
.enable = omap3_noncore_dpll_enable,
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a018a73..da67e08 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-# ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8a6953a..a0e74b9 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -182,3 +182,27 @@ void __init omap4_map_io(void)
}
#endif
+#if defined(CONFIG_ARCH_OMAP5)
+static struct omap_globals omap5_globals = {
+ .class = OMAP54XX_CLASS,
+ .tap = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
+ .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP543x_CTRL_BASE),
+ .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
+ .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
+ .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
+ .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
+};
+
+void __init omap2_set_globals_543x(void)
+{
+ omap2_set_globals_tap(&omap5_globals);
+ omap2_set_globals_control(&omap5_globals);
+ omap2_set_globals_prcm(&omap5_globals);
+}
+
+void __init omap5_map_io(void)
+{
+ omap5_map_common_io();
+}
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0672fc5..797dda7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+extern void omap5_map_common_io(void);
+#else
+static inline void omap5_map_common_io(void)
+{
+}
+#endif
+
extern void omap2_init_common_infrastructure(void);
extern struct sys_timer omap2_timer;
@@ -94,6 +102,7 @@ void omap3_init_early(void); /* Do not use this one */
void am35xx_init_early(void);
void ti81xx_init_early(void);
void omap4430_init_early(void);
+void omap5_init_early(void);
void omap_prcm_restart(char, const char *);
/*
@@ -118,6 +127,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
+void omap2_set_globals_543x(void);
void omap2_set_globals_ti81xx(void);
void omap2_set_globals_am33xx(void);
@@ -132,6 +142,7 @@ void omap243x_map_io(void);
void omap3_map_io(void);
void am33xx_map_io(void);
void omap4_map_io(void);
+void omap5_map_io(void);
void ti81xx_map_io(void);
void omap_barriers_init(void);
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cdfc2a1..6ef5898 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -60,12 +60,12 @@ omap_uart_lsr: .word 0
beq 23f @ configure OMAP2UART3
cmp \rp, #OMAP3UART3 @ only on 34xx
beq 33f @ configure OMAP3UART3
- cmp \rp, #OMAP4UART3 @ only on 44xx
- beq 43f @ configure OMAP4UART3
+ cmp \rp, #OMAP4UART3 @ only on 44xx/54xx
+ beq 43f @ configure OMAP4/5UART3
cmp \rp, #OMAP3UART4 @ only on 36xx
beq 34f @ configure OMAP3UART4
- cmp \rp, #OMAP4UART4 @ only on 44xx
- beq 44f @ configure OMAP4UART4
+ cmp \rp, #OMAP4UART4 @ only on 44xx/54xx
+ beq 44f @ configure OMAP4/5UART4
cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 595a5dd..b3f0c3c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -232,6 +232,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
+#ifdef CONFIG_ARCH_OMAP5
+static struct map_desc omap54xx_io_desc[] __initdata = {
+ {
+ .virtual = L3_54XX_VIRT,
+ .pfn = __phys_to_pfn(L3_54XX_PHYS),
+ .length = L3_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_54XX_PHYS),
+ .length = L4_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_WK_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
+ .length = L4_WK_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = L4_PER_54XX_VIRT,
+ .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
+ .length = L4_PER_54XX_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+#endif
+
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
@@ -277,6 +306,12 @@ void __init omap44xx_map_common_io(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+void __init omap5_map_common_io(void)
+{
+ iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+}
+#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
@@ -454,6 +489,15 @@ void __init omap4430_init_early(void)
}
#endif
+#ifdef CONFIG_ARCH_OMAP5
+void __init omap5_init_early(void)
+{
+ omap2_set_globals_543x();
+ omap5xxx_check_revision();
+ omap_common_init_early();
+}
+#endif
+
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 80b8892..cce2b65 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,6 +1,14 @@
/*
* IO mappings for OMAP2+
*
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@@ -166,4 +174,23 @@
/* 0x49000000 --> 0xfb000000 */
#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_ABE_44XX_SIZE SZ_1M
+/*
+ * ----------------------------------------------------------------------------
+ * Omap5 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */
+#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
+#define L3_54XX_SIZE SZ_1M
+
+#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */
+#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_54XX_SIZE SZ_4M
+
+#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
+#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_WK_54XX_SIZE SZ_2M
+#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_PER_54XX_SIZE SZ_4M
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 480f40a..904b494 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -159,7 +159,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
if (omap2_globals->prcm_mpu)
prcm_mpu_base = omap2_globals->prcm_mpu;
- if (cpu_is_omap44xx()) {
+ if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
omap_prm_base_init();
omap_cm_base_init();
}
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a1..85fa808 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -232,8 +232,9 @@
* Stub omap2xxx/omap3xxx functions so that common files
* continue to build when custom builds are used
*/
-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
- defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+
static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
WARN(1, "prm: omap2xxx/omap3xxx specific function and "
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index c0fe275..e6d7287 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -13,9 +13,7 @@ obj- :=
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
# omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index b299b8d..d939599 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_446X (1 << 13)
+#define CK_54XX (1 << 14)
#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c..41858f4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -61,6 +61,7 @@ struct clkops {
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
+#define RATE_IN_54XX (1 << 10)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -156,7 +157,8 @@ struct dpll_data {
u8 min_divider;
u16 max_divider;
u8 modes;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
+ || defined(CONFIG_ARCH_OMAP5)
void __iomem *autoidle_reg;
void __iomem *idlest_reg;
u32 autoidle_mask;
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978..ddbde38 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
#include <plat/omap44xx.h>
#include <plat/ti81xx.h>
#include <plat/am33xx.h>
+#include <plat/omap54xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba..9117af9 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,13 @@
# endif
#endif
+#ifdef CONFIG_ARCH_OMAP5
+# ifdef OMAP_NAME
+# undef MULTI_OMAP2
+# define MULTI_OMAP2
+# else
+# define OMAP_NAME omap5
+# endif
+#endif
+
#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 0000000..823873f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP54XX_H
+#define __ASM_ARCH_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE 0x4a000000
+#define L4_WK_54XX_BASE 0x4ae00000
+#define L4_PER_54XX_BASE 0x48000000
+#define L3_54XX_BASE 0x44000000
+#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
+#define OMAP54XX_CM_CORE_BASE 0x4a008000
+#define OMAP54XX_PRM_BASE 0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE 0x48243000
+#define OMAP543x_SCM_BASE 0x4a002000
+#define OMAP543x_CTRL_BASE 0x4a002800
+
+#endif /* __ASM_ARCH_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f..c317f22 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,14 @@
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE 0x48066000
+#define OMAP5_UART6_BASE 0x48068000
+
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@@ -93,6 +101,8 @@
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
+#define OMAP5UART3 OMAP4UART3
+#define OMAP5UART4 OMAP4UART4
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11b..42d6f72 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
_DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
OMAP4UART##p)
+#define DEBUG_LL_OMAP5(p, mach) \
+ _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ OMAP5UART##p)
/* Zoom2/3 shift is different for UART1 and external port */
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -173,6 +176,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_OMAP4(3, omap_4430sdp);
DEBUG_LL_OMAP4(3, omap4_panda);
+ /* omap5 based boards using UART3 */
+ DEBUG_LL_OMAP5(3, omap5_sevm);
+
/* zoom2/3 external uart */
DEBUG_LL_ZOOM(omap_zoom2);
DEBUG_LL_ZOOM(omap_zoom3);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index f9a8c53..a7b6df2 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
#else
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#endif
+#define OMAP5_SRAM_PA 0x40300000
#if defined(CONFIG_ARCH_OMAP2PLUS)
#define SRAM_BOOTLOADER_SZ 0x00
@@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
+ } else if (cpu_is_omap54xx()) {
+ omap_sram_start = OMAP5_SRAM_PA;
+ omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0xe000; /* 56K */
+ } else if (cpu_is_omap54xx()) {
+ omap_sram_start = OMAP5_SRAM_PA;
+ omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-03 7:26 ` R Sricharan
@ 2012-05-04 22:39 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:39 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
> obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
>
> ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
> obj-y += mcbsp.o
> @@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
>
> obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
> -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
> +omap-4-5-common = omap4-common.o omap-wakeupgen.o \
> + sleep44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
>
> plus_sec := $(call as-instr,.arch_extension sec,+sec)
> AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> +obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
> obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
> obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
> @@ -87,9 +91,11 @@ obj-y += prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
> +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
> + prcm_mpu44xx.o prminst44xx.o \
> + vc44xx_data.o vp44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
>
> # OMAP voltage domains
> voltagedomain-common := voltage.o vc.o vp.o
> @@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> powerdomain-common += powerdomain.o powerdomain-common.o
> @@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
>
> # PRCM clockdomain control
> obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
> @@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> +omap-clock-4-5-common = clockdomain.o \
> + clockdomain44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
>
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> @@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
> obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
> +obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
>
> # OMAP2 clock rate set data (old "OPP" data)
> obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
OK this seems to be based on Santosh' Makefile cleanup.
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index d9f4931..c589bb8 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
>
> /* OMAP3/4 non-CORE DPLL clkops */
>
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> + defined(CONFIG_ARCH_OMAP5)
>
How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
Then this becomes just:
#ifdef CONFIG_SOC_OMAP3PLUS
> --- a/arch/arm/mach-omap2/cminst44xx.h
> +++ b/arch/arm/mach-omap2/cminst44xx.h
> @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
>
> extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
>
> -# ifdef CONFIG_ARCH_OMAP4
> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> u16 clkctrl_offs);
And this would be:
#ifdef CONFIG_SOC_OMAP4PLUS
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0672fc5..797dda7 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
> }
> #endif
>
> +#ifdef CONFIG_ARCH_OMAP5
> +extern void omap5_map_common_io(void);
> +#else
> +static inline void omap5_map_common_io(void)
> +{
> +}
> +#endif
> +
> extern void omap2_init_common_infrastructure(void);
Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> @@ -232,8 +232,9 @@
> * Stub omap2xxx/omap3xxx functions so that common files
> * continue to build when custom builds are used
> */
> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> - defined(CONFIG_ARCH_OMAP3))
> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> +
> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> {
> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
Maybe these functions could be just set up as __weak to avoid the
ifdeffery?
> --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
> +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
> @@ -40,6 +40,7 @@ struct omap_clk {
> #define CK_443X (1 << 11)
> #define CK_TI816X (1 << 12)
> #define CK_446X (1 << 13)
> +#define CK_54XX (1 << 14)
> #define CK_1710 (1 << 15) /* 1710 extra for rate selection */
>
>
Are we going to have to patch tons of existing clocks just to add
CK_54XX? If so, we should init clocks using SoC specific lists instead.
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index d0ef57c..41858f4 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -61,6 +61,7 @@ struct clkops {
> #define RATE_IN_4460 (1 << 7)
> #define RATE_IN_AM33XX (1 << 8)
> #define RATE_IN_TI814X (1 << 9)
> +#define RATE_IN_54XX (1 << 10)
This too may have similar issues, but I guess that's really a different
patch series to sort out..
> @@ -156,7 +157,8 @@ struct dpll_data {
> u8 min_divider;
> u16 max_divider;
> u8 modes;
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
> + || defined(CONFIG_ARCH_OMAP5)
> void __iomem *autoidle_reg;
> void __iomem *idlest_reg;
> u32 autoidle_mask;
#ifdef CONFIG_SOC_OMAP3PLUS could be used here too
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-04 22:39 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:39 UTC (permalink / raw)
To: linux-arm-kernel
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
> obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
>
> ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
> obj-y += mcbsp.o
> @@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
>
> obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
> -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
> +omap-4-5-common = omap4-common.o omap-wakeupgen.o \
> + sleep44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
>
> plus_sec := $(call as-instr,.arch_extension sec,+sec)
> AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> +obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
> obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
> obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
> @@ -87,9 +91,11 @@ obj-y += prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
> +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
> + prcm_mpu44xx.o prminst44xx.o \
> + vc44xx_data.o vp44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
>
> # OMAP voltage domains
> voltagedomain-common := voltage.o vc.o vp.o
> @@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> powerdomain-common += powerdomain.o powerdomain-common.o
> @@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
>
> # PRCM clockdomain control
> obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
> @@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> +omap-clock-4-5-common = clockdomain.o \
> + clockdomain44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
>
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> @@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
> obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
> +obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
>
> # OMAP2 clock rate set data (old "OPP" data)
> obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
OK this seems to be based on Santosh' Makefile cleanup.
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index d9f4931..c589bb8 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
>
> /* OMAP3/4 non-CORE DPLL clkops */
>
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> + defined(CONFIG_ARCH_OMAP5)
>
How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
Then this becomes just:
#ifdef CONFIG_SOC_OMAP3PLUS
> --- a/arch/arm/mach-omap2/cminst44xx.h
> +++ b/arch/arm/mach-omap2/cminst44xx.h
> @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
>
> extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
>
> -# ifdef CONFIG_ARCH_OMAP4
> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> u16 clkctrl_offs);
And this would be:
#ifdef CONFIG_SOC_OMAP4PLUS
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0672fc5..797dda7 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
> }
> #endif
>
> +#ifdef CONFIG_ARCH_OMAP5
> +extern void omap5_map_common_io(void);
> +#else
> +static inline void omap5_map_common_io(void)
> +{
> +}
> +#endif
> +
> extern void omap2_init_common_infrastructure(void);
Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> @@ -232,8 +232,9 @@
> * Stub omap2xxx/omap3xxx functions so that common files
> * continue to build when custom builds are used
> */
> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> - defined(CONFIG_ARCH_OMAP3))
> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> +
> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> {
> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
Maybe these functions could be just set up as __weak to avoid the
ifdeffery?
> --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
> +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
> @@ -40,6 +40,7 @@ struct omap_clk {
> #define CK_443X (1 << 11)
> #define CK_TI816X (1 << 12)
> #define CK_446X (1 << 13)
> +#define CK_54XX (1 << 14)
> #define CK_1710 (1 << 15) /* 1710 extra for rate selection */
>
>
Are we going to have to patch tons of existing clocks just to add
CK_54XX? If so, we should init clocks using SoC specific lists instead.
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index d0ef57c..41858f4 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -61,6 +61,7 @@ struct clkops {
> #define RATE_IN_4460 (1 << 7)
> #define RATE_IN_AM33XX (1 << 8)
> #define RATE_IN_TI814X (1 << 9)
> +#define RATE_IN_54XX (1 << 10)
This too may have similar issues, but I guess that's really a different
patch series to sort out..
> @@ -156,7 +157,8 @@ struct dpll_data {
> u8 min_divider;
> u16 max_divider;
> u8 modes;
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
> + || defined(CONFIG_ARCH_OMAP5)
> void __iomem *autoidle_reg;
> void __iomem *idlest_reg;
> u32 autoidle_mask;
#ifdef CONFIG_SOC_OMAP3PLUS could be used here too
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-04 22:39 ` Tony Lindgren
@ 2012-05-04 22:47 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:47 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* Tony Lindgren <tony@atomide.com> [120504 15:43]:
> > --- a/arch/arm/mach-omap2/clock.c
> > +++ b/arch/arm/mach-omap2/clock.c
> > @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
> >
> > /* OMAP3/4 non-CORE DPLL clkops */
> >
> > -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> > +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> > + defined(CONFIG_ARCH_OMAP5)
> >
>
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
>
> > --- a/arch/arm/mach-omap2/cminst44xx.h
> > +++ b/arch/arm/mach-omap2/cminst44xx.h
> > @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
> >
> > extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
> >
> > -# ifdef CONFIG_ARCH_OMAP4
> > +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> > extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> > u16 clkctrl_offs);
>
> And this would be:
>
> #ifdef CONFIG_SOC_OMAP4PLUS
Something like this might do the trick (untested):
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -28,10 +28,14 @@ config ARCH_OMAP2
select MULTI_IRQ_HANDLER
select PINCTRL
+bool SOC_OMAP3PLUS
+ bool
+
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_OMAP2PLUS
default y
+ select SOC_OMAP3PLUS
select CPU_V7
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARCH_HAS_OPP
@@ -40,10 +44,15 @@ config ARCH_OMAP3
select MULTI_IRQ_HANDLER
select PINCTRL
+bool SOC_OMAP4PLUS
+ bool
+
config ARCH_OMAP4
bool "TI OMAP4"
default y
depends on ARCH_OMAP2PLUS
+ select SOC_OMAP3PLUS
+ select SOC_OMAP4PLUS
select CACHE_L2X0
select CPU_V7
select ARM_GIC
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-04 22:47 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:47 UTC (permalink / raw)
To: linux-arm-kernel
* Tony Lindgren <tony@atomide.com> [120504 15:43]:
> > --- a/arch/arm/mach-omap2/clock.c
> > +++ b/arch/arm/mach-omap2/clock.c
> > @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
> >
> > /* OMAP3/4 non-CORE DPLL clkops */
> >
> > -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> > +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> > + defined(CONFIG_ARCH_OMAP5)
> >
>
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
>
> > --- a/arch/arm/mach-omap2/cminst44xx.h
> > +++ b/arch/arm/mach-omap2/cminst44xx.h
> > @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
> >
> > extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
> >
> > -# ifdef CONFIG_ARCH_OMAP4
> > +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> > extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> > u16 clkctrl_offs);
>
> And this would be:
>
> #ifdef CONFIG_SOC_OMAP4PLUS
Something like this might do the trick (untested):
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -28,10 +28,14 @@ config ARCH_OMAP2
select MULTI_IRQ_HANDLER
select PINCTRL
+bool SOC_OMAP3PLUS
+ bool
+
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_OMAP2PLUS
default y
+ select SOC_OMAP3PLUS
select CPU_V7
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARCH_HAS_OPP
@@ -40,10 +44,15 @@ config ARCH_OMAP3
select MULTI_IRQ_HANDLER
select PINCTRL
+bool SOC_OMAP4PLUS
+ bool
+
config ARCH_OMAP4
bool "TI OMAP4"
default y
depends on ARCH_OMAP2PLUS
+ select SOC_OMAP3PLUS
+ select SOC_OMAP4PLUS
select CACHE_L2X0
select CPU_V7
select ARM_GIC
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-04 22:39 ` Tony Lindgren
@ 2012-05-06 7:36 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-06 7:36 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Hi Tony,
[snip]
> OK this seems to be based on Santosh' Makefile cleanup.
>
yes..
>>
>> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
>> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
>> + defined(CONFIG_ARCH_OMAP5)
>>
>
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
>
Ok, thanks for the example later. I will do a cleanup patch and
rebase this one.
>> -# ifdef CONFIG_ARCH_OMAP4
>> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
>> extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
>> u16 clkctrl_offs);
>
> And this would be:
>
> #ifdef CONFIG_SOC_OMAP4PLUS
>
ok..
>
> Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
> of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
> for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
>
ok. sure. will change this.
>> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
>> - defined(CONFIG_ARCH_OMAP3))
>> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
>> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
>> +
>> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
>> {
>> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
>
> Maybe these functions could be just set up as __weak to avoid the
> ifdeffery?
>
sorry to understand,
you mean make this weak and have a strong override for OMAP2 ?
>> #define CK_443X (1 << 11)
>> #define CK_TI816X (1 << 12)
>> #define CK_446X (1 << 13)
>> +#define CK_54XX (1 << 14)
>> #define CK_1710 (1 << 15) /* 1710 extra for rate selection */
>>
>>
>
> Are we going to have to patch tons of existing clocks just to add
> CK_54XX? If so, we should init clocks using SoC specific lists instead.
>
>> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
>> index d0ef57c..41858f4 100644
>> --- a/arch/arm/plat-omap/include/plat/clock.h
>> +++ b/arch/arm/plat-omap/include/plat/clock.h
>> @@ -61,6 +61,7 @@ struct clkops {
>> #define RATE_IN_4460 (1 << 7)
>> #define RATE_IN_AM33XX (1 << 8)
>> #define RATE_IN_TI814X (1 << 9)
>> +#define RATE_IN_54XX (1 << 10)
>
> This too may have similar issues, but I guess that's really a different
> patch series to sort out..
>
ok. agree
>> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
>> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
>> + || defined(CONFIG_ARCH_OMAP5)
>> void __iomem *autoidle_reg;
>> void __iomem *idlest_reg;
>> u32 autoidle_mask;
>
>
> #ifdef CONFIG_SOC_OMAP3PLUS could be used here too
>
ok..
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-06 7:36 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-06 7:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
[snip]
> OK this seems to be based on Santosh' Makefile cleanup.
>
yes..
>>
>> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
>> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP5)
>>
>
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
>
Ok, thanks for the example later. I will do a cleanup patch and
rebase this one.
>> -# ifdef CONFIG_ARCH_OMAP4
>> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
>> ?extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?u16 clkctrl_offs);
>
> And this would be:
>
> #ifdef CONFIG_SOC_OMAP4PLUS
>
ok..
>
> Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
> of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
> for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
>
ok. sure. will change this.
>> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
>> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
>> + ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
>> +
>> ?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
>> ?{
>> ? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "
>
> Maybe these functions could be just set up as __weak to avoid the
> ifdeffery?
>
sorry to understand,
you mean make this weak and have a strong override for OMAP2 ?
>> ?#define CK_443X ? ? ? ? ? ? ?(1 << 11)
>> ?#define CK_TI816X ? ?(1 << 12)
>> ?#define CK_446X ? ? ? ? ? ? ?(1 << 13)
>> +#define CK_54XX ? ? ? ? ? ? ?(1 << 14)
>> ?#define CK_1710 ? ? ? ? ? ? ?(1 << 15) ? ? ? /* 1710 extra for rate selection */
>>
>>
>
> Are we going to have to patch tons of existing clocks just to add
> CK_54XX? If so, we should init clocks using SoC specific lists instead.
>
>> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
>> index d0ef57c..41858f4 100644
>> --- a/arch/arm/plat-omap/include/plat/clock.h
>> +++ b/arch/arm/plat-omap/include/plat/clock.h
>> @@ -61,6 +61,7 @@ struct clkops {
>> ?#define RATE_IN_4460 ? ? ? ? (1 << 7)
>> ?#define RATE_IN_AM33XX ? ? ? ? ? ? ? (1 << 8)
>> ?#define RATE_IN_TI814X ? ? ? ? ? ? ? (1 << 9)
>> +#define RATE_IN_54XX ? ? ? ? (1 << 10)
>
> This too may have similar issues, but I guess that's really a different
> patch series to sort out..
>
ok. agree
>> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
>> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
>> + ? ? ? ? ? ? || defined(CONFIG_ARCH_OMAP5)
>> ? ? ? void __iomem ? ? ? ? ? ?*autoidle_reg;
>> ? ? ? void __iomem ? ? ? ? ? ?*idlest_reg;
>> ? ? ? u32 ? ? ? ? ? ? ? ? ? ? autoidle_mask;
>
>
> #ifdef CONFIG_SOC_OMAP3PLUS could be used here too
>
ok..
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-06 7:36 ` R, Sricharan
@ 2012-05-07 17:33 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:33 UTC (permalink / raw)
To: R, Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R, Sricharan <r.sricharan@ti.com> [120506 00:40]:
>
> > Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
> > of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
> > for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
> >
> ok. sure. will change this.
Thanks.
> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> >> - defined(CONFIG_ARCH_OMAP3))
> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> >> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> >> +
> >> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> >> {
> >> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
> >
> > Maybe these functions could be just set up as __weak to avoid the
> > ifdeffery?
> >
> sorry to understand,
> you mean make this weak and have a strong override for OMAP2 ?
Yeah that should do the trick, right?
Regards,
Tony
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-07 17:33 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:33 UTC (permalink / raw)
To: linux-arm-kernel
* R, Sricharan <r.sricharan@ti.com> [120506 00:40]:
>
> > Also, please change the whole series to use CONFIG_SOC_OMAP5 instead
> > of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except
> > for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.
> >
> ok. sure. will change this.
Thanks.
> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
> >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> >> + ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> >> +
> >> ?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> >> ?{
> >> ? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "
> >
> > Maybe these functions could be just set up as __weak to avoid the
> > ifdeffery?
> >
> sorry to understand,
> you mean make this weak and have a strong override for OMAP2 ?
Yeah that should do the trick, right?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 17:33 ` Tony Lindgren
@ 2012-05-09 9:06 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-09 9:06 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Tony,
[snip]
>> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
>> >> - defined(CONFIG_ARCH_OMAP3))
>> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
>> >> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
>> >> +
>> >> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
>> >> {
>> >> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
>> >
>> > Maybe these functions could be just set up as __weak to avoid the
>> > ifdeffery?
>> >
>> sorry to understand,
>> you mean make this weak and have a strong override for OMAP2 ?
>
> Yeah that should do the trick, right?
Ok, There are multiple functions under that #ifdef.
Also i see that __weak cannot be used for inline functions.
So should those functions should be moved to .c file and qualify them
__weak. There is already a strong override for OMAP2 and 3 which
should not be a problem.
[OR]
So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
it can be changed as
#ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
defined(CONFIG_ARCH_OMAP3))
So this will avoid patching this for the future socs. ?
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-09 9:06 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-09 9:06 UTC (permalink / raw)
To: linux-arm-kernel
Tony,
[snip]
>> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
>> >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
>> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
>> >> + ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
>> >> +
>> >> ?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
>> >> ?{
>> >> ? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "
>> >
>> > Maybe these functions could be just set up as __weak to avoid the
>> > ifdeffery?
>> >
>> ?sorry to understand,
>> ?you mean make this weak and have a strong override for OMAP2 ?
>
> Yeah that should do the trick, right?
Ok, There are multiple functions under that #ifdef.
Also i see that __weak cannot be used for inline functions.
So should those functions should be moved to .c file and qualify them
__weak. There is already a strong override for OMAP2 and 3 which
should not be a problem.
[OR]
So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
it can be changed as
#ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
defined(CONFIG_ARCH_OMAP3))
So this will avoid patching this for the future socs. ?
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-09 9:06 ` R, Sricharan
@ 2012-05-09 16:00 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-09 16:00 UTC (permalink / raw)
To: R, Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R, Sricharan <r.sricharan@ti.com> [120509 02:09]:
> Tony,
>
> [snip]
> >> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> >> >> - defined(CONFIG_ARCH_OMAP3))
> >> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> >> >> + !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> >> >> +
> >> >> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> >> >> {
> >> >> WARN(1, "prm: omap2xxx/omap3xxx specific function and "
> >> >
> >> > Maybe these functions could be just set up as __weak to avoid the
> >> > ifdeffery?
> >> >
> >> sorry to understand,
> >> you mean make this weak and have a strong override for OMAP2 ?
> >
> > Yeah that should do the trick, right?
> Ok, There are multiple functions under that #ifdef.
> Also i see that __weak cannot be used for inline functions.
> So should those functions should be moved to .c file and qualify them
> __weak. There is already a strong override for OMAP2 and 3 which
> should not be a problem.
Yes that's worth experimenting with to set up things in a way where
we don't need to add new ifdefs to add a new SoC.
> [OR]
>
> So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
> it can be changed as
> #ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
> defined(CONFIG_ARCH_OMAP3))
>
> So this will avoid patching this for the future socs. ?
Well it seems that we've come to a conclusion that if we introduce
new config options, they should be based on features instead. So
CONFIG_SOC_HAS_OMAPXYZ_BLAH rather than CONFIG_SOC_OMAP4PLUS.
Regards,
Tony
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-09 16:00 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-09 16:00 UTC (permalink / raw)
To: linux-arm-kernel
* R, Sricharan <r.sricharan@ti.com> [120509 02:09]:
> Tony,
>
> [snip]
> >> >> -#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
> >> >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
> >> >> +#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
> >> >> + ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
> >> >> +
> >> >> ?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> >> >> ?{
> >> >> ? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "
> >> >
> >> > Maybe these functions could be just set up as __weak to avoid the
> >> > ifdeffery?
> >> >
> >> ?sorry to understand,
> >> ?you mean make this weak and have a strong override for OMAP2 ?
> >
> > Yeah that should do the trick, right?
> Ok, There are multiple functions under that #ifdef.
> Also i see that __weak cannot be used for inline functions.
> So should those functions should be moved to .c file and qualify them
> __weak. There is already a strong override for OMAP2 and 3 which
> should not be a problem.
Yes that's worth experimenting with to set up things in a way where
we don't need to add new ifdefs to add a new SoC.
> [OR]
>
> So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
> it can be changed as
> #ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
> defined(CONFIG_ARCH_OMAP3))
>
> So this will avoid patching this for the future socs. ?
Well it seems that we've come to a conclusion that if we introduce
new config options, they should be based on features instead. So
CONFIG_SOC_HAS_OMAPXYZ_BLAH rather than CONFIG_SOC_OMAP4PLUS.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-09 16:00 ` Tony Lindgren
@ 2012-05-10 9:49 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 9:49 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Tony,
[snip]
>> So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
>> it can be changed as
>> #ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
>> defined(CONFIG_ARCH_OMAP3))
>>
>> So this will avoid patching this for the future socs. ?
>
> Well it seems that we've come to a conclusion that if we introduce
> new config options, they should be based on features instead. So
> CONFIG_SOC_HAS_OMAPXYZ_BLAH rather than CONFIG_SOC_OMAP4PLUS.
>
Sure thanks for clarifying.
Then i will introduce a relevant config in my cleanup patch first and
then add OMAP5.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-10 9:49 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-10 9:49 UTC (permalink / raw)
To: linux-arm-kernel
Tony,
[snip]
>> ?So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS
>> ?it can be changed as
>> ?#ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
>> defined(CONFIG_ARCH_OMAP3))
>>
>> So this will avoid patching this for the future socs. ?
>
> Well it seems that we've come to a conclusion that if we introduce
> new config options, they should be based on features instead. So
> CONFIG_SOC_HAS_OMAPXYZ_BLAH rather than CONFIG_SOC_OMAP4PLUS.
>
Sure thanks for clarifying.
Then i will introduce a relevant config in my cleanup patch first and
then add OMAP5.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-04 22:39 ` Tony Lindgren
@ 2012-05-07 19:07 ` Paul Walmsley
-1 siblings, 0 replies; 126+ messages in thread
From: Paul Walmsley @ 2012-05-07 19:07 UTC (permalink / raw)
To: Tony Lindgren
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Hi,
On Fri, 4 May 2012, Tony Lindgren wrote:
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
We might want to consider having separate CONFIG_SOC_* values for each
SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
CONFIG_SOC_OMAP3630, etc.
This would be for two main reasons. One is that Kconfig options like
CONFIG_SOC_OMAP3PLUS don't have much meaning. It is really unclear to me
what SoCs would be included in CONFIG_SOC_OMAP3PLUS, since some of them
differ so radically -- different interconnects, different power and system
management IP blocks, different CPU subsystems, different RAM controllers,
etc. The advantage of using SoC-specific Kconfig options, from this point
of view, is that it is easy to know what they mean. Then those
SoC-specific Kconfig options can select the appropriate SoC-independent
interconnect driver, PRCM drivers, CPU options, etc.
The other motivation would be to support device manufacturers who only
wish to build a kernel for the single device that they are shipping. In
terms of kernels shipped, this is probably the most popular use-case. With
something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
of code and data (and potentially bugs) that are not needed for their
specific device.
- Paul
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-07 19:07 ` Paul Walmsley
0 siblings, 0 replies; 126+ messages in thread
From: Paul Walmsley @ 2012-05-07 19:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Fri, 4 May 2012, Tony Lindgren wrote:
> How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> Then this becomes just:
>
> #ifdef CONFIG_SOC_OMAP3PLUS
We might want to consider having separate CONFIG_SOC_* values for each
SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
CONFIG_SOC_OMAP3630, etc.
This would be for two main reasons. One is that Kconfig options like
CONFIG_SOC_OMAP3PLUS don't have much meaning. It is really unclear to me
what SoCs would be included in CONFIG_SOC_OMAP3PLUS, since some of them
differ so radically -- different interconnects, different power and system
management IP blocks, different CPU subsystems, different RAM controllers,
etc. The advantage of using SoC-specific Kconfig options, from this point
of view, is that it is easy to know what they mean. Then those
SoC-specific Kconfig options can select the appropriate SoC-independent
interconnect driver, PRCM drivers, CPU options, etc.
The other motivation would be to support device manufacturers who only
wish to build a kernel for the single device that they are shipping. In
terms of kernels shipped, this is probably the most popular use-case. With
something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
of code and data (and potentially bugs) that are not needed for their
specific device.
- Paul
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 19:07 ` Paul Walmsley
@ 2012-05-07 19:18 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 19:18 UTC (permalink / raw)
To: Paul Walmsley
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> Hi,
>
> On Fri, 4 May 2012, Tony Lindgren wrote:
>
> > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > Then this becomes just:
> >
> > #ifdef CONFIG_SOC_OMAP3PLUS
>
> We might want to consider having separate CONFIG_SOC_* values for each
> SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> CONFIG_SOC_OMAP3630, etc.
Hmm but this would be in addition to the SOC specific options. The goal
is to cut down the ifdeffery needed all over the place to add new SoCs,
see the experimental patch I posted:
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
> This would be for two main reasons. One is that Kconfig options like
> CONFIG_SOC_OMAP3PLUS don't have much meaning. It is really unclear to me
> what SoCs would be included in CONFIG_SOC_OMAP3PLUS, since some of them
> differ so radically -- different interconnects, different power and system
> management IP blocks, different CPU subsystems, different RAM controllers,
> etc. The advantage of using SoC-specific Kconfig options, from this point
> of view, is that it is easy to know what they mean. Then those
> SoC-specific Kconfig options can select the appropriate SoC-independent
> interconnect driver, PRCM drivers, CPU options, etc.
Just to continue exploring just using the SoC specific options, we would
currently end up with more of this kind of nastiness:
#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
defined(CONFIG_ARCH_OMAP3))
> The other motivation would be to support device manufacturers who only
> wish to build a kernel for the single device that they are shipping. In
> terms of kernels shipped, this is probably the most popular use-case. With
> something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
> of code and data (and potentially bugs) that are not needed for their
> specific device.
Sure, but I think you're missing the point: This would be in addition
to the SoC specific options. Do you still see issues with that?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-07 19:18 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 19:18 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> Hi,
>
> On Fri, 4 May 2012, Tony Lindgren wrote:
>
> > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > Then this becomes just:
> >
> > #ifdef CONFIG_SOC_OMAP3PLUS
>
> We might want to consider having separate CONFIG_SOC_* values for each
> SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> CONFIG_SOC_OMAP3630, etc.
Hmm but this would be in addition to the SOC specific options. The goal
is to cut down the ifdeffery needed all over the place to add new SoCs,
see the experimental patch I posted:
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
> This would be for two main reasons. One is that Kconfig options like
> CONFIG_SOC_OMAP3PLUS don't have much meaning. It is really unclear to me
> what SoCs would be included in CONFIG_SOC_OMAP3PLUS, since some of them
> differ so radically -- different interconnects, different power and system
> management IP blocks, different CPU subsystems, different RAM controllers,
> etc. The advantage of using SoC-specific Kconfig options, from this point
> of view, is that it is easy to know what they mean. Then those
> SoC-specific Kconfig options can select the appropriate SoC-independent
> interconnect driver, PRCM drivers, CPU options, etc.
Just to continue exploring just using the SoC specific options, we would
currently end up with more of this kind of nastiness:
#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
defined(CONFIG_ARCH_OMAP3))
> The other motivation would be to support device manufacturers who only
> wish to build a kernel for the single device that they are shipping. In
> terms of kernels shipped, this is probably the most popular use-case. With
> something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
> of code and data (and potentially bugs) that are not needed for their
> specific device.
Sure, but I think you're missing the point: This would be in addition
to the SoC specific options. Do you still see issues with that?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 19:18 ` Tony Lindgren
@ 2012-05-07 19:35 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 19:35 UTC (permalink / raw)
To: Paul Walmsley
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* Tony Lindgren <tony@atomide.com> [120507 12:22]:
> * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > Hi,
> >
> > On Fri, 4 May 2012, Tony Lindgren wrote:
> >
> > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > Then this becomes just:
> > >
> > > #ifdef CONFIG_SOC_OMAP3PLUS
> >
> > We might want to consider having separate CONFIG_SOC_* values for each
> > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > CONFIG_SOC_OMAP3630, etc.
>
> Hmm but this would be in addition to the SOC specific options. The goal
> is to cut down the ifdeffery needed all over the place to add new SoCs,
> see the experimental patch I posted:
>
> http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
Of course we could make this finer grained based on features
like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
grouping like that in mind.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-07 19:35 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 19:35 UTC (permalink / raw)
To: linux-arm-kernel
* Tony Lindgren <tony@atomide.com> [120507 12:22]:
> * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > Hi,
> >
> > On Fri, 4 May 2012, Tony Lindgren wrote:
> >
> > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > Then this becomes just:
> > >
> > > #ifdef CONFIG_SOC_OMAP3PLUS
> >
> > We might want to consider having separate CONFIG_SOC_* values for each
> > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > CONFIG_SOC_OMAP3630, etc.
>
> Hmm but this would be in addition to the SOC specific options. The goal
> is to cut down the ifdeffery needed all over the place to add new SoCs,
> see the experimental patch I posted:
>
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
Of course we could make this finer grained based on features
like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
grouping like that in mind.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 19:35 ` Tony Lindgren
@ 2012-05-08 5:32 ` Paul Walmsley
-1 siblings, 0 replies; 126+ messages in thread
From: Paul Walmsley @ 2012-05-08 5:32 UTC (permalink / raw)
To: Tony Lindgren
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
On Mon, 7 May 2012, Tony Lindgren wrote:
> Of course we could make this finer grained based on features
> like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> grouping like that in mind.
Yep, I like that idea.
- Paul
^ permalink raw reply [flat|nested] 126+ messages in thread
* RE: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 19:35 ` Tony Lindgren
@ 2012-05-08 5:49 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 126+ messages in thread
From: Hiremath, Vaibhav @ 2012-05-08 5:49 UTC (permalink / raw)
To: Tony Lindgren, Paul Walmsley
Cc: R, Sricharan, linux-omap, linux-arm-kernel, Shilimkar, Santosh,
Cousson, Benoit
On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > Hi,
> > >
> > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > >
> > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > Then this becomes just:
> > > >
> > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > >
> > > We might want to consider having separate CONFIG_SOC_* values for each
> > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > CONFIG_SOC_OMAP3630, etc.
> >
> > Hmm but this would be in addition to the SOC specific options. The goal
> > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > see the experimental patch I posted:
> >
> > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
>
> Of course we could make this finer grained based on features
> like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> grouping like that in mind.
>
This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 5:49 ` Hiremath, Vaibhav
0 siblings, 0 replies; 126+ messages in thread
From: Hiremath, Vaibhav @ 2012-05-08 5:49 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > Hi,
> > >
> > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > >
> > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > Then this becomes just:
> > > >
> > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > >
> > > We might want to consider having separate CONFIG_SOC_* values for each
> > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > CONFIG_SOC_OMAP3630, etc.
> >
> > Hmm but this would be in addition to the SOC specific options. The goal
> > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > see the experimental patch I posted:
> >
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
>
> Of course we could make this finer grained based on features
> like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> grouping like that in mind.
>
This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-08 5:49 ` Hiremath, Vaibhav
@ 2012-05-08 15:48 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:48 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Paul Walmsley, R, Sricharan, linux-omap, linux-arm-kernel,
Shilimkar, Santosh, Cousson, Benoit
* Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > Hi,
> > > >
> > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > >
> > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > Then this becomes just:
> > > > >
> > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > >
> > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > CONFIG_SOC_OMAP3630, etc.
> > >
> > > Hmm but this would be in addition to the SOC specific options. The goal
> > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > see the experimental patch I posted:
> > >
> > > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
> >
> > Of course we could make this finer grained based on features
> > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > grouping like that in mind.
> >
>
> This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
OK good, so now the question is just what groupings we need.. Got any
suggestions?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 15:48 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:48 UTC (permalink / raw)
To: linux-arm-kernel
* Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > Hi,
> > > >
> > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > >
> > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > Then this becomes just:
> > > > >
> > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > >
> > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > CONFIG_SOC_OMAP3630, etc.
> > >
> > > Hmm but this would be in addition to the SOC specific options. The goal
> > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > see the experimental patch I posted:
> > >
> > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
> >
> > Of course we could make this finer grained based on features
> > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > grouping like that in mind.
> >
>
> This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
OK good, so now the question is just what groupings we need.. Got any
suggestions?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* RE: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-08 15:48 ` Tony Lindgren
@ 2012-05-08 17:00 ` Hiremath, Vaibhav
-1 siblings, 0 replies; 126+ messages in thread
From: Hiremath, Vaibhav @ 2012-05-08 17:00 UTC (permalink / raw)
To: Tony Lindgren
Cc: Paul Walmsley, R, Sricharan, linux-omap, linux-arm-kernel,
Shilimkar, Santosh, Cousson, Benoit
On Tue, May 08, 2012 at 21:18:29, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> > On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > > Hi,
> > > > >
> > > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > > >
> > > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > > Then this becomes just:
> > > > > >
> > > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > > >
> > > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > > CONFIG_SOC_OMAP3630, etc.
> > > >
> > > > Hmm but this would be in addition to the SOC specific options. The goal
> > > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > > see the experimental patch I posted:
> > > >
> > > > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
> > >
> > > Of course we could make this finer grained based on features
> > > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > > grouping like that in mind.
> > >
> >
> > This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
>
> OK good, so now the question is just what groupings we need.. Got any
> suggestions?
>
Tony
I have submitted first round of cleanup patches in the same direction, can
you please take a look at them? Most of them are trivial and should be
considered for upstream.
I am trying to take cleanup thing one-by-one, and keep submitting them.
Please let me know if you have any suggestions or pointers for me.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 17:00 ` Hiremath, Vaibhav
0 siblings, 0 replies; 126+ messages in thread
From: Hiremath, Vaibhav @ 2012-05-08 17:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, May 08, 2012 at 21:18:29, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> > On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > > Hi,
> > > > >
> > > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > > >
> > > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > > Then this becomes just:
> > > > > >
> > > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > > >
> > > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > > CONFIG_SOC_OMAP3630, etc.
> > > >
> > > > Hmm but this would be in addition to the SOC specific options. The goal
> > > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > > see the experimental patch I posted:
> > > >
> > > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
> > >
> > > Of course we could make this finer grained based on features
> > > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > > grouping like that in mind.
> > >
> >
> > This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
>
> OK good, so now the question is just what groupings we need.. Got any
> suggestions?
>
Tony
I have submitted first round of cleanup patches in the same direction, can
you please take a look at them? Most of them are trivial and should be
considered for upstream.
I am trying to take cleanup thing one-by-one, and keep submitting them.
Please let me know if you have any suggestions or pointers for me.
Thanks,
Vaibhav
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-08 17:00 ` Hiremath, Vaibhav
@ 2012-05-08 19:07 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 19:07 UTC (permalink / raw)
To: Hiremath, Vaibhav
Cc: Paul Walmsley, R, Sricharan, linux-omap, linux-arm-kernel,
Shilimkar, Santosh, Cousson, Benoit
* Hiremath, Vaibhav <hvaibhav@ti.com> [120508 10:04]:
> On Tue, May 08, 2012 at 21:18:29, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> > > On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > > > Hi,
> > > > > >
> > > > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > > > >
> > > > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > > > Then this becomes just:
> > > > > > >
> > > > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > > > >
> > > > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > > > CONFIG_SOC_OMAP3630, etc.
> > > > >
> > > > > Hmm but this would be in addition to the SOC specific options. The goal
> > > > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > > > see the experimental patch I posted:
> > > > >
> > > > > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
> > > >
> > > > Of course we could make this finer grained based on features
> > > > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > > > grouping like that in mind.
> > > >
> > >
> > > This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
> >
> > OK good, so now the question is just what groupings we need.. Got any
> > suggestions?
> >
>
> Tony
>
> I have submitted first round of cleanup patches in the same direction, can
> you please take a look at them? Most of them are trivial and should be
> considered for upstream.
>
> I am trying to take cleanup thing one-by-one, and keep submitting them.
> Please let me know if you have any suggestions or pointers for me.
Yes looking good thanks, made few comments there as you noticed.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 19:07 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 19:07 UTC (permalink / raw)
To: linux-arm-kernel
* Hiremath, Vaibhav <hvaibhav@ti.com> [120508 10:04]:
> On Tue, May 08, 2012 at 21:18:29, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav@ti.com> [120507 22:52]:
> > > On Tue, May 08, 2012 at 01:05:01, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [120507 12:22]:
> > > > > * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > > > > > Hi,
> > > > > >
> > > > > > On Fri, 4 May 2012, Tony Lindgren wrote:
> > > > > >
> > > > > > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > > > > > Then this becomes just:
> > > > > > >
> > > > > > > #ifdef CONFIG_SOC_OMAP3PLUS
> > > > > >
> > > > > > We might want to consider having separate CONFIG_SOC_* values for each
> > > > > > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > > > > > CONFIG_SOC_OMAP3630, etc.
> > > > >
> > > > > Hmm but this would be in addition to the SOC specific options. The goal
> > > > > is to cut down the ifdeffery needed all over the place to add new SoCs,
> > > > > see the experimental patch I posted:
> > > > >
> > > > > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
> > > >
> > > > Of course we could make this finer grained based on features
> > > > like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some
> > > > grouping like that in mind.
> > > >
> > >
> > > This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.
> >
> > OK good, so now the question is just what groupings we need.. Got any
> > suggestions?
> >
>
> Tony
>
> I have submitted first round of cleanup patches in the same direction, can
> you please take a look at them? Most of them are trivial and should be
> considered for upstream.
>
> I am trying to take cleanup thing one-by-one, and keep submitting them.
> Please let me know if you have any suggestions or pointers for me.
Yes looking good thanks, made few comments there as you noticed.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-07 19:18 ` Tony Lindgren
@ 2012-05-08 5:31 ` Paul Walmsley
-1 siblings, 0 replies; 126+ messages in thread
From: Paul Walmsley @ 2012-05-08 5:31 UTC (permalink / raw)
To: Tony Lindgren
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
On Mon, 7 May 2012, Tony Lindgren wrote:
> * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > On Fri, 4 May 2012, Tony Lindgren wrote:
> >
> > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > Then this becomes just:
> > >
> > > #ifdef CONFIG_SOC_OMAP3PLUS
> >
> > We might want to consider having separate CONFIG_SOC_* values for each
> > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > CONFIG_SOC_OMAP3630, etc.
>
> Hmm but this would be in addition to the SOC specific options. The goal
> is to cut down the ifdeffery needed all over the place to add new SoCs,
> see the experimental patch I posted:
>
> http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
I see. Yeah, the problem is that it's hard to figure out which SoCs
should go into SOC_OMAP3PLUS. AM33xx? TI81xx? etc. Some of these chips
draw some aspects from chips that we've historically considered part of
OMAP3, and other aspects from OMAP4-style chips.
What seems better to me would be to use a more specific, IP block-focused
macro as needed. So to pick a random example, in mach-omap2/control.c, we
currently skip compilation of the scratchpad functions unless
CONFIG_ARCH_OMAP3 is defined. Instead of making this
SOC_OMAP3PLUS-dependent, or dependent on a mess of CONFIG_SOC_* macros,
maybe something like CONFIG_OMAP3430_SCM_SCRATCHPAD_FORMAT?
Of course, for some of these cases, maybe it makes more sense to move the
code out into a separate file, control-omap3-scratchpad.c or something,
and just conditionally compile it to avoid the #ifdefs.
> Just to continue exploring just using the SoC specific options, we would
> currently end up with more of this kind of nastiness:
>
> #if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> defined(CONFIG_ARCH_OMAP3))
Yep, agreed that we don't want that.
> > The other motivation would be to support device manufacturers who only
> > wish to build a kernel for the single device that they are shipping. In
> > terms of kernels shipped, this is probably the most popular use-case. With
> > something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
> > of code and data (and potentially bugs) that are not needed for their
> > specific device.
>
> Sure, but I think you're missing the point: This would be in addition
> to the SoC specific options. Do you still see issues with that?
Indeed, I misunderstood your proposal, sorry about that.
Anyway, to me it seems like it would be a little better to have CONFIG_*
macros that are specific to the IP block in question, only because of the
SoC grouping problem that I mentioned above.
- Paul
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 5:31 ` Paul Walmsley
0 siblings, 0 replies; 126+ messages in thread
From: Paul Walmsley @ 2012-05-08 5:31 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 7 May 2012, Tony Lindgren wrote:
> * Paul Walmsley <paul@pwsan.com> [120507 12:11]:
> > On Fri, 4 May 2012, Tony Lindgren wrote:
> >
> > > How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series?
> > > Then this becomes just:
> > >
> > > #ifdef CONFIG_SOC_OMAP3PLUS
> >
> > We might want to consider having separate CONFIG_SOC_* values for each
> > SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430,
> > CONFIG_SOC_OMAP3630, etc.
>
> Hmm but this would be in addition to the SOC specific options. The goal
> is to cut down the ifdeffery needed all over the place to add new SoCs,
> see the experimental patch I posted:
>
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
I see. Yeah, the problem is that it's hard to figure out which SoCs
should go into SOC_OMAP3PLUS. AM33xx? TI81xx? etc. Some of these chips
draw some aspects from chips that we've historically considered part of
OMAP3, and other aspects from OMAP4-style chips.
What seems better to me would be to use a more specific, IP block-focused
macro as needed. So to pick a random example, in mach-omap2/control.c, we
currently skip compilation of the scratchpad functions unless
CONFIG_ARCH_OMAP3 is defined. Instead of making this
SOC_OMAP3PLUS-dependent, or dependent on a mess of CONFIG_SOC_* macros,
maybe something like CONFIG_OMAP3430_SCM_SCRATCHPAD_FORMAT?
Of course, for some of these cases, maybe it makes more sense to move the
code out into a separate file, control-omap3-scratchpad.c or something,
and just conditionally compile it to avoid the #ifdefs.
> Just to continue exploring just using the SoC specific options, we would
> currently end up with more of this kind of nastiness:
>
> #if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
> defined(CONFIG_ARCH_OMAP3))
Yep, agreed that we don't want that.
> > The other motivation would be to support device manufacturers who only
> > wish to build a kernel for the single device that they are shipping. In
> > terms of kernels shipped, this is probably the most popular use-case. With
> > something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit
> > of code and data (and potentially bugs) that are not needed for their
> > specific device.
>
> Sure, but I think you're missing the point: This would be in addition
> to the SoC specific options. Do you still see issues with that?
Indeed, I misunderstood your proposal, sorry about that.
Anyway, to me it seems like it would be a little better to have CONFIG_*
macros that are specific to the IP block in question, only because of the
SoC grouping problem that I mentioned above.
- Paul
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-08 5:31 ` Paul Walmsley
@ 2012-05-08 15:47 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:47 UTC (permalink / raw)
To: Paul Walmsley
Cc: R Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* Paul Walmsley <paul@pwsan.com> [120507 22:35]:
> On Mon, 7 May 2012, Tony Lindgren wrote:
> >
> > http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67938.html
>
> I see. Yeah, the problem is that it's hard to figure out which SoCs
> should go into SOC_OMAP3PLUS. AM33xx? TI81xx? etc. Some of these chips
> draw some aspects from chips that we've historically considered part of
> OMAP3, and other aspects from OMAP4-style chips.
Yes agreed it should be finer grained and feature specific.
> What seems better to me would be to use a more specific, IP block-focused
> macro as needed. So to pick a random example, in mach-omap2/control.c, we
> currently skip compilation of the scratchpad functions unless
> CONFIG_ARCH_OMAP3 is defined. Instead of making this
> SOC_OMAP3PLUS-dependent, or dependent on a mess of CONFIG_SOC_* macros,
> maybe something like CONFIG_OMAP3430_SCM_SCRATCHPAD_FORMAT?
Yes that makes sense. How about let's standardize on naming like
SOC_HAS_OMAP3430_SCM_SCRATCHPAD_FORMAT?
We already have similar naming for generic things like ARCH_HAS_XYZ.
> Of course, for some of these cases, maybe it makes more sense to move the
> code out into a separate file, control-omap3-scratchpad.c or something,
> and just conditionally compile it to avoid the #ifdefs.
Agreed.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-08 15:47 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:47 UTC (permalink / raw)
To: linux-arm-kernel
* Paul Walmsley <paul@pwsan.com> [120507 22:35]:
> On Mon, 7 May 2012, Tony Lindgren wrote:
> >
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html
>
> I see. Yeah, the problem is that it's hard to figure out which SoCs
> should go into SOC_OMAP3PLUS. AM33xx? TI81xx? etc. Some of these chips
> draw some aspects from chips that we've historically considered part of
> OMAP3, and other aspects from OMAP4-style chips.
Yes agreed it should be finer grained and feature specific.
> What seems better to me would be to use a more specific, IP block-focused
> macro as needed. So to pick a random example, in mach-omap2/control.c, we
> currently skip compilation of the scratchpad functions unless
> CONFIG_ARCH_OMAP3 is defined. Instead of making this
> SOC_OMAP3PLUS-dependent, or dependent on a mess of CONFIG_SOC_* macros,
> maybe something like CONFIG_OMAP3430_SCM_SCRATCHPAD_FORMAT?
Yes that makes sense. How about let's standardize on naming like
SOC_HAS_OMAP3430_SCM_SCRATCHPAD_FORMAT?
We already have similar naming for generic things like ARCH_HAS_XYZ.
> Of course, for some of these cases, maybe it makes more sense to move the
> code out into a separate file, control-omap3-scratchpad.c or something,
> and just conditionally compile it to avoid the #ifdefs.
Agreed.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
2012-05-03 7:26 ` R Sricharan
@ 2012-05-10 11:58 ` Roger Quadros
-1 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:58 UTC (permalink / raw)
To: R Sricharan
Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, tony, b-cousson
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
> OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
> architecture. It's a dual core SOC with GIC used for interrupt
> handling and with an integrated L2 cache controller.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
> Patch includes:
> - The machine specific headers and sources updates.
> - Platform header updates.
> - Minimum initialisation support for serial.
> - IO table init
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 26 ++++++++++----
> arch/arm/mach-omap2/clock.c | 3 +-
> arch/arm/mach-omap2/cminst44xx.h | 2 +-
> arch/arm/mach-omap2/common.c | 24 +++++++++++++
> arch/arm/mach-omap2/common.h | 11 ++++++
> arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--
> arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++
> arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++
> arch/arm/mach-omap2/prcm.c | 2 +-
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 ++-
> arch/arm/plat-omap/Makefile | 4 +--
> arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
> arch/arm/plat-omap/include/plat/clock.h | 4 ++-
> arch/arm/plat-omap/include/plat/hardware.h | 1 +
> arch/arm/plat-omap/include/plat/multi.h | 9 +++++
> arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++
> arch/arm/plat-omap/include/plat/serial.h | 10 +++++
> arch/arm/plat-omap/include/plat/uncompress.h | 6 +++
> arch/arm/plat-omap/sram.c | 11 +++++-
> 19 files changed, 208 insertions(+), 22 deletions(-)
> create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 669e2b1..fbb6b3d 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
> obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
>
> ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
> obj-y += mcbsp.o
> @@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
>
> obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
> -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
> +omap-4-5-common = omap4-common.o omap-wakeupgen.o \
> + sleep44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
>
> plus_sec := $(call as-instr,.arch_extension sec,+sec)
> AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> +obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
> obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
> obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
> @@ -87,9 +91,11 @@ obj-y += prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
> +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
> + prcm_mpu44xx.o prminst44xx.o \
> + vc44xx_data.o vp44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
>
> # OMAP voltage domains
> voltagedomain-common := voltage.o vc.o vp.o
> @@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> powerdomain-common += powerdomain.o powerdomain-common.o
> @@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
>
> # PRCM clockdomain control
> obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
> @@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> +omap-clock-4-5-common = clockdomain.o \
> + clockdomain44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
>
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> @@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
> obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
> +obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
>
> # OMAP2 clock rate set data (old "OPP" data)
> obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index d9f4931..c589bb8 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
>
> /* OMAP3/4 non-CORE DPLL clkops */
>
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> + defined(CONFIG_ARCH_OMAP5)
>
> const struct clkops clkops_omap3_noncore_dpll_ops = {
> .enable = omap3_noncore_dpll_enable,
> diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
> index a018a73..da67e08 100644
> --- a/arch/arm/mach-omap2/cminst44xx.h
> +++ b/arch/arm/mach-omap2/cminst44xx.h
> @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
>
> extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
>
> -# ifdef CONFIG_ARCH_OMAP4
> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> u16 clkctrl_offs);
>
> diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
> index 8a6953a..a0e74b9 100644
> --- a/arch/arm/mach-omap2/common.c
> +++ b/arch/arm/mach-omap2/common.c
> @@ -182,3 +182,27 @@ void __init omap4_map_io(void)
> }
> #endif
>
> +#if defined(CONFIG_ARCH_OMAP5)
> +static struct omap_globals omap5_globals = {
> + .class = OMAP54XX_CLASS,
> + .tap = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
> + .ctrl = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
> + .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP543x_CTRL_BASE),
> + .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
> + .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
> + .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
> + .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
Might not be for this patch but just wondering why some register names
are prefixed with OMAP543x whereas others are OMAP54XX.
e.g. will SCM_BASE be different for a different OMAP5 device?
> +};
> +
> +void __init omap2_set_globals_543x(void)
> +{
> + omap2_set_globals_tap(&omap5_globals);
> + omap2_set_globals_control(&omap5_globals);
> + omap2_set_globals_prcm(&omap5_globals);
> +}
> +
> +void __init omap5_map_io(void)
> +{
> + omap5_map_common_io();
> +}
> +#endif
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0672fc5..797dda7 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
> }
> #endif
>
> +#ifdef CONFIG_ARCH_OMAP5
> +extern void omap5_map_common_io(void);
> +#else
> +static inline void omap5_map_common_io(void)
> +{
> +}
nit-pick
static inline void omap5_map_common_io(void) {}
> +#endif
> +
> extern void omap2_init_common_infrastructure(void);
>
> extern struct sys_timer omap2_timer;
> @@ -94,6 +102,7 @@ void omap3_init_early(void); /* Do not use this one */
> void am35xx_init_early(void);
> void ti81xx_init_early(void);
> void omap4430_init_early(void);
> +void omap5_init_early(void);
> void omap_prcm_restart(char, const char *);
>
> /*
> @@ -118,6 +127,7 @@ void omap2_set_globals_242x(void);
> void omap2_set_globals_243x(void);
> void omap2_set_globals_3xxx(void);
> void omap2_set_globals_443x(void);
> +void omap2_set_globals_543x(void);
It might be better to use 5xxx in the naming scheme instead of 543x as
it would be used for all OMAP5 devices.
> void omap2_set_globals_ti81xx(void);
> void omap2_set_globals_am33xx(void);
>
> @@ -132,6 +142,7 @@ void omap243x_map_io(void);
> void omap3_map_io(void);
> void am33xx_map_io(void);
> void omap4_map_io(void);
> +void omap5_map_io(void);
> void ti81xx_map_io(void);
> void omap_barriers_init(void);
<snip>
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 02/13] ARM: OMAP5: Add minimal support for OMAP5430 SOC
@ 2012-05-10 11:58 ` Roger Quadros
0 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
> OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
> architecture. It's a dual core SOC with GIC used for interrupt
> handling and with an integrated L2 cache controller.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
> Patch includes:
> - The machine specific headers and sources updates.
> - Platform header updates.
> - Minimum initialisation support for serial.
> - IO table init
>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 26 ++++++++++----
> arch/arm/mach-omap2/clock.c | 3 +-
> arch/arm/mach-omap2/cminst44xx.h | 2 +-
> arch/arm/mach-omap2/common.c | 24 +++++++++++++
> arch/arm/mach-omap2/common.h | 11 ++++++
> arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--
> arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++
> arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++
> arch/arm/mach-omap2/prcm.c | 2 +-
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 ++-
> arch/arm/plat-omap/Makefile | 4 +--
> arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
> arch/arm/plat-omap/include/plat/clock.h | 4 ++-
> arch/arm/plat-omap/include/plat/hardware.h | 1 +
> arch/arm/plat-omap/include/plat/multi.h | 9 +++++
> arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++
> arch/arm/plat-omap/include/plat/serial.h | 10 +++++
> arch/arm/plat-omap/include/plat/uncompress.h | 6 +++
> arch/arm/plat-omap/sram.c | 11 +++++-
> 19 files changed, 208 insertions(+), 22 deletions(-)
> create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 669e2b1..fbb6b3d 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o
> obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
> obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
> obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
> +obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
>
> ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
> obj-y += mcbsp.o
> @@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
>
> obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
> -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
> -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
> +omap-4-5-common = omap4-common.o omap-wakeupgen.o \
> + sleep44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-common)
>
> plus_sec := $(call as-instr,.arch_extension sec,+sec)
> AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
> @@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> +obj-$(CONFIG_ARCH_OMAP5) += omap-mpuss-lowpower.o
> obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
> obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
> @@ -87,9 +91,11 @@ obj-y += prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
> -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
> +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
> + prcm_mpu44xx.o prminst44xx.o \
> + vc44xx_data.o vp44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-prcm-4-5-common)
>
> # OMAP voltage domains
> voltagedomain-common := voltage.o vc.o vp.o
> @@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(voltagedomain-common)
>
> # OMAP powerdomain framework
> powerdomain-common += powerdomain.o powerdomain-common.o
> @@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
> obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(powerdomain-common) powerdomain44xx.o
>
> # PRCM clockdomain control
> obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o
> @@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> +omap-clock-4-5-common = clockdomain.o \
> + clockdomain44xx.o
> +obj-$(CONFIG_ARCH_OMAP4) += $(omap-clock-4-5-common)
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(omap-clock-4-5-common)
>
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> @@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
> obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
> +obj-$(CONFIG_ARCH_OMAP5) += $(clock-common)
> +obj-$(CONFIG_ARCH_OMAP5) += dpll3xxx.o dpll44xx.o
>
> # OMAP2 clock rate set data (old "OPP" data)
> obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index d9f4931..c589bb8 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
>
> /* OMAP3/4 non-CORE DPLL clkops */
>
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
> + defined(CONFIG_ARCH_OMAP5)
>
> const struct clkops clkops_omap3_noncore_dpll_ops = {
> .enable = omap3_noncore_dpll_enable,
> diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
> index a018a73..da67e08 100644
> --- a/arch/arm/mach-omap2/cminst44xx.h
> +++ b/arch/arm/mach-omap2/cminst44xx.h
> @@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
>
> extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
>
> -# ifdef CONFIG_ARCH_OMAP4
> +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
> extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
> u16 clkctrl_offs);
>
> diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
> index 8a6953a..a0e74b9 100644
> --- a/arch/arm/mach-omap2/common.c
> +++ b/arch/arm/mach-omap2/common.c
> @@ -182,3 +182,27 @@ void __init omap4_map_io(void)
> }
> #endif
>
> +#if defined(CONFIG_ARCH_OMAP5)
> +static struct omap_globals omap5_globals = {
> + .class = OMAP54XX_CLASS,
> + .tap = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
> + .ctrl = OMAP2_L4_IO_ADDRESS(OMAP543x_SCM_BASE),
> + .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP543x_CTRL_BASE),
> + .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
> + .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
> + .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
> + .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
Might not be for this patch but just wondering why some register names
are prefixed with OMAP543x whereas others are OMAP54XX.
e.g. will SCM_BASE be different for a different OMAP5 device?
> +};
> +
> +void __init omap2_set_globals_543x(void)
> +{
> + omap2_set_globals_tap(&omap5_globals);
> + omap2_set_globals_control(&omap5_globals);
> + omap2_set_globals_prcm(&omap5_globals);
> +}
> +
> +void __init omap5_map_io(void)
> +{
> + omap5_map_common_io();
> +}
> +#endif
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0672fc5..797dda7 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
> }
> #endif
>
> +#ifdef CONFIG_ARCH_OMAP5
> +extern void omap5_map_common_io(void);
> +#else
> +static inline void omap5_map_common_io(void)
> +{
> +}
nit-pick
static inline void omap5_map_common_io(void) {}
> +#endif
> +
> extern void omap2_init_common_infrastructure(void);
>
> extern struct sys_timer omap2_timer;
> @@ -94,6 +102,7 @@ void omap3_init_early(void); /* Do not use this one */
> void am35xx_init_early(void);
> void ti81xx_init_early(void);
> void omap4430_init_early(void);
> +void omap5_init_early(void);
> void omap_prcm_restart(char, const char *);
>
> /*
> @@ -118,6 +127,7 @@ void omap2_set_globals_242x(void);
> void omap2_set_globals_243x(void);
> void omap2_set_globals_3xxx(void);
> void omap2_set_globals_443x(void);
> +void omap2_set_globals_543x(void);
It might be better to use 5xxx in the naming scheme instead of 543x as
it would be used for all OMAP5 devices.
> void omap2_set_globals_ti81xx(void);
> void omap2_set_globals_am33xx(void);
>
> @@ -132,6 +142,7 @@ void omap243x_map_io(void);
> void omap3_map_io(void);
> void am33xx_map_io(void);
> void omap4_map_io(void);
> +void omap5_map_io(void);
> void ti81xx_map_io(void);
> void omap_barriers_init(void);
<snip>
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 03/13] TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Not for merge.
Adding the cpu_is_omap54xx checks at relevant places
for that part of code to execute on OMAP5 socs as well.
This patch will no longer be needed once rebased on
top of below series from Kevin Hilman <khilman@ti.com>
http://www.spinics.net/lists/linux-omap/msg69013.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7144ae6..4063a8c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1221,7 +1221,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
oh->prcm.omap2.idlest_reg_id,
oh->prcm.omap2.idlest_idle_bit);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
if (!oh->clkdm)
return -EINVAL;
@@ -1291,13 +1291,16 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift);
- else if (cpu_is_omap44xx())
+ else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
return omap4_prminst_assert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs);
- else
+ } else {
return -EINVAL;
+ }
+
+ return ret;
}
/**
@@ -1326,9 +1329,9 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift,
ohri.st_shift);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
if (ohri.st_shift)
- pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+ pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4+ does not support st_shift\n",
oh->name, name);
ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
@@ -1367,7 +1370,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
ohri.st_shift);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 03/13] TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Not for merge.
Adding the cpu_is_omap54xx checks at relevant places
for that part of code to execute on OMAP5 socs as well.
This patch will no longer be needed once rebased on
top of below series from Kevin Hilman <khilman@ti.com>
http://www.spinics.net/lists/linux-omap/msg69013.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 15 +++++++++------
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7144ae6..4063a8c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1221,7 +1221,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
oh->prcm.omap2.idlest_reg_id,
oh->prcm.omap2.idlest_idle_bit);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
if (!oh->clkdm)
return -EINVAL;
@@ -1291,13 +1291,16 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift);
- else if (cpu_is_omap44xx())
+ else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
return omap4_prminst_assert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs);
- else
+ } else {
return -EINVAL;
+ }
+
+ return ret;
}
/**
@@ -1326,9 +1329,9 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift,
ohri.st_shift);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
if (ohri.st_shift)
- pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+ pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4+ does not support st_shift\n",
oh->name, name);
ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
@@ -1367,7 +1370,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
ohri.st_shift);
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 04/13] ARM: OMAP5: timer: Add clocksource, clockevent support
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/timer.c | 5 +++++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 797dda7..88fb577 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -92,6 +92,7 @@ extern struct sys_timer omap2_timer;
extern struct sys_timer omap3_timer;
extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap4_timer;
+extern struct sys_timer omap5_timer;
void omap2420_init_early(void);
void omap2430_init_early(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac..3262ad6 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -348,6 +348,11 @@ static void __init omap4_timer_init(void)
OMAP_SYS_TIMER(4)
#endif
+#ifdef CONFIG_ARCH_OMAP5
+OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(5)
+#endif
+
/**
* omap2_dm_timer_set_src - change the timer input clock source
* @pdev: timer platform device pointer
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 04/13] ARM: OMAP5: timer: Add clocksource, clockevent support
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/timer.c | 5 +++++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 797dda7..88fb577 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -92,6 +92,7 @@ extern struct sys_timer omap2_timer;
extern struct sys_timer omap3_timer;
extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap4_timer;
+extern struct sys_timer omap5_timer;
void omap2420_init_early(void);
void omap2430_init_early(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac..3262ad6 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -348,6 +348,11 @@ static void __init omap4_timer_init(void)
OMAP_SYS_TIMER(4)
#endif
+#ifdef CONFIG_ARCH_OMAP5
+OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(5)
+#endif
+
/**
* omap2_dm_timer_set_src - change the timer input clock source
* @pdev: timer platform device pointer
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 05/13] TEMP: ARM: OMAP5: Update the base address of the 32k-counter.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Not for merge.
Just update the base address of the counter for
OMAP5 soc.
This patch will no longer be needed after rebasing on top of below
series from Vaibhav Hiremath <hvaibhav@ti.com>.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67166.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/plat-omap/counter_32k.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5068fe5..5a48ec9 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -90,6 +90,8 @@ int __init omap_init_clocksource_32k(void)
pbase = OMAP3430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap44xx())
pbase = OMAP4430_32KSYNCT_BASE + 0x10;
+ else if (cpu_is_omap54xx())
+ pbase = OMAP54XX_32KSYNCT_BASE + 0x30;
else
return -ENODEV;
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 05/13] TEMP: ARM: OMAP5: Update the base address of the 32k-counter.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Not for merge.
Just update the base address of the counter for
OMAP5 soc.
This patch will no longer be needed after rebasing on top of below
series from Vaibhav Hiremath <hvaibhav@ti.com>.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/plat-omap/counter_32k.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5068fe5..5a48ec9 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -90,6 +90,8 @@ int __init omap_init_clocksource_32k(void)
pbase = OMAP3430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap44xx())
pbase = OMAP4430_32KSYNCT_BASE + 0x10;
+ else if (cpu_is_omap54xx())
+ pbase = OMAP54XX_32KSYNCT_BASE + 0x30;
else
return -ENODEV;
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 06/13] ARM: OMAP5: gpmc: Update gpmc_init()
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/gpmc.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..2f8f915 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -713,7 +713,8 @@ static int __init gpmc_init(void)
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
gpmc_irq = INT_34XX_GPMC_IRQ;
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
+ /* Base address and irq number are same for OMAP4/5 */
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
gpmc_irq = OMAP44XX_IRQ_GPMC;
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 06/13] ARM: OMAP5: gpmc: Update gpmc_init()
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/gpmc.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..2f8f915 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -713,7 +713,8 @@ static int __init gpmc_init(void)
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
gpmc_irq = INT_34XX_GPMC_IRQ;
- } else if (cpu_is_omap44xx()) {
+ } else if (cpu_is_omap44xx() || cpu_is_omap54xx()) {
+ /* Base address and irq number are same for OMAP4/5 */
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
gpmc_irq = OMAP44XX_IRQ_GPMC;
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
The l3 interconnect ip is same for OMAP4 and OMAP5.
So reuse the l3 error handler error code for OMAP5
as well. Also a few targets has been newly added for
OMAP5. So updating the driver for that here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/devices.c | 2 +-
arch/arm/mach-omap2/omap_l3_noc.h | 22 ++++++++++++++++++----
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fbb6b3d..9f554e3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -183,6 +183,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
# L3 interconnect
obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
+obj-$(CONFIG_ARCH_OMAP5) += omap_l3_noc.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e433603..a1b539a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -85,7 +85,7 @@ static int __init omap4_l3_init(void)
* To avoid code running on other OMAPs in
* multi-omap builds
*/
- if (!(cpu_is_omap44xx()))
+ if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 90b5098..a6ce34d 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
0x200, /* DMM2 */
0x300, /* ABE */
0x400, /* L4CFG */
- 0x600 /* CLK2 PWR DISC */
+ 0x600, /* CLK2 PWR DISC */
+ 0x0, /* Host CLK1 */
+ 0x900 /* L4 Wakeup */
};
static u32 l3_targ_inst_clk2[] = {
@@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
0xE00, /* missing in TRM corresponds to AES2*/
0xC00, /* L4 PER3 */
0xA00, /* L4 PER1*/
- 0xB00 /* L4 PER2*/
+ 0xB00, /* L4 PER2*/
+ 0x0, /* HOST CLK2 */
+ 0x1800, /* CAL */
+ 0x1700 /* LLI */
};
static u32 l3_targ_inst_clk3[] = {
- 0x0100 /* EMUSS */
+ 0x0100 /* EMUSS */,
+ 0x0300, /* DEBUGSS_CT_TBR */
+ 0x0 /* HOST CLK3 */
};
static struct l3_masters_data {
@@ -110,13 +117,15 @@ static struct l3_masters_data {
{ 0xC8, "USBHOSTFS"}
};
-static char *l3_targ_inst_name[L3_MODULES][18] = {
+static char *l3_targ_inst_name[L3_MODULES][21] = {
{
"DMM1",
"DMM2",
"ABE",
"L4CFG",
"CLK2 PWR DISC",
+ "HOST CLK1",
+ "L4 WAKEUP"
},
{
"CORTEX M3" ,
@@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
"L4 PER3",
"L4 PER1",
"L4 PER2",
+ "HOST CLK2",
+ "CAL",
+ "LLI"
},
{
"EMUSS",
+ "DEBUG SOURCE",
+ "HOST CLK3"
},
};
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
The l3 interconnect ip is same for OMAP4 and OMAP5.
So reuse the l3 error handler error code for OMAP5
as well. Also a few targets has been newly added for
OMAP5. So updating the driver for that here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/devices.c | 2 +-
arch/arm/mach-omap2/omap_l3_noc.h | 22 ++++++++++++++++++----
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fbb6b3d..9f554e3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -183,6 +183,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
# L3 interconnect
obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
+obj-$(CONFIG_ARCH_OMAP5) += omap_l3_noc.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e433603..a1b539a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -85,7 +85,7 @@ static int __init omap4_l3_init(void)
* To avoid code running on other OMAPs in
* multi-omap builds
*/
- if (!(cpu_is_omap44xx()))
+ if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 90b5098..a6ce34d 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
0x200, /* DMM2 */
0x300, /* ABE */
0x400, /* L4CFG */
- 0x600 /* CLK2 PWR DISC */
+ 0x600, /* CLK2 PWR DISC */
+ 0x0, /* Host CLK1 */
+ 0x900 /* L4 Wakeup */
};
static u32 l3_targ_inst_clk2[] = {
@@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
0xE00, /* missing in TRM corresponds to AES2*/
0xC00, /* L4 PER3 */
0xA00, /* L4 PER1*/
- 0xB00 /* L4 PER2*/
+ 0xB00, /* L4 PER2*/
+ 0x0, /* HOST CLK2 */
+ 0x1800, /* CAL */
+ 0x1700 /* LLI */
};
static u32 l3_targ_inst_clk3[] = {
- 0x0100 /* EMUSS */
+ 0x0100 /* EMUSS */,
+ 0x0300, /* DEBUGSS_CT_TBR */
+ 0x0 /* HOST CLK3 */
};
static struct l3_masters_data {
@@ -110,13 +117,15 @@ static struct l3_masters_data {
{ 0xC8, "USBHOSTFS"}
};
-static char *l3_targ_inst_name[L3_MODULES][18] = {
+static char *l3_targ_inst_name[L3_MODULES][21] = {
{
"DMM1",
"DMM2",
"ABE",
"L4CFG",
"CLK2 PWR DISC",
+ "HOST CLK1",
+ "L4 WAKEUP"
},
{
"CORTEX M3" ,
@@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
"L4 PER3",
"L4 PER1",
"L4 PER2",
+ "HOST CLK2",
+ "CAL",
+ "LLI"
},
{
"EMUSS",
+ "DEBUG SOURCE",
+ "HOST CLK3"
},
};
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-04 22:51 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:51 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -85,7 +85,7 @@ static int __init omap4_l3_init(void)
> * To avoid code running on other OMAPs in
> * multi-omap builds
> */
> - if (!(cpu_is_omap44xx()))
> + if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
> return -ENODEV;
>
> for (i = 0; i < L3_MODULES; i++) {
Isn't there some unnecessary parens here?
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
@ 2012-05-04 22:51 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:51 UTC (permalink / raw)
To: linux-arm-kernel
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -85,7 +85,7 @@ static int __init omap4_l3_init(void)
> * To avoid code running on other OMAPs in
> * multi-omap builds
> */
> - if (!(cpu_is_omap44xx()))
> + if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
> return -ENODEV;
>
> for (i = 0; i < L3_MODULES; i++) {
Isn't there some unnecessary parens here?
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
2012-05-04 22:51 ` Tony Lindgren
@ 2012-05-06 7:38 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-06 7:38 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Hi Tony,
>> - if (!(cpu_is_omap44xx()))
>> + if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
>> return -ENODEV;
>>
>> for (i = 0; i < L3_MODULES; i++) {
>
> Isn't there some unnecessary parens here?
You mean in this above for loop?.
There are multiple statements .
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
@ 2012-05-06 7:38 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-06 7:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
>> - ? ? if (!(cpu_is_omap44xx()))
>> + ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
>> ? ? ? ? ? ? ? return -ENODEV;
>>
>> ? ? ? for (i = 0; i < L3_MODULES; i++) {
>
> Isn't there some unnecessary parens here?
You mean in this above for loop?.
There are multiple statements .
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
2012-05-06 7:38 ` R, Sricharan
@ 2012-05-07 17:34 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:34 UTC (permalink / raw)
To: R, Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R, Sricharan <r.sricharan@ti.com> [120506 00:42]:
> Hi Tony,
>
> >> - if (!(cpu_is_omap44xx()))
> >> + if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
> >> return -ENODEV;
> >>
> >> for (i = 0; i < L3_MODULES; i++) {
> >
> > Isn't there some unnecessary parens here?
>
> You mean in this above for loop?.
> There are multiple statements .
No, both the old (!(cpu_is_omap44xx())) and the added one.
Tony
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
@ 2012-05-07 17:34 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:34 UTC (permalink / raw)
To: linux-arm-kernel
* R, Sricharan <r.sricharan@ti.com> [120506 00:42]:
> Hi Tony,
>
> >> - ? ? if (!(cpu_is_omap44xx()))
> >> + ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
> >> ? ? ? ? ? ? ? return -ENODEV;
> >>
> >> ? ? ? for (i = 0; i < L3_MODULES; i++) {
> >
> > Isn't there some unnecessary parens here?
>
> You mean in this above for loop?.
> There are multiple statements .
No, both the old (!(cpu_is_omap44xx())) and the added one.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
2012-05-07 17:34 ` Tony Lindgren
@ 2012-05-08 6:04 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-08 6:04 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Tony,
On Mon, May 7, 2012 at 11:04 PM, Tony Lindgren <tony@atomide.com> wrote:
> * R, Sricharan <r.sricharan@ti.com> [120506 00:42]:
>> Hi Tony,
>>
>> >> - if (!(cpu_is_omap44xx()))
>> >> + if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
>> >> return -ENODEV;
>> >>
>> >> for (i = 0; i < L3_MODULES; i++) {
>> >
>> > Isn't there some unnecessary parens here?
>>
>> You mean in this above for loop?.
>> There are multiple statements .
>
> No, both the old (!(cpu_is_omap44xx())) and the added one.
>
oh ok, will remove those extra ones. Thanks.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 07/13] ARM: OMAP5: l3: Add l3 error handler support for omap5.
@ 2012-05-08 6:04 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-08 6:04 UTC (permalink / raw)
To: linux-arm-kernel
Tony,
On Mon, May 7, 2012 at 11:04 PM, Tony Lindgren <tony@atomide.com> wrote:
> * R, Sricharan <r.sricharan@ti.com> [120506 00:42]:
>> Hi Tony,
>>
>> >> - ? ? if (!(cpu_is_omap44xx()))
>> >> + ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx()))
>> >> ? ? ? ? ? ? ? return -ENODEV;
>> >>
>> >> ? ? ? for (i = 0; i < L3_MODULES; i++) {
>> >
>> > Isn't there some unnecessary parens here?
>>
>> ?You mean in this above for loop?.
>> ?There are multiple statements .
>
> No, both the old (!(cpu_is_omap44xx())) and the added one.
>
oh ok, will remove those extra ones. Thanks.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
arch/arm/mach-omap2/omap-smp.c | 19 +++-
arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
5 files changed, 135 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index 548de90..4d700bc 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -11,15 +11,20 @@
#ifndef OMAP_ARCH_WAKEUPGEN_H
#define OMAP_ARCH_WAKEUPGEN_H
+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE 0x48281000
+
#define OMAP_WKG_CONTROL_0 0x00
#define OMAP_WKG_ENB_A_0 0x10
#define OMAP_WKG_ENB_B_0 0x14
#define OMAP_WKG_ENB_C_0 0x18
#define OMAP_WKG_ENB_D_0 0x1c
+#define OMAP_WKG_ENB_E_0 0x20
#define OMAP_WKG_ENB_A_1 0x410
#define OMAP_WKG_ENB_B_1 0x414
#define OMAP_WKG_ENB_C_1 0x418
#define OMAP_WKG_ENB_D_1 0x41c
+#define OMAP_WKG_ENB_E_1 0x420
#define OMAP_AUX_CORE_BOOT_0 0x800
#define OMAP_AUX_CORE_BOOT_1 0x804
#define OMAP_PTMSYNCREQ_MASK 0xc00
@@ -28,4 +33,5 @@
#define OMAP_TIMESTAMPCYCLEHI 0xc0c
extern int __init omap_wakeupgen_init(void);
+extern void __iomem *omap_get_wakeupgen_base(void);
#endif
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 56c345b..052303c 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
+#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
#include "common.h"
@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
*/
void __ref platform_cpu_die(unsigned int cpu)
{
- unsigned int this_cpu;
+ unsigned int boot_cpu = 0;
+ void __iomem *base = omap_get_wakeupgen_base();
flush_cache_all();
dsb();
@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
/*
* we're ready for shutdown now, so do it
*/
- if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
- pr_err("Secure clear status failed\n");
+ if (cpu_is_omap44xx()) {
+ if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+ pr_err("Secure clear status failed\n");
+ } else {
+ __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+ }
+
for (;;) {
/*
* Enter into low power state
*/
omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
- this_cpu = smp_processor_id();
- if (omap_read_auxcoreboot0() == this_cpu) {
+
+ if (cpu_is_omap44xx())
+ boot_cpu = omap_read_auxcoreboot0();
+ else
+ boot_cpu =
+ __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+
+ if (boot_cpu == smp_processor_id()) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1..151fd5b 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,6 +26,8 @@
#include <mach/hardware.h>
#include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
#include "iomap.h"
#include "common.h"
@@ -73,6 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;
+ void __iomem *base = omap_get_wakeupgen_base();
+
/*
* Set synchronisation state between this boot processor
* and the secondary one
@@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained
*/
- omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+ if (cpu_is_omap44xx())
+ omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+ else
+ __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
flush_cache_all();
smp_wmb();
@@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void)
{
+ void __iomem *base = omap_get_wakeupgen_base();
+
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
- omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+ if (cpu_is_omap44xx())
+ omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+ else
+ __raw_writel(virt_to_phys(omap5_secondary_startup),
+ base + OMAP_AUX_CORE_BOOT_1);
+
smp_wmb();
/*
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb..444cf12 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -33,18 +33,22 @@
#include "omap4-sar-layout.h"
#include "common.h"
-#define NR_REG_BANKS 4
-#define MAX_IRQS 128
+#define MAX_NR_REG_BANKS 5
+#define MAX_IRQS 160
#define WKG_MASK_ALL 0x00000000
#define WKG_UNMASK_ALL 0xffffffff
#define CPU_ENA_OFFSET 0x400
#define CPU0_ID 0x0
#define CPU1_ID 0x1
+#define OMAP4_NR_BANKS 4
+#define OMAP4_NR_IRQS 128
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_banks = MAX_NR_REG_BANKS;
+static unsigned int max_irqs = MAX_IRQS;
/*
* Static helper functions.
@@ -146,13 +150,13 @@ static void wakeupgen_unmask(struct irq_data *d)
}
#ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
@@ -160,7 +164,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
@@ -168,7 +172,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
wakeupgen_writel(reg, i, cpu);
}
@@ -196,25 +200,11 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
#endif
#ifdef CONFIG_CPU_PM
-/*
- * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
- * ROM code. WakeupGen IP is integrated along with GIC to manage the
- * interrupt wakeups from CPU low power states. It manages
- * masking/unmasking of Shared peripheral interrupts(SPI). So the
- * interrupt enable/disable control should be in sync and consistent
- * at WakeupGen and GIC so that interrupts are not lost.
- */
-static void irq_save_context(void)
+static inline void omap4_irq_save_context(void)
{
u32 i, val;
- if (omap_rev() == OMAP4430_REV_ES1_0)
- return;
-
- if (!sar_base)
- sar_base = omap4_get_sar_ram_base();
-
- for (i = 0; i < NR_REG_BANKS; i++) {
+ for (i = 0; i < irq_banks; i++) {
/* Save the CPUx interrupt mask for IRQ 0 to 127 */
val = wakeupgen_readl(i, 0);
sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@@ -254,6 +244,53 @@ static void irq_save_context(void)
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+static inline void omap5_irq_save_context(void)
+{
+ u32 i, val;
+
+ for (i = 0; i < irq_banks; i++) {
+ /* Save the CPUx interrupt mask for IRQ 0 to 159 */
+ val = wakeupgen_readl(i, 0);
+ sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
+ val = wakeupgen_readl(i, 1);
+ sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
+ sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+ sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+ }
+
+ /* Save AuxBoot* registers */
+ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+
+ /* Set the Backup Bit Mask status */
+ val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+ val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+ __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+ if (!sar_base)
+ sar_base = omap4_get_sar_ram_base();
+
+ if (cpu_is_omap54xx())
+ omap5_irq_save_context();
+ else
+ omap4_irq_save_context();
}
/*
@@ -262,9 +299,14 @@ static void irq_save_context(void)
void irq_sar_clear(void)
{
u32 val;
- val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+ u32 offset = SAR_BACKUP_STATUS_OFFSET;
+
+ if (cpu_is_omap54xx())
+ offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
+
+ val = __raw_readl(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
- __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+ __raw_writel(val, sar_base + offset);
}
/*
@@ -336,13 +378,20 @@ static struct notifier_block irq_notifier_block = {
static void __init irq_pm_init(void)
{
- cpu_pm_register_notifier(&irq_notifier_block);
+ /* FIXME: Remove this when MPU OSWR support is added */
+ if (!cpu_is_omap54xx())
+ cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
{}
#endif
+void __iomem *omap_get_wakeupgen_base(void)
+{
+ return wakeupgen_base;
+}
+
/*
* Initialise the wakeupgen module.
*/
@@ -358,12 +407,17 @@ int __init omap_wakeupgen_init(void)
}
/* Static mapping, never released */
- wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+ wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
if (WARN_ON(!wakeupgen_base))
return -ENOMEM;
+ if (cpu_is_omap44xx()) {
+ irq_banks = OMAP4_NR_BANKS;
+ max_irqs = OMAP4_NR_IRQS;
+ }
+
/* Clear all IRQ bitmasks at wakeupGen level */
- for (i = 0; i < NR_REG_BANKS; i++) {
+ for (i = 0; i < irq_banks; i++) {
wakeupgen_writel(0, i, CPU0_ID);
wakeupgen_writel(0, i, CPU1_ID);
}
@@ -382,7 +436,7 @@ int __init omap_wakeupgen_init(void)
*/
/* Associate all the IRQs to boot CPU like GIC init does. */
- for (i = 0; i < NR_IRQS; i++)
+ for (i = 0; i < max_irqs; i++)
irq_target_cpu[i] = boot_cpu;
irq_hotplug_init();
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index fe5b545..e170fe8 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -12,7 +12,7 @@
#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
/*
- * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
*/
#define SAR_BANK1_OFFSET 0x0000
#define SAR_BANK2_OFFSET 0x1000
@@ -47,4 +47,14 @@
#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
+/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
+#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
+#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
+#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
+
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
arch/arm/mach-omap2/omap-smp.c | 19 +++-
arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
5 files changed, 135 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index 548de90..4d700bc 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -11,15 +11,20 @@
#ifndef OMAP_ARCH_WAKEUPGEN_H
#define OMAP_ARCH_WAKEUPGEN_H
+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE 0x48281000
+
#define OMAP_WKG_CONTROL_0 0x00
#define OMAP_WKG_ENB_A_0 0x10
#define OMAP_WKG_ENB_B_0 0x14
#define OMAP_WKG_ENB_C_0 0x18
#define OMAP_WKG_ENB_D_0 0x1c
+#define OMAP_WKG_ENB_E_0 0x20
#define OMAP_WKG_ENB_A_1 0x410
#define OMAP_WKG_ENB_B_1 0x414
#define OMAP_WKG_ENB_C_1 0x418
#define OMAP_WKG_ENB_D_1 0x41c
+#define OMAP_WKG_ENB_E_1 0x420
#define OMAP_AUX_CORE_BOOT_0 0x800
#define OMAP_AUX_CORE_BOOT_1 0x804
#define OMAP_PTMSYNCREQ_MASK 0xc00
@@ -28,4 +33,5 @@
#define OMAP_TIMESTAMPCYCLEHI 0xc0c
extern int __init omap_wakeupgen_init(void);
+extern void __iomem *omap_get_wakeupgen_base(void);
#endif
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 56c345b..052303c 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
+#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
#include "common.h"
@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
*/
void __ref platform_cpu_die(unsigned int cpu)
{
- unsigned int this_cpu;
+ unsigned int boot_cpu = 0;
+ void __iomem *base = omap_get_wakeupgen_base();
flush_cache_all();
dsb();
@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
/*
* we're ready for shutdown now, so do it
*/
- if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
- pr_err("Secure clear status failed\n");
+ if (cpu_is_omap44xx()) {
+ if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+ pr_err("Secure clear status failed\n");
+ } else {
+ __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+ }
+
for (;;) {
/*
* Enter into low power state
*/
omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
- this_cpu = smp_processor_id();
- if (omap_read_auxcoreboot0() == this_cpu) {
+
+ if (cpu_is_omap44xx())
+ boot_cpu = omap_read_auxcoreboot0();
+ else
+ boot_cpu =
+ __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+
+ if (boot_cpu == smp_processor_id()) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1..151fd5b 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,6 +26,8 @@
#include <mach/hardware.h>
#include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
#include "iomap.h"
#include "common.h"
@@ -73,6 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;
+ void __iomem *base = omap_get_wakeupgen_base();
+
/*
* Set synchronisation state between this boot processor
* and the secondary one
@@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained
*/
- omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+ if (cpu_is_omap44xx())
+ omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+ else
+ __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
flush_cache_all();
smp_wmb();
@@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void)
{
+ void __iomem *base = omap_get_wakeupgen_base();
+
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
- omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+ if (cpu_is_omap44xx())
+ omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+ else
+ __raw_writel(virt_to_phys(omap5_secondary_startup),
+ base + OMAP_AUX_CORE_BOOT_1);
+
smp_wmb();
/*
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb..444cf12 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -33,18 +33,22 @@
#include "omap4-sar-layout.h"
#include "common.h"
-#define NR_REG_BANKS 4
-#define MAX_IRQS 128
+#define MAX_NR_REG_BANKS 5
+#define MAX_IRQS 160
#define WKG_MASK_ALL 0x00000000
#define WKG_UNMASK_ALL 0xffffffff
#define CPU_ENA_OFFSET 0x400
#define CPU0_ID 0x0
#define CPU1_ID 0x1
+#define OMAP4_NR_BANKS 4
+#define OMAP4_NR_IRQS 128
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_banks = MAX_NR_REG_BANKS;
+static unsigned int max_irqs = MAX_IRQS;
/*
* Static helper functions.
@@ -146,13 +150,13 @@ static void wakeupgen_unmask(struct irq_data *d)
}
#ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
@@ -160,7 +164,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
@@ -168,7 +172,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
- for (i = 0; i < NR_REG_BANKS; i++)
+ for (i = 0; i < irq_banks; i++)
wakeupgen_writel(reg, i, cpu);
}
@@ -196,25 +200,11 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
#endif
#ifdef CONFIG_CPU_PM
-/*
- * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
- * ROM code. WakeupGen IP is integrated along with GIC to manage the
- * interrupt wakeups from CPU low power states. It manages
- * masking/unmasking of Shared peripheral interrupts(SPI). So the
- * interrupt enable/disable control should be in sync and consistent
- * at WakeupGen and GIC so that interrupts are not lost.
- */
-static void irq_save_context(void)
+static inline void omap4_irq_save_context(void)
{
u32 i, val;
- if (omap_rev() == OMAP4430_REV_ES1_0)
- return;
-
- if (!sar_base)
- sar_base = omap4_get_sar_ram_base();
-
- for (i = 0; i < NR_REG_BANKS; i++) {
+ for (i = 0; i < irq_banks; i++) {
/* Save the CPUx interrupt mask for IRQ 0 to 127 */
val = wakeupgen_readl(i, 0);
sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@@ -254,6 +244,53 @@ static void irq_save_context(void)
val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
val |= SAR_BACKUP_STATUS_WAKEUPGEN;
__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+static inline void omap5_irq_save_context(void)
+{
+ u32 i, val;
+
+ for (i = 0; i < irq_banks; i++) {
+ /* Save the CPUx interrupt mask for IRQ 0 to 159 */
+ val = wakeupgen_readl(i, 0);
+ sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
+ val = wakeupgen_readl(i, 1);
+ sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
+ sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+ sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+ }
+
+ /* Save AuxBoot* registers */
+ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+ __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+
+ /* Set the Backup Bit Mask status */
+ val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+ val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+ __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+ if (!sar_base)
+ sar_base = omap4_get_sar_ram_base();
+
+ if (cpu_is_omap54xx())
+ omap5_irq_save_context();
+ else
+ omap4_irq_save_context();
}
/*
@@ -262,9 +299,14 @@ static void irq_save_context(void)
void irq_sar_clear(void)
{
u32 val;
- val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+ u32 offset = SAR_BACKUP_STATUS_OFFSET;
+
+ if (cpu_is_omap54xx())
+ offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
+
+ val = __raw_readl(sar_base + offset);
val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
- __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+ __raw_writel(val, sar_base + offset);
}
/*
@@ -336,13 +378,20 @@ static struct notifier_block irq_notifier_block = {
static void __init irq_pm_init(void)
{
- cpu_pm_register_notifier(&irq_notifier_block);
+ /* FIXME: Remove this when MPU OSWR support is added */
+ if (!cpu_is_omap54xx())
+ cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
{}
#endif
+void __iomem *omap_get_wakeupgen_base(void)
+{
+ return wakeupgen_base;
+}
+
/*
* Initialise the wakeupgen module.
*/
@@ -358,12 +407,17 @@ int __init omap_wakeupgen_init(void)
}
/* Static mapping, never released */
- wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+ wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
if (WARN_ON(!wakeupgen_base))
return -ENOMEM;
+ if (cpu_is_omap44xx()) {
+ irq_banks = OMAP4_NR_BANKS;
+ max_irqs = OMAP4_NR_IRQS;
+ }
+
/* Clear all IRQ bitmasks@wakeupGen level */
- for (i = 0; i < NR_REG_BANKS; i++) {
+ for (i = 0; i < irq_banks; i++) {
wakeupgen_writel(0, i, CPU0_ID);
wakeupgen_writel(0, i, CPU1_ID);
}
@@ -382,7 +436,7 @@ int __init omap_wakeupgen_init(void)
*/
/* Associate all the IRQs to boot CPU like GIC init does. */
- for (i = 0; i < NR_IRQS; i++)
+ for (i = 0; i < max_irqs; i++)
irq_target_cpu[i] = boot_cpu;
irq_hotplug_init();
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index fe5b545..e170fe8 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -12,7 +12,7 @@
#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
/*
- * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
*/
#define SAR_BANK1_OFFSET 0x0000
#define SAR_BANK2_OFFSET 0x1000
@@ -47,4 +47,14 @@
#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
+/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
+#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
+#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
+#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
+
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-04 22:55 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:55 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/omap-hotplug.c
> +++ b/arch/arm/mach-omap2/omap-hotplug.c
> @@ -17,8 +17,10 @@
> #include <linux/kernel.h>
> #include <linux/errno.h>
> #include <linux/smp.h>
> +#include <linux/io.h>
>
> #include <asm/cacheflush.h>
> +#include <mach/omap-wakeupgen.h>
>
> #include "common.h"
>
> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
> */
> void __ref platform_cpu_die(unsigned int cpu)
> {
> - unsigned int this_cpu;
> + unsigned int boot_cpu = 0;
> + void __iomem *base = omap_get_wakeupgen_base();
>
> flush_cache_all();
> dsb();
> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
> /*
> * we're ready for shutdown now, so do it
> */
> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> - pr_err("Secure clear status failed\n");
> + if (cpu_is_omap44xx()) {
> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> + pr_err("Secure clear status failed\n");
> + } else {
> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
> + }
> +
>
> for (;;) {
> /*
> * Enter into low power state
> */
> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
> - this_cpu = smp_processor_id();
> - if (omap_read_auxcoreboot0() == this_cpu) {
> +
> + if (cpu_is_omap44xx())
> + boot_cpu = omap_read_auxcoreboot0();
> + else
> + boot_cpu =
> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
> +
> + if (boot_cpu == smp_processor_id()) {
> /*
> * OK, proper wakeup, we're done
> */
These should use variables set up during init instead of cpu_is_omapxxx
checks.
> @@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> * the AuxCoreBoot1 register is updated with cpu state
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + if (cpu_is_omap44xx())
> + omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + else
> + __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
> +
> flush_cache_all();
> smp_wmb();
>
> @@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> static void __init wakeup_secondary(void)
> {
> + void __iomem *base = omap_get_wakeupgen_base();
> +
> /*
> * Write the address of secondary startup routine into the
> * AuxCoreBoot1 where ROM code will jump and start executing
> * on secondary core once out of WFE
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + if (cpu_is_omap44xx())
> + omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + else
> + __raw_writel(virt_to_phys(omap5_secondary_startup),
> + base + OMAP_AUX_CORE_BOOT_1);
> +
> smp_wmb();
>
> /*
Probably these too could be set up during init while at it.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-04 22:55 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:55 UTC (permalink / raw)
To: linux-arm-kernel
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/omap-hotplug.c
> +++ b/arch/arm/mach-omap2/omap-hotplug.c
> @@ -17,8 +17,10 @@
> #include <linux/kernel.h>
> #include <linux/errno.h>
> #include <linux/smp.h>
> +#include <linux/io.h>
>
> #include <asm/cacheflush.h>
> +#include <mach/omap-wakeupgen.h>
>
> #include "common.h"
>
> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
> */
> void __ref platform_cpu_die(unsigned int cpu)
> {
> - unsigned int this_cpu;
> + unsigned int boot_cpu = 0;
> + void __iomem *base = omap_get_wakeupgen_base();
>
> flush_cache_all();
> dsb();
> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
> /*
> * we're ready for shutdown now, so do it
> */
> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> - pr_err("Secure clear status failed\n");
> + if (cpu_is_omap44xx()) {
> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> + pr_err("Secure clear status failed\n");
> + } else {
> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
> + }
> +
>
> for (;;) {
> /*
> * Enter into low power state
> */
> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
> - this_cpu = smp_processor_id();
> - if (omap_read_auxcoreboot0() == this_cpu) {
> +
> + if (cpu_is_omap44xx())
> + boot_cpu = omap_read_auxcoreboot0();
> + else
> + boot_cpu =
> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
> +
> + if (boot_cpu == smp_processor_id()) {
> /*
> * OK, proper wakeup, we're done
> */
These should use variables set up during init instead of cpu_is_omapxxx
checks.
> @@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> * the AuxCoreBoot1 register is updated with cpu state
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + if (cpu_is_omap44xx())
> + omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + else
> + __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
> +
> flush_cache_all();
> smp_wmb();
>
> @@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> static void __init wakeup_secondary(void)
> {
> + void __iomem *base = omap_get_wakeupgen_base();
> +
> /*
> * Write the address of secondary startup routine into the
> * AuxCoreBoot1 where ROM code will jump and start executing
> * on secondary core once out of WFE
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + if (cpu_is_omap44xx())
> + omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + else
> + __raw_writel(virt_to_phys(omap5_secondary_startup),
> + base + OMAP_AUX_CORE_BOOT_1);
> +
> smp_wmb();
>
> /*
Probably these too could be set up during init while at it.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-04 22:55 ` Tony Lindgren
@ 2012-05-07 9:06 ` Santosh Shilimkar
-1 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-07 9:06 UTC (permalink / raw)
To: Tony Lindgren; +Cc: R Sricharan, linux-omap, linux-arm-kernel, b-cousson
On Saturday 05 May 2012 04:25 AM, Tony Lindgren wrote:
> * R Sricharan <r.sricharan@ti.com> [120503 00:30]:
>> --- a/arch/arm/mach-omap2/omap-hotplug.c
>> +++ b/arch/arm/mach-omap2/omap-hotplug.c
>> @@ -17,8 +17,10 @@
>> #include <linux/kernel.h>
>> #include <linux/errno.h>
>> #include <linux/smp.h>
>> +#include <linux/io.h>
>>
>> #include <asm/cacheflush.h>
>> +#include <mach/omap-wakeupgen.h>
>>
>> #include "common.h"
>>
>> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
>> */
>> void __ref platform_cpu_die(unsigned int cpu)
>> {
>> - unsigned int this_cpu;
>> + unsigned int boot_cpu = 0;
>> + void __iomem *base = omap_get_wakeupgen_base();
>>
>> flush_cache_all();
>> dsb();
>> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
>> /*
>> * we're ready for shutdown now, so do it
>> */
>> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
>> - pr_err("Secure clear status failed\n");
>> + if (cpu_is_omap44xx()) {
>> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
>> + pr_err("Secure clear status failed\n");
>> + } else {
>> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
>> + }
>> +
>>
>> for (;;) {
>> /*
>> * Enter into low power state
>> */
>> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
>> - this_cpu = smp_processor_id();
>> - if (omap_read_auxcoreboot0() == this_cpu) {
>> +
>> + if (cpu_is_omap44xx())
>> + boot_cpu = omap_read_auxcoreboot0();
>> + else
>> + boot_cpu =
>> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
>> +
>> + if (boot_cpu == smp_processor_id()) {
>> /*
>> * OK, proper wakeup, we're done
>> */
>
> These should use variables set up during init instead of cpu_is_omapxxx
> checks.
>
Sounds good. Will fit it.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-07 9:06 ` Santosh Shilimkar
0 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-07 9:06 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 05 May 2012 04:25 AM, Tony Lindgren wrote:
> * R Sricharan <r.sricharan@ti.com> [120503 00:30]:
>> --- a/arch/arm/mach-omap2/omap-hotplug.c
>> +++ b/arch/arm/mach-omap2/omap-hotplug.c
>> @@ -17,8 +17,10 @@
>> #include <linux/kernel.h>
>> #include <linux/errno.h>
>> #include <linux/smp.h>
>> +#include <linux/io.h>
>>
>> #include <asm/cacheflush.h>
>> +#include <mach/omap-wakeupgen.h>
>>
>> #include "common.h"
>>
>> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
>> */
>> void __ref platform_cpu_die(unsigned int cpu)
>> {
>> - unsigned int this_cpu;
>> + unsigned int boot_cpu = 0;
>> + void __iomem *base = omap_get_wakeupgen_base();
>>
>> flush_cache_all();
>> dsb();
>> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
>> /*
>> * we're ready for shutdown now, so do it
>> */
>> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
>> - pr_err("Secure clear status failed\n");
>> + if (cpu_is_omap44xx()) {
>> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
>> + pr_err("Secure clear status failed\n");
>> + } else {
>> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
>> + }
>> +
>>
>> for (;;) {
>> /*
>> * Enter into low power state
>> */
>> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
>> - this_cpu = smp_processor_id();
>> - if (omap_read_auxcoreboot0() == this_cpu) {
>> +
>> + if (cpu_is_omap44xx())
>> + boot_cpu = omap_read_auxcoreboot0();
>> + else
>> + boot_cpu =
>> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
>> +
>> + if (boot_cpu == smp_processor_id()) {
>> /*
>> * OK, proper wakeup, we're done
>> */
>
> These should use variables set up during init instead of cpu_is_omapxxx
> checks.
>
Sounds good. Will fit it.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-10 11:36 ` Roger Quadros
-1 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:36 UTC (permalink / raw)
To: R Sricharan, santosh.shilimkar
Cc: linux-omap, linux-arm-kernel, tony, b-cousson
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
> - Additional 32 interrupt support is added w.r.t OMAP4 design.
> - The AUX CORE boot registers are now made accessible from non-secure SW.
> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>
> Patch updates the WakeupGen code accordingly.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
> arch/arm/mach-omap2/omap-smp.c | 19 +++-
> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
> 5 files changed, 135 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> index 548de90..4d700bc 100644
> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> @@ -11,15 +11,20 @@
> #ifndef OMAP_ARCH_WAKEUPGEN_H
> #define OMAP_ARCH_WAKEUPGEN_H
>
> +/* OMAP4 and OMAP5 has same base address */
> +#define OMAP_WKUPGEN_BASE 0x48281000
unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
define this in the same header as OMAP44XX_WKUPGEN_BASE?
> +
> #define OMAP_WKG_CONTROL_0 0x00
> #define OMAP_WKG_ENB_A_0 0x10
> #define OMAP_WKG_ENB_B_0 0x14
> #define OMAP_WKG_ENB_C_0 0x18
> #define OMAP_WKG_ENB_D_0 0x1c
> +#define OMAP_WKG_ENB_E_0 0x20
> #define OMAP_WKG_ENB_A_1 0x410
> #define OMAP_WKG_ENB_B_1 0x414
> #define OMAP_WKG_ENB_C_1 0x418
> #define OMAP_WKG_ENB_D_1 0x41c
> +#define OMAP_WKG_ENB_E_1 0x420
> #define OMAP_AUX_CORE_BOOT_0 0x800
> #define OMAP_AUX_CORE_BOOT_1 0x804
> #define OMAP_PTMSYNCREQ_MASK 0xc00
> @@ -28,4 +33,5 @@
> #define OMAP_TIMESTAMPCYCLEHI 0xc0c
>
> extern int __init omap_wakeupgen_init(void);
> +extern void __iomem *omap_get_wakeupgen_base(void);
> #endif
> diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
> index 56c345b..052303c 100644
> --- a/arch/arm/mach-omap2/omap-hotplug.c
> +++ b/arch/arm/mach-omap2/omap-hotplug.c
> @@ -17,8 +17,10 @@
> #include <linux/kernel.h>
> #include <linux/errno.h>
> #include <linux/smp.h>
> +#include <linux/io.h>
>
> #include <asm/cacheflush.h>
> +#include <mach/omap-wakeupgen.h>
>
> #include "common.h"
>
> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
> */
> void __ref platform_cpu_die(unsigned int cpu)
> {
> - unsigned int this_cpu;
> + unsigned int boot_cpu = 0;
> + void __iomem *base = omap_get_wakeupgen_base();
this is unnecessary copy for omap4, move it to the place where you want
it below.
+ void __iomem *base;
>
> flush_cache_all();
> dsb();
> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
> /*
> * we're ready for shutdown now, so do it
> */
> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> - pr_err("Secure clear status failed\n");
> + if (cpu_is_omap44xx()) {
> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> + pr_err("Secure clear status failed\n");
> + } else {
i.e. here
+ *base = omap_get_wakeupgen_base();
> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
> + }
> +
>
> for (;;) {
> /*
> * Enter into low power state
> */
> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
> - this_cpu = smp_processor_id();
> - if (omap_read_auxcoreboot0() == this_cpu) {
> +
> + if (cpu_is_omap44xx())
> + boot_cpu = omap_read_auxcoreboot0();
> + else
> + boot_cpu =
> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
> +
> + if (boot_cpu == smp_processor_id()) {
> /*
> * OK, proper wakeup, we're done
> */
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index deffbf1..151fd5b 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -26,6 +26,8 @@
>
> #include <mach/hardware.h>
> #include <mach/omap-secure.h>
> +#include <mach/omap-wakeupgen.h>
> +#include <asm/cputype.h>
>
> #include "iomap.h"
> #include "common.h"
> @@ -73,6 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> static struct clockdomain *cpu1_clkdm;
> static bool booted;
> + void __iomem *base = omap_get_wakeupgen_base();
ditto.
> +
> /*
> * Set synchronisation state between this boot processor
> * and the secondary one
> @@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> * the AuxCoreBoot1 register is updated with cpu state
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + if (cpu_is_omap44xx())
> + omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + else
put it here instead
+{
+ void __iomem *base = omap_get_wakeup_base();
> + __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+}
> +
> flush_cache_all();
> smp_wmb();
>
> @@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> static void __init wakeup_secondary(void)
> {
> + void __iomem *base = omap_get_wakeupgen_base();
> +
ditto
> /*
> * Write the address of secondary startup routine into the
> * AuxCoreBoot1 where ROM code will jump and start executing
> * on secondary core once out of WFE
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + if (cpu_is_omap44xx())
> + omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + else
> + __raw_writel(virt_to_phys(omap5_secondary_startup),
> + base + OMAP_AUX_CORE_BOOT_1);
> +
> smp_wmb();
>
> /*
> diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
> index 42cd7fb..444cf12 100644
> --- a/arch/arm/mach-omap2/omap-wakeupgen.c
> +++ b/arch/arm/mach-omap2/omap-wakeupgen.c
> @@ -33,18 +33,22 @@
> #include "omap4-sar-layout.h"
> #include "common.h"
>
> -#define NR_REG_BANKS 4
> -#define MAX_IRQS 128
> +#define MAX_NR_REG_BANKS 5
> +#define MAX_IRQS 160
> #define WKG_MASK_ALL 0x00000000
> #define WKG_UNMASK_ALL 0xffffffff
> #define CPU_ENA_OFFSET 0x400
> #define CPU0_ID 0x0
> #define CPU1_ID 0x1
> +#define OMAP4_NR_BANKS 4
> +#define OMAP4_NR_IRQS 128
>
> static void __iomem *wakeupgen_base;
> static void __iomem *sar_base;
> static DEFINE_SPINLOCK(wakeupgen_lock);
> static unsigned int irq_target_cpu[NR_IRQS];
> +static unsigned int irq_banks = MAX_NR_REG_BANKS;
> +static unsigned int max_irqs = MAX_IRQS;
>
> /*
> * Static helper functions.
> @@ -146,13 +150,13 @@ static void wakeupgen_unmask(struct irq_data *d)
> }
>
> #ifdef CONFIG_HOTPLUG_CPU
> -static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
> +static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
>
> static void _wakeupgen_save_masks(unsigned int cpu)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
> }
>
> @@ -160,7 +164,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
> }
>
> @@ -168,7 +172,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> wakeupgen_writel(reg, i, cpu);
> }
>
> @@ -196,25 +200,11 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
> #endif
>
> #ifdef CONFIG_CPU_PM
> -/*
> - * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
> - * ROM code. WakeupGen IP is integrated along with GIC to manage the
> - * interrupt wakeups from CPU low power states. It manages
> - * masking/unmasking of Shared peripheral interrupts(SPI). So the
> - * interrupt enable/disable control should be in sync and consistent
> - * at WakeupGen and GIC so that interrupts are not lost.
> - */
> -static void irq_save_context(void)
> +static inline void omap4_irq_save_context(void)
> {
> u32 i, val;
>
> - if (omap_rev() == OMAP4430_REV_ES1_0)
> - return;
you removed the above check for 4430_ES1_0 here but do not add it back
in the new irq_save_context().
> -
> - if (!sar_base)
> - sar_base = omap4_get_sar_ram_base();
> -
> - for (i = 0; i < NR_REG_BANKS; i++) {
> + for (i = 0; i < irq_banks; i++) {
> /* Save the CPUx interrupt mask for IRQ 0 to 127 */
> val = wakeupgen_readl(i, 0);
> sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
> @@ -254,6 +244,53 @@ static void irq_save_context(void)
> val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
> val |= SAR_BACKUP_STATUS_WAKEUPGEN;
> __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
> +
> +}
> +
> +static inline void omap5_irq_save_context(void)
> +{
> + u32 i, val;
> +
> + for (i = 0; i < irq_banks; i++) {
> + /* Save the CPUx interrupt mask for IRQ 0 to 159 */
> + val = wakeupgen_readl(i, 0);
> + sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
> + val = wakeupgen_readl(i, 1);
> + sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
> + sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
> + sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
> + }
> +
> + /* Save AuxBoot* registers */
> + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
> + __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
> + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
> + __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
> +
> + /* Set the Backup Bit Mask status */
> + val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
> + val |= SAR_BACKUP_STATUS_WAKEUPGEN;
> + __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
> +
> +}
> +
> +/*
> + * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
> + * ROM code. WakeupGen IP is integrated along with GIC to manage the
> + * interrupt wakeups from CPU low power states. It manages
> + * masking/unmasking of Shared peripheral interrupts(SPI). So the
> + * interrupt enable/disable control should be in sync and consistent
> + * at WakeupGen and GIC so that interrupts are not lost.
> + */
> +static void irq_save_context(void)
> +{
add the 4430 ES1 check here
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ return;
> + if (!sar_base)
> + sar_base = omap4_get_sar_ram_base();
> +
> + if (cpu_is_omap54xx())
> + omap5_irq_save_context();
> + else
> + omap4_irq_save_context();
> }
>
> /*
> @@ -262,9 +299,14 @@ static void irq_save_context(void)
> void irq_sar_clear(void)
> {
> u32 val;
> - val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
> + u32 offset = SAR_BACKUP_STATUS_OFFSET;
> +
> + if (cpu_is_omap54xx())
> + offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
> +
> + val = __raw_readl(sar_base + offset);
> val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
> - __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
> + __raw_writel(val, sar_base + offset);
> }
>
> /*
> @@ -336,13 +378,20 @@ static struct notifier_block irq_notifier_block = {
>
> static void __init irq_pm_init(void)
> {
> - cpu_pm_register_notifier(&irq_notifier_block);
> + /* FIXME: Remove this when MPU OSWR support is added */
> + if (!cpu_is_omap54xx())
> + cpu_pm_register_notifier(&irq_notifier_block);
> }
> #else
> static void __init irq_pm_init(void)
> {}
> #endif
>
> +void __iomem *omap_get_wakeupgen_base(void)
> +{
> + return wakeupgen_base;
> +}
> +
> /*
> * Initialise the wakeupgen module.
> */
> @@ -358,12 +407,17 @@ int __init omap_wakeupgen_init(void)
> }
>
> /* Static mapping, never released */
> - wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
> + wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
unnecessary change. I don't see why you can't continue to use
OMAP44XX_WKUPGEN_BASE
> if (WARN_ON(!wakeupgen_base))
> return -ENOMEM;
>
> + if (cpu_is_omap44xx()) {
> + irq_banks = OMAP4_NR_BANKS;
> + max_irqs = OMAP4_NR_IRQS;
> + }
> +
> /* Clear all IRQ bitmasks at wakeupGen level */
> - for (i = 0; i < NR_REG_BANKS; i++) {
> + for (i = 0; i < irq_banks; i++) {
> wakeupgen_writel(0, i, CPU0_ID);
> wakeupgen_writel(0, i, CPU1_ID);
> }
> @@ -382,7 +436,7 @@ int __init omap_wakeupgen_init(void)
> */
>
> /* Associate all the IRQs to boot CPU like GIC init does. */
> - for (i = 0; i < NR_IRQS; i++)
> + for (i = 0; i < max_irqs; i++)
> irq_target_cpu[i] = boot_cpu;
>
> irq_hotplug_init();
> diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
> index fe5b545..e170fe8 100644
> --- a/arch/arm/mach-omap2/omap4-sar-layout.h
> +++ b/arch/arm/mach-omap2/omap4-sar-layout.h
> @@ -12,7 +12,7 @@
> #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
>
> /*
> - * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
> + * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
> */
> #define SAR_BANK1_OFFSET 0x0000
> #define SAR_BANK2_OFFSET 0x1000
> @@ -47,4 +47,14 @@
> #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
> #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
>
> +/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
> +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
> +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
> +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
> +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
> +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
> +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
> +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
> +#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
> +
> #endif
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-10 11:36 ` Roger Quadros
0 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
> - Additional 32 interrupt support is added w.r.t OMAP4 design.
> - The AUX CORE boot registers are now made accessible from non-secure SW.
> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>
> Patch updates the WakeupGen code accordingly.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
> arch/arm/mach-omap2/omap-smp.c | 19 +++-
> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
> 5 files changed, 135 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> index 548de90..4d700bc 100644
> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
> @@ -11,15 +11,20 @@
> #ifndef OMAP_ARCH_WAKEUPGEN_H
> #define OMAP_ARCH_WAKEUPGEN_H
>
> +/* OMAP4 and OMAP5 has same base address */
> +#define OMAP_WKUPGEN_BASE 0x48281000
unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
define this in the same header as OMAP44XX_WKUPGEN_BASE?
> +
> #define OMAP_WKG_CONTROL_0 0x00
> #define OMAP_WKG_ENB_A_0 0x10
> #define OMAP_WKG_ENB_B_0 0x14
> #define OMAP_WKG_ENB_C_0 0x18
> #define OMAP_WKG_ENB_D_0 0x1c
> +#define OMAP_WKG_ENB_E_0 0x20
> #define OMAP_WKG_ENB_A_1 0x410
> #define OMAP_WKG_ENB_B_1 0x414
> #define OMAP_WKG_ENB_C_1 0x418
> #define OMAP_WKG_ENB_D_1 0x41c
> +#define OMAP_WKG_ENB_E_1 0x420
> #define OMAP_AUX_CORE_BOOT_0 0x800
> #define OMAP_AUX_CORE_BOOT_1 0x804
> #define OMAP_PTMSYNCREQ_MASK 0xc00
> @@ -28,4 +33,5 @@
> #define OMAP_TIMESTAMPCYCLEHI 0xc0c
>
> extern int __init omap_wakeupgen_init(void);
> +extern void __iomem *omap_get_wakeupgen_base(void);
> #endif
> diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
> index 56c345b..052303c 100644
> --- a/arch/arm/mach-omap2/omap-hotplug.c
> +++ b/arch/arm/mach-omap2/omap-hotplug.c
> @@ -17,8 +17,10 @@
> #include <linux/kernel.h>
> #include <linux/errno.h>
> #include <linux/smp.h>
> +#include <linux/io.h>
>
> #include <asm/cacheflush.h>
> +#include <mach/omap-wakeupgen.h>
>
> #include "common.h"
>
> @@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
> */
> void __ref platform_cpu_die(unsigned int cpu)
> {
> - unsigned int this_cpu;
> + unsigned int boot_cpu = 0;
> + void __iomem *base = omap_get_wakeupgen_base();
this is unnecessary copy for omap4, move it to the place where you want
it below.
+ void __iomem *base;
>
> flush_cache_all();
> dsb();
> @@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
> /*
> * we're ready for shutdown now, so do it
> */
> - if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> - pr_err("Secure clear status failed\n");
> + if (cpu_is_omap44xx()) {
> + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
> + pr_err("Secure clear status failed\n");
> + } else {
i.e. here
+ *base = omap_get_wakeupgen_base();
> + __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
> + }
> +
>
> for (;;) {
> /*
> * Enter into low power state
> */
> omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
> - this_cpu = smp_processor_id();
> - if (omap_read_auxcoreboot0() == this_cpu) {
> +
> + if (cpu_is_omap44xx())
> + boot_cpu = omap_read_auxcoreboot0();
> + else
> + boot_cpu =
> + __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
> +
> + if (boot_cpu == smp_processor_id()) {
> /*
> * OK, proper wakeup, we're done
> */
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index deffbf1..151fd5b 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -26,6 +26,8 @@
>
> #include <mach/hardware.h>
> #include <mach/omap-secure.h>
> +#include <mach/omap-wakeupgen.h>
> +#include <asm/cputype.h>
>
> #include "iomap.h"
> #include "common.h"
> @@ -73,6 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> static struct clockdomain *cpu1_clkdm;
> static bool booted;
> + void __iomem *base = omap_get_wakeupgen_base();
ditto.
> +
> /*
> * Set synchronisation state between this boot processor
> * and the secondary one
> @@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> * the AuxCoreBoot1 register is updated with cpu state
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + if (cpu_is_omap44xx())
> + omap_modify_auxcoreboot0(0x200, 0xfffffdff);
> + else
put it here instead
+{
+ void __iomem *base = omap_get_wakeup_base();
> + __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+}
> +
> flush_cache_all();
> smp_wmb();
>
> @@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> static void __init wakeup_secondary(void)
> {
> + void __iomem *base = omap_get_wakeupgen_base();
> +
ditto
> /*
> * Write the address of secondary startup routine into the
> * AuxCoreBoot1 where ROM code will jump and start executing
> * on secondary core once out of WFE
> * A barrier is added to ensure that write buffer is drained
> */
> - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + if (cpu_is_omap44xx())
> + omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
> + else
> + __raw_writel(virt_to_phys(omap5_secondary_startup),
> + base + OMAP_AUX_CORE_BOOT_1);
> +
> smp_wmb();
>
> /*
> diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
> index 42cd7fb..444cf12 100644
> --- a/arch/arm/mach-omap2/omap-wakeupgen.c
> +++ b/arch/arm/mach-omap2/omap-wakeupgen.c
> @@ -33,18 +33,22 @@
> #include "omap4-sar-layout.h"
> #include "common.h"
>
> -#define NR_REG_BANKS 4
> -#define MAX_IRQS 128
> +#define MAX_NR_REG_BANKS 5
> +#define MAX_IRQS 160
> #define WKG_MASK_ALL 0x00000000
> #define WKG_UNMASK_ALL 0xffffffff
> #define CPU_ENA_OFFSET 0x400
> #define CPU0_ID 0x0
> #define CPU1_ID 0x1
> +#define OMAP4_NR_BANKS 4
> +#define OMAP4_NR_IRQS 128
>
> static void __iomem *wakeupgen_base;
> static void __iomem *sar_base;
> static DEFINE_SPINLOCK(wakeupgen_lock);
> static unsigned int irq_target_cpu[NR_IRQS];
> +static unsigned int irq_banks = MAX_NR_REG_BANKS;
> +static unsigned int max_irqs = MAX_IRQS;
>
> /*
> * Static helper functions.
> @@ -146,13 +150,13 @@ static void wakeupgen_unmask(struct irq_data *d)
> }
>
> #ifdef CONFIG_HOTPLUG_CPU
> -static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
> +static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
>
> static void _wakeupgen_save_masks(unsigned int cpu)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
> }
>
> @@ -160,7 +164,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
> }
>
> @@ -168,7 +172,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
> {
> u8 i;
>
> - for (i = 0; i < NR_REG_BANKS; i++)
> + for (i = 0; i < irq_banks; i++)
> wakeupgen_writel(reg, i, cpu);
> }
>
> @@ -196,25 +200,11 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
> #endif
>
> #ifdef CONFIG_CPU_PM
> -/*
> - * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
> - * ROM code. WakeupGen IP is integrated along with GIC to manage the
> - * interrupt wakeups from CPU low power states. It manages
> - * masking/unmasking of Shared peripheral interrupts(SPI). So the
> - * interrupt enable/disable control should be in sync and consistent
> - * at WakeupGen and GIC so that interrupts are not lost.
> - */
> -static void irq_save_context(void)
> +static inline void omap4_irq_save_context(void)
> {
> u32 i, val;
>
> - if (omap_rev() == OMAP4430_REV_ES1_0)
> - return;
you removed the above check for 4430_ES1_0 here but do not add it back
in the new irq_save_context().
> -
> - if (!sar_base)
> - sar_base = omap4_get_sar_ram_base();
> -
> - for (i = 0; i < NR_REG_BANKS; i++) {
> + for (i = 0; i < irq_banks; i++) {
> /* Save the CPUx interrupt mask for IRQ 0 to 127 */
> val = wakeupgen_readl(i, 0);
> sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
> @@ -254,6 +244,53 @@ static void irq_save_context(void)
> val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
> val |= SAR_BACKUP_STATUS_WAKEUPGEN;
> __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
> +
> +}
> +
> +static inline void omap5_irq_save_context(void)
> +{
> + u32 i, val;
> +
> + for (i = 0; i < irq_banks; i++) {
> + /* Save the CPUx interrupt mask for IRQ 0 to 159 */
> + val = wakeupgen_readl(i, 0);
> + sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
> + val = wakeupgen_readl(i, 1);
> + sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
> + sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
> + sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
> + }
> +
> + /* Save AuxBoot* registers */
> + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
> + __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
> + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
> + __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
> +
> + /* Set the Backup Bit Mask status */
> + val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
> + val |= SAR_BACKUP_STATUS_WAKEUPGEN;
> + __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
> +
> +}
> +
> +/*
> + * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
> + * ROM code. WakeupGen IP is integrated along with GIC to manage the
> + * interrupt wakeups from CPU low power states. It manages
> + * masking/unmasking of Shared peripheral interrupts(SPI). So the
> + * interrupt enable/disable control should be in sync and consistent
> + * at WakeupGen and GIC so that interrupts are not lost.
> + */
> +static void irq_save_context(void)
> +{
add the 4430 ES1 check here
+ if (omap_rev() == OMAP4430_REV_ES1_0)
+ return;
> + if (!sar_base)
> + sar_base = omap4_get_sar_ram_base();
> +
> + if (cpu_is_omap54xx())
> + omap5_irq_save_context();
> + else
> + omap4_irq_save_context();
> }
>
> /*
> @@ -262,9 +299,14 @@ static void irq_save_context(void)
> void irq_sar_clear(void)
> {
> u32 val;
> - val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
> + u32 offset = SAR_BACKUP_STATUS_OFFSET;
> +
> + if (cpu_is_omap54xx())
> + offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
> +
> + val = __raw_readl(sar_base + offset);
> val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
> - __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
> + __raw_writel(val, sar_base + offset);
> }
>
> /*
> @@ -336,13 +378,20 @@ static struct notifier_block irq_notifier_block = {
>
> static void __init irq_pm_init(void)
> {
> - cpu_pm_register_notifier(&irq_notifier_block);
> + /* FIXME: Remove this when MPU OSWR support is added */
> + if (!cpu_is_omap54xx())
> + cpu_pm_register_notifier(&irq_notifier_block);
> }
> #else
> static void __init irq_pm_init(void)
> {}
> #endif
>
> +void __iomem *omap_get_wakeupgen_base(void)
> +{
> + return wakeupgen_base;
> +}
> +
> /*
> * Initialise the wakeupgen module.
> */
> @@ -358,12 +407,17 @@ int __init omap_wakeupgen_init(void)
> }
>
> /* Static mapping, never released */
> - wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
> + wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
unnecessary change. I don't see why you can't continue to use
OMAP44XX_WKUPGEN_BASE
> if (WARN_ON(!wakeupgen_base))
> return -ENOMEM;
>
> + if (cpu_is_omap44xx()) {
> + irq_banks = OMAP4_NR_BANKS;
> + max_irqs = OMAP4_NR_IRQS;
> + }
> +
> /* Clear all IRQ bitmasks at wakeupGen level */
> - for (i = 0; i < NR_REG_BANKS; i++) {
> + for (i = 0; i < irq_banks; i++) {
> wakeupgen_writel(0, i, CPU0_ID);
> wakeupgen_writel(0, i, CPU1_ID);
> }
> @@ -382,7 +436,7 @@ int __init omap_wakeupgen_init(void)
> */
>
> /* Associate all the IRQs to boot CPU like GIC init does. */
> - for (i = 0; i < NR_IRQS; i++)
> + for (i = 0; i < max_irqs; i++)
> irq_target_cpu[i] = boot_cpu;
>
> irq_hotplug_init();
> diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
> index fe5b545..e170fe8 100644
> --- a/arch/arm/mach-omap2/omap4-sar-layout.h
> +++ b/arch/arm/mach-omap2/omap4-sar-layout.h
> @@ -12,7 +12,7 @@
> #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
>
> /*
> - * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
> + * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
> */
> #define SAR_BANK1_OFFSET 0x0000
> #define SAR_BANK2_OFFSET 0x1000
> @@ -47,4 +47,14 @@
> #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
> #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
>
> +/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
> +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
> +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
> +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
> +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
> +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
> +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
> +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
> +#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
> +
> #endif
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-10 11:36 ` Roger Quadros
@ 2012-05-10 11:42 ` Shilimkar, Santosh
-1 siblings, 0 replies; 126+ messages in thread
From: Shilimkar, Santosh @ 2012-05-10 11:42 UTC (permalink / raw)
To: Roger Quadros; +Cc: R Sricharan, linux-omap, linux-arm-kernel, tony, b-cousson
On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
> Hi,
>
> On 05/03/2012 10:26 AM, R Sricharan wrote:
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>
>> Patch updates the WakeupGen code accordingly.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> ---
>> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
>> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
>> arch/arm/mach-omap2/omap-smp.c | 19 +++-
>> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
>> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
>> 5 files changed, 135 insertions(+), 36 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> index 548de90..4d700bc 100644
>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> @@ -11,15 +11,20 @@
>> #ifndef OMAP_ARCH_WAKEUPGEN_H
>> #define OMAP_ARCH_WAKEUPGEN_H
>>
>> +/* OMAP4 and OMAP5 has same base address */
>> +#define OMAP_WKUPGEN_BASE 0x48281000
>
> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>
Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
remove the OMAP44XX reference if the base is generic and not depend
on OMAP4/5.
It's not un-necessary change as such.
Regards
Santosh
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-10 11:42 ` Shilimkar, Santosh
0 siblings, 0 replies; 126+ messages in thread
From: Shilimkar, Santosh @ 2012-05-10 11:42 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
> Hi,
>
> On 05/03/2012 10:26 AM, R Sricharan wrote:
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>
>> Patch updates the WakeupGen code accordingly.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> ---
>> ?arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | ? ?6 +
>> ?arch/arm/mach-omap2/omap-hotplug.c ? ? ? ? ? ? ? ?| ? 24 ++++-
>> ?arch/arm/mach-omap2/omap-smp.c ? ? ? ? ? ? ? ? ? ?| ? 19 +++-
>> ?arch/arm/mach-omap2/omap-wakeupgen.c ? ? ? ? ? ? ?| ?110 +++++++++++++++-----
>> ?arch/arm/mach-omap2/omap4-sar-layout.h ? ? ? ? ? ?| ? 12 ++-
>> ?5 files changed, 135 insertions(+), 36 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> index 548de90..4d700bc 100644
>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>> @@ -11,15 +11,20 @@
>> ?#ifndef OMAP_ARCH_WAKEUPGEN_H
>> ?#define OMAP_ARCH_WAKEUPGEN_H
>>
>> +/* OMAP4 and OMAP5 has same base address */
>> +#define OMAP_WKUPGEN_BASE ? ? ? ? ? ? ? ? ? ?0x48281000
>
> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>
Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
remove the OMAP44XX reference if the base is generic and not depend
on OMAP4/5.
It's not un-necessary change as such.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-10 11:42 ` Shilimkar, Santosh
@ 2012-05-10 11:48 ` Roger Quadros
-1 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:48 UTC (permalink / raw)
To: Shilimkar, Santosh
Cc: R Sricharan, linux-omap, linux-arm-kernel, tony, b-cousson
On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
> On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
>> Hi,
>>
>> On 05/03/2012 10:26 AM, R Sricharan wrote:
>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>
>>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>>
>>> Patch updates the WakeupGen code accordingly.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>>> ---
>>> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
>>> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
>>> arch/arm/mach-omap2/omap-smp.c | 19 +++-
>>> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
>>> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
>>> 5 files changed, 135 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> index 548de90..4d700bc 100644
>>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> @@ -11,15 +11,20 @@
>>> #ifndef OMAP_ARCH_WAKEUPGEN_H
>>> #define OMAP_ARCH_WAKEUPGEN_H
>>>
>>> +/* OMAP4 and OMAP5 has same base address */
>>> +#define OMAP_WKUPGEN_BASE 0x48281000
>>
>> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
>> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>>
> Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
> remove the OMAP44XX reference if the base is generic and not depend
> on OMAP4/5.
>
> It's not un-necessary change as such.
>
OK, is OMAP_WKUPGEN_BASE applicable for OMAPs prior to OMAP4? If not the
naming scheme does not look appropriate.
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-10 11:48 ` Roger Quadros
0 siblings, 0 replies; 126+ messages in thread
From: Roger Quadros @ 2012-05-10 11:48 UTC (permalink / raw)
To: linux-arm-kernel
On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
> On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
>> Hi,
>>
>> On 05/03/2012 10:26 AM, R Sricharan wrote:
>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>
>>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>>
>>> Patch updates the WakeupGen code accordingly.
>>>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>>> ---
>>> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
>>> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
>>> arch/arm/mach-omap2/omap-smp.c | 19 +++-
>>> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
>>> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
>>> 5 files changed, 135 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> index 548de90..4d700bc 100644
>>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>> @@ -11,15 +11,20 @@
>>> #ifndef OMAP_ARCH_WAKEUPGEN_H
>>> #define OMAP_ARCH_WAKEUPGEN_H
>>>
>>> +/* OMAP4 and OMAP5 has same base address */
>>> +#define OMAP_WKUPGEN_BASE 0x48281000
>>
>> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
>> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>>
> Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
> remove the OMAP44XX reference if the base is generic and not depend
> on OMAP4/5.
>
> It's not un-necessary change as such.
>
OK, is OMAP_WKUPGEN_BASE applicable for OMAPs prior to OMAP4? If not the
naming scheme does not look appropriate.
regards,
-roger
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
2012-05-10 11:48 ` Roger Quadros
@ 2012-05-10 11:52 ` Santosh Shilimkar
-1 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-10 11:52 UTC (permalink / raw)
To: Roger Quadros; +Cc: R Sricharan, linux-omap, linux-arm-kernel, tony, b-cousson
On Thursday 10 May 2012 05:18 PM, Roger Quadros wrote:
> On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
>> On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
>>> Hi,
>>>
>>> On 05/03/2012 10:26 AM, R Sricharan wrote:
>>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>
>>>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>>>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>>>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>>>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>>>
>>>> Patch updates the WakeupGen code accordingly.
>>>>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>>>> ---
>>>> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
>>>> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
>>>> arch/arm/mach-omap2/omap-smp.c | 19 +++-
>>>> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
>>>> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
>>>> 5 files changed, 135 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> index 548de90..4d700bc 100644
>>>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> @@ -11,15 +11,20 @@
>>>> #ifndef OMAP_ARCH_WAKEUPGEN_H
>>>> #define OMAP_ARCH_WAKEUPGEN_H
>>>>
>>>> +/* OMAP4 and OMAP5 has same base address */
>>>> +#define OMAP_WKUPGEN_BASE 0x48281000
>>>
>>> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
>>> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>>>
>> Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
>> remove the OMAP44XX reference if the base is generic and not depend
>> on OMAP4/5.
>>
>> It's not un-necessary change as such.
>>
>
> OK, is OMAP_WKUPGEN_BASE applicable for OMAPs prior to OMAP4? If not the
> naming scheme does not look appropriate.
>
It's IP exist on OMAP4/5 and future OMAPs, no name is
fine. Btw, if you go on that route you will too many examples
of non appropriate names.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 08/13] ARM: OMAP5: Add the WakeupGen IP updates.
@ 2012-05-10 11:52 ` Santosh Shilimkar
0 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-10 11:52 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 10 May 2012 05:18 PM, Roger Quadros wrote:
> On 05/10/2012 02:42 PM, Shilimkar, Santosh wrote:
>> On Thu, May 10, 2012 at 5:06 PM, Roger Quadros <rogerq@ti.com> wrote:
>>> Hi,
>>>
>>> On 05/03/2012 10:26 AM, R Sricharan wrote:
>>>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>>
>>>> OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
>>>> - Additional 32 interrupt support is added w.r.t OMAP4 design.
>>>> - The AUX CORE boot registers are now made accessible from non-secure SW.
>>>> - SAR offset are changed and PTMSYNC* registers are removed from SAR.
>>>>
>>>> Patch updates the WakeupGen code accordingly.
>>>>
>>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>>>> ---
>>>> arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 6 +
>>>> arch/arm/mach-omap2/omap-hotplug.c | 24 ++++-
>>>> arch/arm/mach-omap2/omap-smp.c | 19 +++-
>>>> arch/arm/mach-omap2/omap-wakeupgen.c | 110 +++++++++++++++-----
>>>> arch/arm/mach-omap2/omap4-sar-layout.h | 12 ++-
>>>> 5 files changed, 135 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> index 548de90..4d700bc 100644
>>>> --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
>>>> @@ -11,15 +11,20 @@
>>>> #ifndef OMAP_ARCH_WAKEUPGEN_H
>>>> #define OMAP_ARCH_WAKEUPGEN_H
>>>>
>>>> +/* OMAP4 and OMAP5 has same base address */
>>>> +#define OMAP_WKUPGEN_BASE 0x48281000
>>>
>>> unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or
>>> define this in the same header as OMAP44XX_WKUPGEN_BASE?
>>>
>> Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to
>> remove the OMAP44XX reference if the base is generic and not depend
>> on OMAP4/5.
>>
>> It's not un-necessary change as such.
>>
>
> OK, is OMAP_WKUPGEN_BASE applicable for OMAPs prior to OMAP4? If not the
> naming scheme does not look appropriate.
>
It's IP exist on OMAP4/5 and future OMAPs, no name is
fine. Btw, if you go on that route you will too many examples
of non appropriate names.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 09/13] ARM: OMAP5: Add SMP support.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
3 files changed, 51 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 88fb577..0771d22 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -222,6 +222,7 @@ extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
+extern void omap5_secondary_startup(void);
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac77..502e313 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
#include <linux/init.h>
__CPUINIT
+
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define AUX_CORE_BOOT0_PA 0x48281800
+
+/*
+ * OMAP5 specific entry point for secondary CPU to jump from ROM
+ * code. This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update this flag using a hardware
++ * register AuxCoreBoot0.
+ */
+ENTRY(omap5_secondary_startup)
+wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
+ ldr r0, [r2]
+ mov r0, r0, lsr #5
+ mrc p15, 0, r4, c0, c0, 5
+ and r4, r4, #0x0f
+ cmp r0, r4
+ bne wait
+ b secondary_startup
+END(omap5_secondary_startup)
/*
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 151fd5b..9424bb6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -33,6 +33,10 @@
#include "common.h"
#include "clockdomain.h"
+#define CPU_MASK 0xff0ffff0
+#define CPU_CORTEX_A9 0x410FC090
+#define CPU_CORTEX_A15 0x410FC0F0
+
/* SCU base address */
static void __iomem *scu_base;
@@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
return scu_base;
}
+static inline unsigned int get_a15_core_count(void)
+{
+ unsigned int ncores;
+
+ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
+ return ((ncores >> 24) & 3) + 1;
+}
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@@ -133,7 +145,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void)
{
void __iomem *base = omap_get_wakeupgen_base();
-
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
@@ -162,16 +173,21 @@ static void __init wakeup_secondary(void)
*/
void __init smp_init_cpus(void)
{
- unsigned int i, ncores;
-
- /*
- * Currently we can't call ioremap here because
- * SoC detection won't work until after init_early.
- */
- scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
- BUG_ON(!scu_base);
-
- ncores = scu_get_core_count(scu_base);
+ unsigned int i = 0, ncores = 1, cpu_id;
+
+ /* Use ARM cpuid check here, as SoC detection will not work so early */
+ cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+ if (cpu_id == CPU_CORTEX_A9) {
+ /*
+ * Currently we can't call ioremap here because
+ * SoC detection won't work until after init_early.
+ */
+ scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+ BUG_ON(!scu_base);
+ ncores = scu_get_core_count(scu_base);
+ } else if (cpu_id == CPU_CORTEX_A15) {
+ ncores = get_a15_core_count();
+ }
/* sanity check */
if (ncores > nr_cpu_ids) {
@@ -193,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the SCU and wake up the secondary core using
* wakeup_secondary().
*/
- scu_enable(scu_base);
+ if (scu_base)
+ scu_enable(scu_base);
wakeup_secondary();
}
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 09/13] ARM: OMAP5: Add SMP support.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/common.h | 1 +
arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
3 files changed, 51 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 88fb577..0771d22 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -222,6 +222,7 @@ extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
+extern void omap5_secondary_startup(void);
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac77..502e313 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
#include <linux/init.h>
__CPUINIT
+
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define AUX_CORE_BOOT0_PA 0x48281800
+
+/*
+ * OMAP5 specific entry point for secondary CPU to jump from ROM
+ * code. This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update this flag using a hardware
++ * register AuxCoreBoot0.
+ */
+ENTRY(omap5_secondary_startup)
+wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
+ ldr r0, [r2]
+ mov r0, r0, lsr #5
+ mrc p15, 0, r4, c0, c0, 5
+ and r4, r4, #0x0f
+ cmp r0, r4
+ bne wait
+ b secondary_startup
+END(omap5_secondary_startup)
/*
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 151fd5b..9424bb6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -33,6 +33,10 @@
#include "common.h"
#include "clockdomain.h"
+#define CPU_MASK 0xff0ffff0
+#define CPU_CORTEX_A9 0x410FC090
+#define CPU_CORTEX_A15 0x410FC0F0
+
/* SCU base address */
static void __iomem *scu_base;
@@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
return scu_base;
}
+static inline unsigned int get_a15_core_count(void)
+{
+ unsigned int ncores;
+
+ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
+ return ((ncores >> 24) & 3) + 1;
+}
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@@ -133,7 +145,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init wakeup_secondary(void)
{
void __iomem *base = omap_get_wakeupgen_base();
-
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
@@ -162,16 +173,21 @@ static void __init wakeup_secondary(void)
*/
void __init smp_init_cpus(void)
{
- unsigned int i, ncores;
-
- /*
- * Currently we can't call ioremap here because
- * SoC detection won't work until after init_early.
- */
- scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
- BUG_ON(!scu_base);
-
- ncores = scu_get_core_count(scu_base);
+ unsigned int i = 0, ncores = 1, cpu_id;
+
+ /* Use ARM cpuid check here, as SoC detection will not work so early */
+ cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+ if (cpu_id == CPU_CORTEX_A9) {
+ /*
+ * Currently we can't call ioremap here because
+ * SoC detection won't work until after init_early.
+ */
+ scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+ BUG_ON(!scu_base);
+ ncores = scu_get_core_count(scu_base);
+ } else if (cpu_id == CPU_CORTEX_A15) {
+ ncores = get_a15_core_count();
+ }
/* sanity check */
if (ncores > nr_cpu_ids) {
@@ -193,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the SCU and wake up the secondary core using
* wakeup_secondary().
*/
- scu_enable(scu_base);
+ if (scu_base)
+ scu_enable(scu_base);
wakeup_secondary();
}
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 09/13] ARM: OMAP5: Add SMP support.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-08 12:47 ` Will Deacon
-1 siblings, 0 replies; 126+ messages in thread
From: Will Deacon @ 2012-05-08 12:47 UTC (permalink / raw)
To: R Sricharan
Cc: linux-omap, tony, santosh.shilimkar, b-cousson, linux-arm-kernel
Hello,
On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
> are runtime checked using cpu id
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/common.h | 1 +
> arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
> arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
> 3 files changed, 51 insertions(+), 12 deletions(-)
[...]
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 151fd5b..9424bb6 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -33,6 +33,10 @@
> #include "common.h"
> #include "clockdomain.h"
>
> +#define CPU_MASK 0xff0ffff0
> +#define CPU_CORTEX_A9 0x410FC090
> +#define CPU_CORTEX_A15 0x410FC0F0
> +
> /* SCU base address */
> static void __iomem *scu_base;
>
> @@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
> return scu_base;
> }
>
> +static inline unsigned int get_a15_core_count(void)
> +{
> + unsigned int ncores;
> +
> + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
> + return ((ncores >> 24) & 3) + 1;
> +}
This register (L2 control) only tells you how many cores you have hanging
off the L2 cache, which isn't really viable for future multi-cluster
configurations. You're probably better off either reading the number of CPU
nodes out of the DT (ppc, vexpress) or returning a constant for now
(exynos5).
Will
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 09/13] ARM: OMAP5: Add SMP support.
@ 2012-05-08 12:47 ` Will Deacon
0 siblings, 0 replies; 126+ messages in thread
From: Will Deacon @ 2012-05-08 12:47 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
> are runtime checked using cpu id
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/common.h | 1 +
> arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
> arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
> 3 files changed, 51 insertions(+), 12 deletions(-)
[...]
> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
> index 151fd5b..9424bb6 100644
> --- a/arch/arm/mach-omap2/omap-smp.c
> +++ b/arch/arm/mach-omap2/omap-smp.c
> @@ -33,6 +33,10 @@
> #include "common.h"
> #include "clockdomain.h"
>
> +#define CPU_MASK 0xff0ffff0
> +#define CPU_CORTEX_A9 0x410FC090
> +#define CPU_CORTEX_A15 0x410FC0F0
> +
> /* SCU base address */
> static void __iomem *scu_base;
>
> @@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
> return scu_base;
> }
>
> +static inline unsigned int get_a15_core_count(void)
> +{
> + unsigned int ncores;
> +
> + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
> + return ((ncores >> 24) & 3) + 1;
> +}
This register (L2 control) only tells you how many cores you have hanging
off the L2 cache, which isn't really viable for future multi-cluster
configurations. You're probably better off either reading the number of CPU
nodes out of the DT (ppc, vexpress) or returning a constant for now
(exynos5).
Will
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 09/13] ARM: OMAP5: Add SMP support.
2012-05-08 12:47 ` Will Deacon
@ 2012-05-08 13:00 ` Santosh Shilimkar
-1 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-08 13:00 UTC (permalink / raw)
To: Will Deacon; +Cc: R Sricharan, linux-omap, tony, b-cousson, linux-arm-kernel
On Tuesday 08 May 2012 06:17 PM, Will Deacon wrote:
> Hello,
>
> On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
>> are runtime checked using cpu id
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> ---
>> arch/arm/mach-omap2/common.h | 1 +
>> arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
>> arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
>> 3 files changed, 51 insertions(+), 12 deletions(-)
>
> [...]
>
>> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
>> index 151fd5b..9424bb6 100644
>> --- a/arch/arm/mach-omap2/omap-smp.c
>> +++ b/arch/arm/mach-omap2/omap-smp.c
>> @@ -33,6 +33,10 @@
>> #include "common.h"
>> #include "clockdomain.h"
>>
>> +#define CPU_MASK 0xff0ffff0
>> +#define CPU_CORTEX_A9 0x410FC090
>> +#define CPU_CORTEX_A15 0x410FC0F0
>> +
>> /* SCU base address */
>> static void __iomem *scu_base;
>>
>> @@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
>> return scu_base;
>> }
>>
>> +static inline unsigned int get_a15_core_count(void)
>> +{
>> + unsigned int ncores;
>> +
>> + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
>> + return ((ncores >> 24) & 3) + 1;
>> +}
>
> This register (L2 control) only tells you how many cores you have hanging
> off the L2 cache, which isn't really viable for future multi-cluster
> configurations. You're probably better off either reading the number of CPU
> nodes out of the DT (ppc, vexpress) or returning a constant for now
> (exynos5).
>
Thanks will for the information. I agree for the future multiple
packages, this register may not be good enough. We can hard-code
it as well for now.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 09/13] ARM: OMAP5: Add SMP support.
@ 2012-05-08 13:00 ` Santosh Shilimkar
0 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-08 13:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 08 May 2012 06:17 PM, Will Deacon wrote:
> Hello,
>
> On Thu, May 03, 2012 at 08:26:18AM +0100, R Sricharan wrote:
>> From: Santosh Shilimkar <santosh.shilimkar@ti.com>
>>
>> Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
>> are runtime checked using cpu id
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> ---
>> arch/arm/mach-omap2/common.h | 1 +
>> arch/arm/mach-omap2/omap-headsmp.S | 21 ++++++++++++++++++
>> arch/arm/mach-omap2/omap-smp.c | 41 +++++++++++++++++++++++++----------
>> 3 files changed, 51 insertions(+), 12 deletions(-)
>
> [...]
>
>> diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
>> index 151fd5b..9424bb6 100644
>> --- a/arch/arm/mach-omap2/omap-smp.c
>> +++ b/arch/arm/mach-omap2/omap-smp.c
>> @@ -33,6 +33,10 @@
>> #include "common.h"
>> #include "clockdomain.h"
>>
>> +#define CPU_MASK 0xff0ffff0
>> +#define CPU_CORTEX_A9 0x410FC090
>> +#define CPU_CORTEX_A15 0x410FC0F0
>> +
>> /* SCU base address */
>> static void __iomem *scu_base;
>>
>> @@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
>> return scu_base;
>> }
>>
>> +static inline unsigned int get_a15_core_count(void)
>> +{
>> + unsigned int ncores;
>> +
>> + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
>> + return ((ncores >> 24) & 3) + 1;
>> +}
>
> This register (L2 control) only tells you how many cores you have hanging
> off the L2 cache, which isn't really viable for future multi-cluster
> configurations. You're probably better off either reading the number of CPU
> nodes out of the DT (ppc, vexpress) or returning a constant for now
> (exynos5).
>
Thanks will for the information. I agree for the future multiple
packages, this register may not be good enough. We can hard-code
it as well for now.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Adding the minimal support for OMAP5 soc with device tree.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/board-generic.c | 39 +++++++++++++++++++++-------------
arch/arm/mach-omap2/common.h | 2 +
arch/arm/mach-omap2/irq.c | 11 +++++++++
arch/arm/mach-omap2/omap4-common.c | 14 ++++++++++++
4 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 098d183..0dd9e3f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,6 +20,7 @@
#include <mach/hardware.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
+#include <mach/omap-wakeupgen.h>
#include <plat/board.h>
#include "common.h"
@@ -32,17 +33,6 @@
#define gic_of_init NULL
#endif
-static struct of_device_id irq_match[] __initdata = {
- { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
- { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
- { }
-};
-
-static void __init omap_init_irq(void)
-{
- of_irq_init(irq_match);
-}
-
static struct of_device_id omap_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },
@@ -66,7 +56,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@@ -85,7 +75,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@@ -120,7 +110,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_init,
.timer = &omap3_timer,
@@ -155,7 +145,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap4_init,
.timer = &omap4_timer,
@@ -163,3 +153,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.restart = omap_prcm_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_ARCH_OMAP5
+static const char *omap5_boards_compat[] __initdata = {
+ "ti,omap5",
+ NULL,
+};
+
+DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .map_io = omap5_map_io,
+ .init_early = omap5_init_early,
+ .init_irq = omap_gic_of_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = omap_generic_init,
+ .timer = &omap5_timer,
+ .dt_compat = omap5_boards_compat,
+ .restart = omap_prcm_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0771d22..e66859d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
void omap3_intc_resume_idle(void);
void omap2_intc_handle_irq(struct pt_regs *regs);
void omap3_intc_handle_irq(struct pt_regs *regs);
+void omap_of_init_irq(void);
+void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *omap4_get_l2cache_base(void);
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d25..d316c68 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -21,6 +21,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <mach/hardware.h>
@@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node *node,
return 0;
}
+static struct of_device_id irq_match[] __initdata = {
+ { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+ { }
+};
+
+void __init omap_of_init_irq(void)
+{
+ of_irq_init(irq_match);
+}
+
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 70de277..5d7c083 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,6 +16,8 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -207,3 +209,15 @@ static int __init omap4_sar_ram_init(void)
return 0;
}
early_initcall(omap4_sar_ram_init);
+
+static struct of_device_id irq_match[] __initdata = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+ { }
+};
+
+void __init omap_gic_of_init(void)
+{
+ omap_wakeupgen_init();
+ of_irq_init(irq_match);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Adding the minimal support for OMAP5 soc with device tree.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/mach-omap2/board-generic.c | 39 +++++++++++++++++++++-------------
arch/arm/mach-omap2/common.h | 2 +
arch/arm/mach-omap2/irq.c | 11 +++++++++
arch/arm/mach-omap2/omap4-common.c | 14 ++++++++++++
4 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 098d183..0dd9e3f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,6 +20,7 @@
#include <mach/hardware.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
+#include <mach/omap-wakeupgen.h>
#include <plat/board.h>
#include "common.h"
@@ -32,17 +33,6 @@
#define gic_of_init NULL
#endif
-static struct of_device_id irq_match[] __initdata = {
- { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
- { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
- { }
-};
-
-static void __init omap_init_irq(void)
-{
- of_irq_init(irq_match);
-}
-
static struct of_device_id omap_dt_match_table[] __initdata = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },
@@ -66,7 +56,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@@ -85,7 +75,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
@@ -120,7 +110,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_of_init_irq,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_init,
.timer = &omap3_timer,
@@ -155,7 +145,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap_gic_of_init,
.handle_irq = gic_handle_irq,
.init_machine = omap4_init,
.timer = &omap4_timer,
@@ -163,3 +153,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.restart = omap_prcm_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_ARCH_OMAP5
+static const char *omap5_boards_compat[] __initdata = {
+ "ti,omap5",
+ NULL,
+};
+
+DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .map_io = omap5_map_io,
+ .init_early = omap5_init_early,
+ .init_irq = omap_gic_of_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = omap_generic_init,
+ .timer = &omap5_timer,
+ .dt_compat = omap5_boards_compat,
+ .restart = omap_prcm_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 0771d22..e66859d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
void omap3_intc_resume_idle(void);
void omap2_intc_handle_irq(struct pt_regs *regs);
void omap3_intc_handle_irq(struct pt_regs *regs);
+void omap_of_init_irq(void);
+void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0
extern void __iomem *omap4_get_l2cache_base(void);
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d25..d316c68 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -21,6 +21,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <mach/hardware.h>
@@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node *node,
return 0;
}
+static struct of_device_id irq_match[] __initdata = {
+ { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+ { }
+};
+
+void __init omap_of_init_irq(void)
+{
+ of_irq_init(irq_match);
+}
+
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 70de277..5d7c083 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,6 +16,8 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -207,3 +209,15 @@ static int __init omap4_sar_ram_init(void)
return 0;
}
early_initcall(omap4_sar_ram_init);
+
+static struct of_device_id irq_match[] __initdata = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+ { }
+};
+
+void __init omap_gic_of_init(void)
+{
+ omap_wakeupgen_init();
+ of_irq_init(irq_match);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* Re: [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
2012-05-03 7:26 ` R Sricharan
@ 2012-05-07 13:27 ` Cousson, Benoit
-1 siblings, 0 replies; 126+ messages in thread
From: Cousson, Benoit @ 2012-05-07 13:27 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, tony
Hi Sricharan,
On 5/3/2012 9:26 AM, R Sricharan wrote:
> Adding the minimal support for OMAP5 soc with device tree.
You should probably split that patch since you are doing several things
that are not OMAP5 related.
Do a patch that move the omap_init_irq into the INTC and GIC code first.
Then, you can add a patch to add the OMAP5_DT machine entry.
> Signed-off-by: R Sricharan<r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/board-generic.c | 39 +++++++++++++++++++++-------------
> arch/arm/mach-omap2/common.h | 2 +
> arch/arm/mach-omap2/irq.c | 11 +++++++++
> arch/arm/mach-omap2/omap4-common.c | 14 ++++++++++++
> 4 files changed, 51 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index 098d183..0dd9e3f 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -20,6 +20,7 @@
> #include<mach/hardware.h>
> #include<asm/hardware/gic.h>
> #include<asm/mach/arch.h>
> +#include<mach/omap-wakeupgen.h>
>
> #include<plat/board.h>
> #include "common.h"
> @@ -32,17 +33,6 @@
> #define gic_of_init NULL
> #endif
>
> -static struct of_device_id irq_match[] __initdata = {
> - { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
> - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> - { }
> -};
> -
> -static void __init omap_init_irq(void)
> -{
> - of_irq_init(irq_match);
> -}
> -
> static struct of_device_id omap_dt_match_table[] __initdata = {
> { .compatible = "simple-bus", },
> { .compatible = "ti,omap-infra", },
> @@ -66,7 +56,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap242x_map_io,
> .init_early = omap2420_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap2_intc_handle_irq,
> .init_machine = omap_generic_init,
> .timer =&omap2_timer,
> @@ -85,7 +75,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap243x_map_io,
> .init_early = omap2430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap2_intc_handle_irq,
> .init_machine = omap_generic_init,
> .timer =&omap2_timer,
> @@ -120,7 +110,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap3_map_io,
> .init_early = omap3430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap3_intc_handle_irq,
> .init_machine = omap3_init,
> .timer =&omap3_timer,
> @@ -155,7 +145,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap4_map_io,
> .init_early = omap4430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_gic_of_init,
> .handle_irq = gic_handle_irq,
> .init_machine = omap4_init,
> .timer =&omap4_timer,
> @@ -163,3 +153,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
> .restart = omap_prcm_restart,
> MACHINE_END
> #endif
> +
> +#ifdef CONFIG_ARCH_OMAP5
> +static const char *omap5_boards_compat[] __initdata = {
> + "ti,omap5",
> + NULL,
> +};
> +
> +DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
> + .reserve = omap_reserve,
> + .map_io = omap5_map_io,
> + .init_early = omap5_init_early,
> + .init_irq = omap_gic_of_init,
> + .handle_irq = gic_handle_irq,
> + .init_machine = omap_generic_init,
> + .timer =&omap5_timer,
> + .dt_compat = omap5_boards_compat,
> + .restart = omap_prcm_restart,
> +MACHINE_END
> +#endif
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0771d22..e66859d 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
> void omap3_intc_resume_idle(void);
> void omap2_intc_handle_irq(struct pt_regs *regs);
> void omap3_intc_handle_irq(struct pt_regs *regs);
> +void omap_of_init_irq(void);
In order to be consistent with the GIC function and even the previous
ones, you should name the exported one:
+void omap_intc_of_init(void);
> +void omap_gic_of_init(void);
>
> #ifdef CONFIG_CACHE_L2X0
> extern void __iomem *omap4_get_l2cache_base(void);
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index 65f0d25..d316c68 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -21,6 +21,7 @@
> #include<linux/irqdomain.h>
> #include<linux/of.h>
> #include<linux/of_address.h>
> +#include<linux/of_irq.h>
>
> #include<mach/hardware.h>
>
> @@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node *node,
And thus rename that one that become a private function without the
omap_ prefix.
> return 0;
> }
>
> +static struct of_device_id irq_match[] __initdata = {
> + { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+ { .compatible = "ti,omap2-intc", .data = intc_of_init, },
> + { }
> +};
> +
> +void __init omap_of_init_irq(void)
+void __init omap_intc_of_init(void)
> +{
> + of_irq_init(irq_match);
> +}
Regards,
Benoit
^ permalink raw reply [flat|nested] 126+ messages in thread* [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
@ 2012-05-07 13:27 ` Cousson, Benoit
0 siblings, 0 replies; 126+ messages in thread
From: Cousson, Benoit @ 2012-05-07 13:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sricharan,
On 5/3/2012 9:26 AM, R Sricharan wrote:
> Adding the minimal support for OMAP5 soc with device tree.
You should probably split that patch since you are doing several things
that are not OMAP5 related.
Do a patch that move the omap_init_irq into the INTC and GIC code first.
Then, you can add a patch to add the OMAP5_DT machine entry.
> Signed-off-by: R Sricharan<r.sricharan@ti.com>
> ---
> arch/arm/mach-omap2/board-generic.c | 39 +++++++++++++++++++++-------------
> arch/arm/mach-omap2/common.h | 2 +
> arch/arm/mach-omap2/irq.c | 11 +++++++++
> arch/arm/mach-omap2/omap4-common.c | 14 ++++++++++++
> 4 files changed, 51 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index 098d183..0dd9e3f 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -20,6 +20,7 @@
> #include<mach/hardware.h>
> #include<asm/hardware/gic.h>
> #include<asm/mach/arch.h>
> +#include<mach/omap-wakeupgen.h>
>
> #include<plat/board.h>
> #include "common.h"
> @@ -32,17 +33,6 @@
> #define gic_of_init NULL
> #endif
>
> -static struct of_device_id irq_match[] __initdata = {
> - { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
> - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
> - { }
> -};
> -
> -static void __init omap_init_irq(void)
> -{
> - of_irq_init(irq_match);
> -}
> -
> static struct of_device_id omap_dt_match_table[] __initdata = {
> { .compatible = "simple-bus", },
> { .compatible = "ti,omap-infra", },
> @@ -66,7 +56,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap242x_map_io,
> .init_early = omap2420_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap2_intc_handle_irq,
> .init_machine = omap_generic_init,
> .timer =&omap2_timer,
> @@ -85,7 +75,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap243x_map_io,
> .init_early = omap2430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap2_intc_handle_irq,
> .init_machine = omap_generic_init,
> .timer =&omap2_timer,
> @@ -120,7 +110,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap3_map_io,
> .init_early = omap3430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_of_init_irq,
> .handle_irq = omap3_intc_handle_irq,
> .init_machine = omap3_init,
> .timer =&omap3_timer,
> @@ -155,7 +145,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = omap4_map_io,
> .init_early = omap4430_init_early,
> - .init_irq = omap_init_irq,
> + .init_irq = omap_gic_of_init,
> .handle_irq = gic_handle_irq,
> .init_machine = omap4_init,
> .timer =&omap4_timer,
> @@ -163,3 +153,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
> .restart = omap_prcm_restart,
> MACHINE_END
> #endif
> +
> +#ifdef CONFIG_ARCH_OMAP5
> +static const char *omap5_boards_compat[] __initdata = {
> + "ti,omap5",
> + NULL,
> +};
> +
> +DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
> + .reserve = omap_reserve,
> + .map_io = omap5_map_io,
> + .init_early = omap5_init_early,
> + .init_irq = omap_gic_of_init,
> + .handle_irq = gic_handle_irq,
> + .init_machine = omap_generic_init,
> + .timer =&omap5_timer,
> + .dt_compat = omap5_boards_compat,
> + .restart = omap_prcm_restart,
> +MACHINE_END
> +#endif
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 0771d22..e66859d 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
> void omap3_intc_resume_idle(void);
> void omap2_intc_handle_irq(struct pt_regs *regs);
> void omap3_intc_handle_irq(struct pt_regs *regs);
> +void omap_of_init_irq(void);
In order to be consistent with the GIC function and even the previous
ones, you should name the exported one:
+void omap_intc_of_init(void);
> +void omap_gic_of_init(void);
>
> #ifdef CONFIG_CACHE_L2X0
> extern void __iomem *omap4_get_l2cache_base(void);
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index 65f0d25..d316c68 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -21,6 +21,7 @@
> #include<linux/irqdomain.h>
> #include<linux/of.h>
> #include<linux/of_address.h>
> +#include<linux/of_irq.h>
>
> #include<mach/hardware.h>
>
> @@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node *node,
And thus rename that one that become a private function without the
omap_ prefix.
> return 0;
> }
>
> +static struct of_device_id irq_match[] __initdata = {
> + { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+ { .compatible = "ti,omap2-intc", .data = intc_of_init, },
> + { }
> +};
> +
> +void __init omap_of_init_irq(void)
+void __init omap_intc_of_init(void)
> +{
> + of_irq_init(irq_match);
> +}
Regards,
Benoit
^ permalink raw reply [flat|nested] 126+ messages in thread* Re: [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
2012-05-07 13:27 ` Cousson, Benoit
@ 2012-05-07 14:08 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-07 14:08 UTC (permalink / raw)
To: Cousson, Benoit; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, tony
Hi Benoit,
Thanks for the reviews.
>
>> Adding the minimal support for OMAP5 soc with device tree.
>
>
> You should probably split that patch since you are doing several things that
> are not OMAP5 related.
>
> Do a patch that move the omap_init_irq into the INTC and GIC code first.
>
> Then, you can add a patch to add the OMAP5_DT machine entry.
>
ok, will split this then accordingly.
[snip]
>> @@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
>> void omap3_intc_resume_idle(void);
>> void omap2_intc_handle_irq(struct pt_regs *regs);
>> void omap3_intc_handle_irq(struct pt_regs *regs);
>> +void omap_of_init_irq(void);
>
>
> In order to be consistent with the GIC function and even the previous ones,
> you should name the exported one:
>
> +void omap_intc_of_init(void);
>
Ok, will take care of this rename.
>>
>> @@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node
>> *node,
>
>
> And thus rename that one that become a private function without the omap_
> prefix.
>
ok..
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
@ 2012-05-07 14:08 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-07 14:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Benoit,
Thanks for the reviews.
>
>> Adding the minimal support for OMAP5 soc with device tree.
>
>
> You should probably split that patch since you are doing several things that
> are not OMAP5 related.
>
> Do a patch that move the omap_init_irq into the INTC and GIC code first.
>
> Then, you can add a patch to add the OMAP5_DT machine entry.
>
ok, will split this then accordingly.
[snip]
>> @@ -185,6 +185,8 @@ void omap3_intc_prepare_idle(void);
>> ?void omap3_intc_resume_idle(void);
>> ?void omap2_intc_handle_irq(struct pt_regs *regs);
>> ?void omap3_intc_handle_irq(struct pt_regs *regs);
>> +void omap_of_init_irq(void);
>
>
> In order to be consistent with the GIC function and even the previous ones,
> you should name the exported one:
>
> +void omap_intc_of_init(void);
>
Ok, will take care of this rename.
>>
>> @@ -279,6 +280,16 @@ int __init omap_intc_of_init(struct device_node
>> *node,
>
>
> And thus rename that one that become a private function without the omap_
> prefix.
>
ok..
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
2012-05-07 14:08 ` R, Sricharan
@ 2012-05-07 17:35 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:35 UTC (permalink / raw)
To: R, Sricharan
Cc: Cousson, Benoit, linux-omap, linux-arm-kernel, santosh.shilimkar
* R, Sricharan <r.sricharan@ti.com> [120507 07:12]:
> Hi Benoit,
> Thanks for the reviews.
>
> >
> >> Adding the minimal support for OMAP5 soc with device tree.
> >
> >
> > You should probably split that patch since you are doing several things that
> > are not OMAP5 related.
> >
> > Do a patch that move the omap_init_irq into the INTC and GIC code first.
> >
> > Then, you can add a patch to add the OMAP5_DT machine entry.
> >
> ok, will split this then accordingly.
Thanks, that allows us to remove the dependencies that will easily
cause merge errors adding let's say am33xx here.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 10/13] ARM: OMAP5: board-generic: Add device tree support.
@ 2012-05-07 17:35 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:35 UTC (permalink / raw)
To: linux-arm-kernel
* R, Sricharan <r.sricharan@ti.com> [120507 07:12]:
> Hi Benoit,
> Thanks for the reviews.
>
> >
> >> Adding the minimal support for OMAP5 soc with device tree.
> >
> >
> > You should probably split that patch since you are doing several things that
> > are not OMAP5 related.
> >
> > Do a patch that move the omap_init_irq into the INTC and GIC code first.
> >
> > Then, you can add a patch to add the OMAP5_DT machine entry.
> >
> ok, will split this then accordingly.
Thanks, that allows us to remove the dependencies that will easily
cause merge errors adding let's say am33xx here.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 11/13] arm/dts: OMAP5: Add omap5 dts files
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Adding the minimum device tree files required for
OMAP5 to boot.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
.../devicetree/bindings/arm/omap/omap.txt | 3 +
arch/arm/boot/dts/omap5-evm.dts | 20 ++
arch/arm/boot/dts/omap5.dtsi | 201 ++++++++++++++++++++
3 files changed, 224 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/omap5-evm.dts
create mode 100644 arch/arm/boot/dts/omap5.dtsi
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index e78e8bc..3d450f6 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -47,3 +47,6 @@ Boards:
- AM335X EVM : Software Developement Board for AM335x
compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
+
+- OMAP5 EVM : Evaluation Module
+ compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 0000000..200c39a
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap5.dtsi"
+
+/ {
+ model = "TI OMAP5 EVM board";
+ compatible = "ti,omap5-evm", "ti,omap5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 0000000..b50c28d
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * Carveout for multimedia usecases
+ * It should be the last 48MB of the first 512MB memory part
+ * In theory, it should not even exist. That zone should be reserved
+ * dynamically during the .reserve callback.
+ */
+/memreserve/ 0x9d000000 0x03000000;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,omap5";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ };
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP4 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ *
+ * MPU -+-- MPU_PRIVATE - GIC, L2
+ * |
+ * +----------------+----------+
+ * | | |
+ * + +- EMIF - DDR |
+ * | | |
+ * | + +--------+
+ * | | |
+ * | +- L4_ABE - AESS, MCBSP, TIMERs...
+ * | |
+ * +- L3_MAIN --+- L4_CORE - IPs...
+ * |
+ * +- L4_PER - IPs...
+ * |
+ *
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap5-uart";
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap6-uart";
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread* [PATCH 11/13] arm/dts: OMAP5: Add omap5 dts files
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Adding the minimum device tree files required for
OMAP5 to boot.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
.../devicetree/bindings/arm/omap/omap.txt | 3 +
arch/arm/boot/dts/omap5-evm.dts | 20 ++
arch/arm/boot/dts/omap5.dtsi | 201 ++++++++++++++++++++
3 files changed, 224 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/omap5-evm.dts
create mode 100644 arch/arm/boot/dts/omap5.dtsi
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index e78e8bc..3d450f6 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -47,3 +47,6 @@ Boards:
- AM335X EVM : Software Developement Board for AM335x
compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
+
+- OMAP5 EVM : Evaluation Module
+ compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 0000000..200c39a
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap5.dtsi"
+
+/ {
+ model = "TI OMAP5 EVM board";
+ compatible = "ti,omap5-evm", "ti,omap5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 0000000..b50c28d
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * Carveout for multimedia usecases
+ * It should be the last 48MB of the first 512MB memory part
+ * In theory, it should not even exist. That zone should be reserved
+ * dynamically during the .reserve callback.
+ */
+/memreserve/ 0x9d000000 0x03000000;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,omap5";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu at 0 {
+ compatible = "arm,cortex-a15";
+ };
+ cpu at 1 {
+ compatible = "arm,cortex-a15";
+ };
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP4 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ *
+ * MPU -+-- MPU_PRIVATE - GIC, L2
+ * |
+ * +----------------+----------+
+ * | | |
+ * + +- EMIF - DDR |
+ * | | |
+ * | + +--------+
+ * | | |
+ * | +- L4_ABE - AESS, MCBSP, TIMERs...
+ * | |
+ * +- L3_MAIN --+- L4_CORE - IPs...
+ * |
+ * +- L4_PER - IPs...
+ * |
+ *
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+
+ gic: interrupt-controller at 48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ gpio1: gpio at 4ae10000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio at 48055000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio at 48057000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio at 48059000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio at 4805b000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio at 4805d000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio at 48051000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio at 48053000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial at 4806a000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial at 4806c000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial at 48020000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial at 4806e000 {
+ compatible = "ti,omap4-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial at 48066000 {
+ compatible = "ti,omap5-uart";
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial at 48068000 {
+ compatible = "ti,omap6-uart";
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 2 ++
arch/arm/mach-omap2/Kconfig | 13 ++++++++++++-
arch/arm/plat-omap/Kconfig | 4 ++--
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index d5f00d7..8beba1a 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -234,3 +234,5 @@ CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_ARCH_OMAP5=y
+CONFIG_MACH_OMAP5_SEVM=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8141b76..b50541a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
select REGULATOR
select PM_RUNTIME
select VFP
- select NEON if ARCH_OMAP3 || ARCH_OMAP4
+ select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
select SERIAL_OMAP
select SERIAL_OMAP_CONSOLE
select I2C
@@ -55,6 +55,13 @@ config ARCH_OMAP4
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_CPU_SUSPEND if PM
+config ARCH_OMAP5
+ bool "TI OMAP5"
+ depends on ARCH_OMAP2PLUS
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+
comment "OMAP Core Type"
depends on ARCH_OMAP2
@@ -343,6 +350,10 @@ config MACH_OMAP4_PANDA
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+config MACH_OMAP5_SEVM
+ bool "OMAP5 sevm Board"
+ depends on ARCH_OMAP5
+
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
depends on ARCH_OMAP3
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a..dcfb506 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
select USE_OF
select PROC_DEVICETREE if PROC_FS
help
- "Systems based on OMAP2, OMAP3 or OMAP4"
+ "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
endchoice
@@ -150,7 +150,7 @@ config OMAP_32K_TIMER
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+ currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 2 ++
arch/arm/mach-omap2/Kconfig | 13 ++++++++++++-
arch/arm/plat-omap/Kconfig | 4 ++--
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index d5f00d7..8beba1a 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -234,3 +234,5 @@ CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_ARCH_OMAP5=y
+CONFIG_MACH_OMAP5_SEVM=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8141b76..b50541a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
select REGULATOR
select PM_RUNTIME
select VFP
- select NEON if ARCH_OMAP3 || ARCH_OMAP4
+ select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
select SERIAL_OMAP
select SERIAL_OMAP_CONSOLE
select I2C
@@ -55,6 +55,13 @@ config ARCH_OMAP4
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select ARM_CPU_SUSPEND if PM
+config ARCH_OMAP5
+ bool "TI OMAP5"
+ depends on ARCH_OMAP2PLUS
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+
comment "OMAP Core Type"
depends on ARCH_OMAP2
@@ -343,6 +350,10 @@ config MACH_OMAP4_PANDA
select OMAP_PACKAGE_CBS
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+config MACH_OMAP5_SEVM
+ bool "OMAP5 sevm Board"
+ depends on ARCH_OMAP5
+
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
depends on ARCH_OMAP3
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a..dcfb506 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
select USE_OF
select PROC_DEVICETREE if PROC_FS
help
- "Systems based on OMAP2, OMAP3 or OMAP4"
+ "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
endchoice
@@ -150,7 +150,7 @@ config OMAP_32K_TIMER
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+ currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* Re: [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-03 7:26 ` R Sricharan
@ 2012-05-04 22:58 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:58 UTC (permalink / raw)
To: R Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
> select REGULATOR
> select PM_RUNTIME
> select VFP
> - select NEON if ARCH_OMAP3 || ARCH_OMAP4
> + select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
> select SERIAL_OMAP
> select SERIAL_OMAP_CONSOLE
> select I2C
If we add CONFIG_SOC_OMAP3PLUS and CONFIG_SOC_OMAP4PLUS, then
this becomes more future proof with select NEON if SOC_OMAP3PLUS.
> @@ -55,6 +55,13 @@ config ARCH_OMAP4
> select USB_ARCH_HAS_EHCI if USB_SUPPORT
> select ARM_CPU_SUSPEND if PM
>
> +config ARCH_OMAP5
> + bool "TI OMAP5"
> + depends on ARCH_OMAP2PLUS
> + select CPU_V7
> + select ARM_GIC
> + select HAVE_SMP
No need to have depends on ARCH_OMAP2PLUS, it's all inside
if ARCH_OMAP2PLUS anyways. I removed those already once, but that
had to be reverted because the patch was doing other things too
that did not work out too well..
> @@ -343,6 +350,10 @@ config MACH_OMAP4_PANDA
> select OMAP_PACKAGE_CBS
> select REGULATOR_FIXED_VOLTAGE if REGULATOR
>
> +config MACH_OMAP5_SEVM
> + bool "OMAP5 sevm Board"
> + depends on ARCH_OMAP5
> +
> config OMAP3_EMU
> bool "OMAP3 debugging peripherals"
> depends on ARCH_OMAP3
No need for it here either. Actually, I think this whole chunk
can be now left out since it's DT based?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-04 22:58 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-04 22:58 UTC (permalink / raw)
To: linux-arm-kernel
* R Sricharan <r.sricharan@ti.com> [120503 00:30]:
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
> select REGULATOR
> select PM_RUNTIME
> select VFP
> - select NEON if ARCH_OMAP3 || ARCH_OMAP4
> + select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
> select SERIAL_OMAP
> select SERIAL_OMAP_CONSOLE
> select I2C
If we add CONFIG_SOC_OMAP3PLUS and CONFIG_SOC_OMAP4PLUS, then
this becomes more future proof with select NEON if SOC_OMAP3PLUS.
> @@ -55,6 +55,13 @@ config ARCH_OMAP4
> select USB_ARCH_HAS_EHCI if USB_SUPPORT
> select ARM_CPU_SUSPEND if PM
>
> +config ARCH_OMAP5
> + bool "TI OMAP5"
> + depends on ARCH_OMAP2PLUS
> + select CPU_V7
> + select ARM_GIC
> + select HAVE_SMP
No need to have depends on ARCH_OMAP2PLUS, it's all inside
if ARCH_OMAP2PLUS anyways. I removed those already once, but that
had to be reverted because the patch was doing other things too
that did not work out too well..
> @@ -343,6 +350,10 @@ config MACH_OMAP4_PANDA
> select OMAP_PACKAGE_CBS
> select REGULATOR_FIXED_VOLTAGE if REGULATOR
>
> +config MACH_OMAP5_SEVM
> + bool "OMAP5 sevm Board"
> + depends on ARCH_OMAP5
> +
> config OMAP3_EMU
> bool "OMAP3 debugging peripherals"
> depends on ARCH_OMAP3
No need for it here either. Actually, I think this whole chunk
can be now left out since it's DT based?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-04 22:58 ` Tony Lindgren
@ 2012-05-07 3:35 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-07 3:35 UTC (permalink / raw)
To: Tony Lindgren; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
Hi Tony,
>> - select NEON if ARCH_OMAP3 || ARCH_OMAP4
>> + select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
>> select SERIAL_OMAP
>> select SERIAL_OMAP_CONSOLE
>> select I2C
>
> If we add CONFIG_SOC_OMAP3PLUS and CONFIG_SOC_OMAP4PLUS, then
> this becomes more future proof with select NEON if SOC_OMAP3PLUS.
>
ok. will change this.
>> +config ARCH_OMAP5
>> + bool "TI OMAP5"
>> + depends on ARCH_OMAP2PLUS
>> + select CPU_V7
>> + select ARM_GIC
>> + select HAVE_SMP
>
> No need to have depends on ARCH_OMAP2PLUS, it's all inside
> if ARCH_OMAP2PLUS anyways. I removed those already once, but that
> had to be reverted because the patch was doing other things too
> that did not work out too well..
>ll
ok, will remove this then.
>> +config MACH_OMAP5_SEVM
>> + bool "OMAP5 sevm Board"
>> + depends on ARCH_OMAP5
>> +
>> config OMAP3_EMU
>> bool "OMAP3 debugging peripherals"
>> depends on ARCH_OMAP3
>
> No need for it here either. Actually, I think this whole chunk
> can be now left out since it's DT based?
>he
ok, but the concern here was that without this macro
the print from compress and subsequently early
prints appear broken.
machine_is_omap5_sevm becomes zero without this config and
machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
uncompress.h.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-07 3:35 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-07 3:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
>> - ? ? select NEON if ARCH_OMAP3 || ARCH_OMAP4
>> + ? ? select NEON if ARCH_OMAP3 || ARCH_OMAP4 || ARCH_OMAP5
>> ? ? ? select SERIAL_OMAP
>> ? ? ? select SERIAL_OMAP_CONSOLE
>> ? ? ? select I2C
>
> If we add CONFIG_SOC_OMAP3PLUS and CONFIG_SOC_OMAP4PLUS, then
> this becomes more future proof with select NEON if SOC_OMAP3PLUS.
>
ok. will change this.
>> +config ARCH_OMAP5
>> + ? ? bool "TI OMAP5"
>> + ? ? depends on ARCH_OMAP2PLUS
>> + ? ? select CPU_V7
>> + ? ? select ARM_GIC
>> + ? ? select HAVE_SMP
>
> No need to have depends on ARCH_OMAP2PLUS, it's all inside
> if ARCH_OMAP2PLUS anyways. I removed those already once, but that
> had to be reverted because the patch was doing other things too
> that did not work out too well..
>ll
ok, will remove this then.
>> +config MACH_OMAP5_SEVM
>> + ? ? bool "OMAP5 sevm Board"
>> + ? ? depends on ARCH_OMAP5
>> +
>> ?config OMAP3_EMU
>> ? ? ? bool "OMAP3 debugging peripherals"
>> ? ? ? depends on ARCH_OMAP3
>
> No need for it here either. Actually, I think this whole chunk
> can be now left out since it's DT based?
>he
ok, but the concern here was that without this macro
the print from compress and subsequently early
prints appear broken.
machine_is_omap5_sevm becomes zero without this config and
machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
uncompress.h.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-07 3:35 ` R, Sricharan
@ 2012-05-07 17:37 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:37 UTC (permalink / raw)
To: R, Sricharan; +Cc: linux-omap, linux-arm-kernel, santosh.shilimkar, b-cousson
* R, Sricharan <r.sricharan@ti.com> [120506 20:39]:
> >> +config MACH_OMAP5_SEVM
> >> + bool "OMAP5 sevm Board"
> >> + depends on ARCH_OMAP5
> >> +
> >> config OMAP3_EMU
> >> bool "OMAP3 debugging peripherals"
> >> depends on ARCH_OMAP3
> >
> > No need for it here either. Actually, I think this whole chunk
> > can be now left out since it's DT based?
> >he
> ok, but the concern here was that without this macro
> the print from compress and subsequently early
> prints appear broken.
>
> machine_is_omap5_sevm becomes zero without this config and
> machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
> uncompress.h.
Ah I see.
Tony
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the body of a message to majordomo@vger.kernel.org
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-07 17:37 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 17:37 UTC (permalink / raw)
To: linux-arm-kernel
* R, Sricharan <r.sricharan@ti.com> [120506 20:39]:
> >> +config MACH_OMAP5_SEVM
> >> + ? ? bool "OMAP5 sevm Board"
> >> + ? ? depends on ARCH_OMAP5
> >> +
> >> ?config OMAP3_EMU
> >> ? ? ? bool "OMAP3 debugging peripherals"
> >> ? ? ? depends on ARCH_OMAP3
> >
> > No need for it here either. Actually, I think this whole chunk
> > can be now left out since it's DT based?
> >he
> ok, but the concern here was that without this macro
> the print from compress and subsequently early
> prints appear broken.
>
> machine_is_omap5_sevm becomes zero without this config and
> machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
> uncompress.h.
Ah I see.
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-07 17:37 ` Tony Lindgren
@ 2012-05-08 9:19 ` Cousson, Benoit
-1 siblings, 0 replies; 126+ messages in thread
From: Cousson, Benoit @ 2012-05-08 9:19 UTC (permalink / raw)
To: Tony Lindgren
Cc: R, Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar
Hi Tony,
On 5/7/2012 7:37 PM, Tony Lindgren wrote:
> * R, Sricharan<r.sricharan@ti.com> [120506 20:39]:
>>>> +config MACH_OMAP5_SEVM
>>>> + bool "OMAP5 sevm Board"
>>>> + depends on ARCH_OMAP5
>>>> +
>>>> config OMAP3_EMU
>>>> bool "OMAP3 debugging peripherals"
>>>> depends on ARCH_OMAP3
>>>
>>> No need for it here either. Actually, I think this whole chunk
>>> can be now left out since it's DT based?
>>> he
>> ok, but the concern here was that without this macro
>> the print from compress and subsequently early
>> prints appear broken.
>>
>> machine_is_omap5_sevm becomes zero without this config and
>> machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
>> uncompress.h.
>
> Ah I see.
Mmm, still, I guess this mechanism should be deprecated with DT?
We cannot keep creating fake board entry since we are not supposed to
have MACHINE_ID anymore.
That will break DEBUG_LL for sure, but we knew about that current
limitation with DT.
The point is that we should fix the code to stop relying on a machine id
going forward.
And maybe we can parse the FDT at that time?
Regards,
Benoit
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-08 9:19 ` Cousson, Benoit
0 siblings, 0 replies; 126+ messages in thread
From: Cousson, Benoit @ 2012-05-08 9:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
On 5/7/2012 7:37 PM, Tony Lindgren wrote:
> * R, Sricharan<r.sricharan@ti.com> [120506 20:39]:
>>>> +config MACH_OMAP5_SEVM
>>>> + bool "OMAP5 sevm Board"
>>>> + depends on ARCH_OMAP5
>>>> +
>>>> config OMAP3_EMU
>>>> bool "OMAP3 debugging peripherals"
>>>> depends on ARCH_OMAP3
>>>
>>> No need for it here either. Actually, I think this whole chunk
>>> can be now left out since it's DT based?
>>> he
>> ok, but the concern here was that without this macro
>> the print from compress and subsequently early
>> prints appear broken.
>>
>> machine_is_omap5_sevm becomes zero without this config and
>> machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
>> uncompress.h.
>
> Ah I see.
Mmm, still, I guess this mechanism should be deprecated with DT?
We cannot keep creating fake board entry since we are not supposed to
have MACHINE_ID anymore.
That will break DEBUG_LL for sure, but we knew about that current
limitation with DT.
The point is that we should fix the code to stop relying on a machine id
going forward.
And maybe we can parse the FDT at that time?
Regards,
Benoit
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 12/13] ARM: OMAP5: Add the build support
2012-05-08 9:19 ` Cousson, Benoit
@ 2012-05-08 15:57 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:57 UTC (permalink / raw)
To: Cousson, Benoit
Cc: R, Sricharan, linux-omap, linux-arm-kernel, santosh.shilimkar
* Cousson, Benoit <b-cousson@ti.com> [120508 02:23]:
> Hi Tony,
>
> On 5/7/2012 7:37 PM, Tony Lindgren wrote:
> >* R, Sricharan<r.sricharan@ti.com> [120506 20:39]:
> >>>>+config MACH_OMAP5_SEVM
> >>>>+ bool "OMAP5 sevm Board"
> >>>>+ depends on ARCH_OMAP5
> >>>>+
> >>>> config OMAP3_EMU
> >>>> bool "OMAP3 debugging peripherals"
> >>>> depends on ARCH_OMAP3
> >>>
> >>>No need for it here either. Actually, I think this whole chunk
> >>>can be now left out since it's DT based?
> >>>he
> >> ok, but the concern here was that without this macro
> >> the print from compress and subsequently early
> >>prints appear broken.
> >>
> >>machine_is_omap5_sevm becomes zero without this config and
> >>machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
> >>uncompress.h.
> >
> >Ah I see.
>
> Mmm, still, I guess this mechanism should be deprecated with DT?
> We cannot keep creating fake board entry since we are not supposed
> to have MACHINE_ID anymore.
> That will break DEBUG_LL for sure, but we knew about that current
> limitation with DT.
For most usecases for DEBUG_LL we can get away in two steps:
1. Debug output for uncompress code based on DT parsing (I think
this is already there)
2. Early console/earlyprintk parsed from DT that gets set up in
init_early
This should be enough for most users, then the people who need
to debug early kernel code until init_early is done can patch
it in manually.
> The point is that we should fix the code to stop relying on a
> machine id going forward.
> And maybe we can parse the FDT at that time?
Yes that should be trivial for most use cases, we just need
to initialize the earlycon/earlyprintk based on the DT.
See kernel/early_printk.c for more info. We just need to
set up the hardware specific function for early_write instead
of printch.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 12/13] ARM: OMAP5: Add the build support
@ 2012-05-08 15:57 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:57 UTC (permalink / raw)
To: linux-arm-kernel
* Cousson, Benoit <b-cousson@ti.com> [120508 02:23]:
> Hi Tony,
>
> On 5/7/2012 7:37 PM, Tony Lindgren wrote:
> >* R, Sricharan<r.sricharan@ti.com> [120506 20:39]:
> >>>>+config MACH_OMAP5_SEVM
> >>>>+ bool "OMAP5 sevm Board"
> >>>>+ depends on ARCH_OMAP5
> >>>>+
> >>>> config OMAP3_EMU
> >>>> bool "OMAP3 debugging peripherals"
> >>>> depends on ARCH_OMAP3
> >>>
> >>>No need for it here either. Actually, I think this whole chunk
> >>>can be now left out since it's DT based?
> >>>he
> >> ok, but the concern here was that without this macro
> >> the print from compress and subsequently early
> >>prints appear broken.
> >>
> >>machine_is_omap5_sevm becomes zero without this config and
> >>machine_is_xxxx is used by the macro _DEBUG_LL_ENTRY
> >>uncompress.h.
> >
> >Ah I see.
>
> Mmm, still, I guess this mechanism should be deprecated with DT?
> We cannot keep creating fake board entry since we are not supposed
> to have MACHINE_ID anymore.
> That will break DEBUG_LL for sure, but we knew about that current
> limitation with DT.
For most usecases for DEBUG_LL we can get away in two steps:
1. Debug output for uncompress code based on DT parsing (I think
this is already there)
2. Early console/earlyprintk parsed from DT that gets set up in
init_early
This should be enough for most users, then the people who need
to debug early kernel code until init_early is done can patch
it in manually.
> The point is that we should fix the code to stop relying on a
> machine id going forward.
> And maybe we can parse the FDT at that time?
Yes that should be trivial for most use cases, we just need
to initialize the earlycon/earlyprintk based on the DT.
See kernel/early_printk.c for more info. We just need to
set up the hardware specific function for early_write instead
of printch.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 13/13] ARM: Kconfig update to support additional GPIOs in OMAP5
2012-05-03 7:26 ` R Sricharan
@ 2012-05-03 7:26 ` R Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-omap
Cc: linux-arm-kernel, santosh.shilimkar, tony, b-cousson, r.sricharan
From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Reported-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d4..d649c16 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1602,6 +1602,7 @@ config ARCH_NR_GPIO
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
+ default 512 if ARCH_OMAP5
default 0
help
Maximum number of GPIOs in the system.
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* [PATCH 13/13] ARM: Kconfig update to support additional GPIOs in OMAP5
@ 2012-05-03 7:26 ` R Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R Sricharan @ 2012-05-03 7:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Reported-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
arch/arm/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d4..d649c16 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1602,6 +1602,7 @@ config ARCH_NR_GPIO
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
+ default 512 if ARCH_OMAP5
default 0
help
Maximum number of GPIOs in the system.
--
1.7.1
^ permalink raw reply related [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-03 7:26 ` R Sricharan
@ 2012-05-07 9:49 ` Santosh Shilimkar
-1 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-07 9:49 UTC (permalink / raw)
To: tony; +Cc: R Sricharan, linux-omap, linux-arm-kernel, b-cousson
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> The series adds minimal OMAP5 support.
> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> hence large part of the peripherals are re-used.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
> Series is generated against the 3.4-rc5. This has been rebased on
> top of the OMAP2+ cleanup series [1]
>
> To get the boot working with omap2plus_defconfig,
> OMAP5 hwmod/clock/prm/cm database needs to be added.
> The data and the integrated tree are available in the
> below git repository
>
> OMAP5_DATA:
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> omap5_data
>
> OMAP5_INTEGRATED:
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> omap5_dt_integrated
>
> The series is boot tested on OMAP5430 ES1.0.
> OMAP2/3/4 build and boot is tested as well to avoid any breakage
> because of the series.
>
> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> can be dropped once rebased against [2]
>
> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> temporary and can be dropped once rebased against [3]
>
>
> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> [3] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67166.html
>
Do you have a branch where above dependencies are merged ?
How do you suggest to go about updating this series so
that above dependencies plus DT support(3.3 based branch
in arm-soc tree and needs to be updated against 3.4) is
base tree for the patchset.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-07 9:49 ` Santosh Shilimkar
0 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-07 9:49 UTC (permalink / raw)
To: linux-arm-kernel
Tony,
On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> The series adds minimal OMAP5 support.
> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> hence large part of the peripherals are re-used.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
> Series is generated against the 3.4-rc5. This has been rebased on
> top of the OMAP2+ cleanup series [1]
>
> To get the boot working with omap2plus_defconfig,
> OMAP5 hwmod/clock/prm/cm database needs to be added.
> The data and the integrated tree are available in the
> below git repository
>
> OMAP5_DATA:
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> omap5_data
>
> OMAP5_INTEGRATED:
> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> omap5_dt_integrated
>
> The series is boot tested on OMAP5430 ES1.0.
> OMAP2/3/4 build and boot is tested as well to avoid any breakage
> because of the series.
>
> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> can be dropped once rebased against [2]
>
> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> temporary and can be dropped once rebased against [3]
>
>
> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
>
Do you have a branch where above dependencies are merged ?
How do you suggest to go about updating this series so
that above dependencies plus DT support(3.3 based branch
in arm-soc tree and needs to be updated against 3.4) is
base tree for the patchset.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-07 9:49 ` Santosh Shilimkar
@ 2012-05-07 22:26 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 22:26 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: R Sricharan, linux-omap, linux-arm-kernel, b-cousson
* Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
> Tony,
>
> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> > The series adds minimal OMAP5 support.
> > OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> > L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> > hence large part of the peripherals are re-used.
> >
> > OMAP5432 is another variant of OMAP5430, with a
> > memory controller supporting DDR3 and SATA.
> >
> > Series is generated against the 3.4-rc5. This has been rebased on
> > top of the OMAP2+ cleanup series [1]
> >
> > To get the boot working with omap2plus_defconfig,
> > OMAP5 hwmod/clock/prm/cm database needs to be added.
> > The data and the integrated tree are available in the
> > below git repository
> >
> > OMAP5_DATA:
> > git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> > omap5_data
> >
> > OMAP5_INTEGRATED:
> > git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> > omap5_dt_integrated
> >
> > The series is boot tested on OMAP5430 ES1.0.
> > OMAP2/3/4 build and boot is tested as well to avoid any breakage
> > because of the series.
> >
> > Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> > can be dropped once rebased against [2]
> >
> > Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> > temporary and can be dropped once rebased against [3]
> >
> >
> > [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> > [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> > [3] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67166.html
> >
> Do you have a branch where above dependencies are merged ?
Seems like those should go into the cleanup branch, and then
that can be used as a base.
> How do you suggest to go about updating this series so
> that above dependencies plus DT support(3.3 based branch
> in arm-soc tree and needs to be updated against 3.4) is
> base tree for the patchset.
Probably the DT patch should be separate, we can make dt branch
depend on the cleanup branch.
Then the data files should be first posted for reviews (and potentially
updated for what we have queued in hwmod-cleanup). Does this series
compile on it's own without the data now?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-07 22:26 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-07 22:26 UTC (permalink / raw)
To: linux-arm-kernel
* Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
> Tony,
>
> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> > The series adds minimal OMAP5 support.
> > OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> > L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> > hence large part of the peripherals are re-used.
> >
> > OMAP5432 is another variant of OMAP5430, with a
> > memory controller supporting DDR3 and SATA.
> >
> > Series is generated against the 3.4-rc5. This has been rebased on
> > top of the OMAP2+ cleanup series [1]
> >
> > To get the boot working with omap2plus_defconfig,
> > OMAP5 hwmod/clock/prm/cm database needs to be added.
> > The data and the integrated tree are available in the
> > below git repository
> >
> > OMAP5_DATA:
> > git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> > omap5_data
> >
> > OMAP5_INTEGRATED:
> > git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> > omap5_dt_integrated
> >
> > The series is boot tested on OMAP5430 ES1.0.
> > OMAP2/3/4 build and boot is tested as well to avoid any breakage
> > because of the series.
> >
> > Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> > can be dropped once rebased against [2]
> >
> > Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> > temporary and can be dropped once rebased against [3]
> >
> >
> > [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> > [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> > [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
> >
> Do you have a branch where above dependencies are merged ?
Seems like those should go into the cleanup branch, and then
that can be used as a base.
> How do you suggest to go about updating this series so
> that above dependencies plus DT support(3.3 based branch
> in arm-soc tree and needs to be updated against 3.4) is
> base tree for the patchset.
Probably the DT patch should be separate, we can make dt branch
depend on the cleanup branch.
Then the data files should be first posted for reviews (and potentially
updated for what we have queued in hwmod-cleanup). Does this series
compile on it's own without the data now?
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-07 22:26 ` Tony Lindgren
@ 2012-05-08 7:24 ` Santosh Shilimkar
-1 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-08 7:24 UTC (permalink / raw)
To: Tony Lindgren; +Cc: R Sricharan, linux-omap, linux-arm-kernel, b-cousson
On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
>> Tony,
>>
>> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
>>> The series adds minimal OMAP5 support.
>>> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
>>> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
>>> hence large part of the peripherals are re-used.
>>>
>>> OMAP5432 is another variant of OMAP5430, with a
>>> memory controller supporting DDR3 and SATA.
>>>
>>> Series is generated against the 3.4-rc5. This has been rebased on
>>> top of the OMAP2+ cleanup series [1]
>>>
>>> To get the boot working with omap2plus_defconfig,
>>> OMAP5 hwmod/clock/prm/cm database needs to be added.
>>> The data and the integrated tree are available in the
>>> below git repository
>>>
>>> OMAP5_DATA:
>>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
>>> omap5_data
>>>
>>> OMAP5_INTEGRATED:
>>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
>>> omap5_dt_integrated
>>>
>>> The series is boot tested on OMAP5430 ES1.0.
>>> OMAP2/3/4 build and boot is tested as well to avoid any breakage
>>> because of the series.
>>>
>>> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
>>> can be dropped once rebased against [2]
>>>
>>> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
>>> temporary and can be dropped once rebased against [3]
>>>
>>>
>>> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
>>> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
>>> [3] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67166.html
>>>
>> Do you have a branch where above dependencies are merged ?
>
> Seems like those should go into the cleanup branch, and then
> that can be used as a base.
>
Yep. That will be a good base.
>> How do you suggest to go about updating this series so
>> that above dependencies plus DT support(3.3 based branch
>> in arm-soc tree and needs to be updated against 3.4) is
>> base tree for the patchset.
>
> Probably the DT patch should be separate, we can make dt branch
> depend on the cleanup branch.
>
Sounds good. Btw, who is re-basing the omap-dt branch against 3.4 ?
> Then the data files should be first posted for reviews (and potentially
> updated for what we have queued in hwmod-cleanup). Does this series
> compile on it's own without the data now?
>
This series does compile on it's own without data patches. Data
patches needs to re-based against Paul's clean-up and also we
need to sort out ES1/ES2 diff so they can wait till then.
Probably 3.6+
This series was intentionally made in such a way that it can
be merged without data patches. Just for getting boot working
on OMAP5 data patches needs to be merged.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-08 7:24 ` Santosh Shilimkar
0 siblings, 0 replies; 126+ messages in thread
From: Santosh Shilimkar @ 2012-05-08 7:24 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
> * Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
>> Tony,
>>
>> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
>>> The series adds minimal OMAP5 support.
>>> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
>>> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
>>> hence large part of the peripherals are re-used.
>>>
>>> OMAP5432 is another variant of OMAP5430, with a
>>> memory controller supporting DDR3 and SATA.
>>>
>>> Series is generated against the 3.4-rc5. This has been rebased on
>>> top of the OMAP2+ cleanup series [1]
>>>
>>> To get the boot working with omap2plus_defconfig,
>>> OMAP5 hwmod/clock/prm/cm database needs to be added.
>>> The data and the integrated tree are available in the
>>> below git repository
>>>
>>> OMAP5_DATA:
>>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
>>> omap5_data
>>>
>>> OMAP5_INTEGRATED:
>>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
>>> omap5_dt_integrated
>>>
>>> The series is boot tested on OMAP5430 ES1.0.
>>> OMAP2/3/4 build and boot is tested as well to avoid any breakage
>>> because of the series.
>>>
>>> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
>>> can be dropped once rebased against [2]
>>>
>>> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
>>> temporary and can be dropped once rebased against [3]
>>>
>>>
>>> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
>>> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
>>> [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
>>>
>> Do you have a branch where above dependencies are merged ?
>
> Seems like those should go into the cleanup branch, and then
> that can be used as a base.
>
Yep. That will be a good base.
>> How do you suggest to go about updating this series so
>> that above dependencies plus DT support(3.3 based branch
>> in arm-soc tree and needs to be updated against 3.4) is
>> base tree for the patchset.
>
> Probably the DT patch should be separate, we can make dt branch
> depend on the cleanup branch.
>
Sounds good. Btw, who is re-basing the omap-dt branch against 3.4 ?
> Then the data files should be first posted for reviews (and potentially
> updated for what we have queued in hwmod-cleanup). Does this series
> compile on it's own without the data now?
>
This series does compile on it's own without data patches. Data
patches needs to re-based against Paul's clean-up and also we
need to sort out ES1/ES2 diff so they can wait till then.
Probably 3.6+
This series was intentionally made in such a way that it can
be merged without data patches. Just for getting boot working
on OMAP5 data patches needs to be merged.
Regards
Santosh
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-08 7:24 ` Santosh Shilimkar
@ 2012-05-08 15:58 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:58 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: R Sricharan, linux-omap, linux-arm-kernel, b-cousson
* Santosh Shilimkar <santosh.shilimkar@ti.com> [120508 00:27]:
> On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
> > * Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
> >> Tony,
> >>
> >> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> >>> The series adds minimal OMAP5 support.
> >>> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> >>> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> >>> hence large part of the peripherals are re-used.
> >>>
> >>> OMAP5432 is another variant of OMAP5430, with a
> >>> memory controller supporting DDR3 and SATA.
> >>>
> >>> Series is generated against the 3.4-rc5. This has been rebased on
> >>> top of the OMAP2+ cleanup series [1]
> >>>
> >>> To get the boot working with omap2plus_defconfig,
> >>> OMAP5 hwmod/clock/prm/cm database needs to be added.
> >>> The data and the integrated tree are available in the
> >>> below git repository
> >>>
> >>> OMAP5_DATA:
> >>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> >>> omap5_data
> >>>
> >>> OMAP5_INTEGRATED:
> >>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> >>> omap5_dt_integrated
> >>>
> >>> The series is boot tested on OMAP5430 ES1.0.
> >>> OMAP2/3/4 build and boot is tested as well to avoid any breakage
> >>> because of the series.
> >>>
> >>> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> >>> can be dropped once rebased against [2]
> >>>
> >>> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> >>> temporary and can be dropped once rebased against [3]
> >>>
> >>>
> >>> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> >>> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> >>> [3] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg67166.html
> >>>
> >> Do you have a branch where above dependencies are merged ?
> >
> > Seems like those should go into the cleanup branch, and then
> > that can be used as a base.
> >
> Yep. That will be a good base.
>
> >> How do you suggest to go about updating this series so
> >> that above dependencies plus DT support(3.3 based branch
> >> in arm-soc tree and needs to be updated against 3.4) is
> >> base tree for the patchset.
> >
> > Probably the DT patch should be separate, we can make dt branch
> > depend on the cleanup branch.
> >
> Sounds good. Btw, who is re-basing the omap-dt branch against 3.4 ?
That's already queued up, I can merge in some trivial v3.4 based patches
Benoit has and it gets updated automatically.
> > Then the data files should be first posted for reviews (and potentially
> > updated for what we have queued in hwmod-cleanup). Does this series
> > compile on it's own without the data now?
> >
> This series does compile on it's own without data patches. Data
> patches needs to re-based against Paul's clean-up and also we
> need to sort out ES1/ES2 diff so they can wait till then.
> Probably 3.6+
OK good.
> This series was intentionally made in such a way that it can
> be merged without data patches. Just for getting boot working
> on OMAP5 data patches needs to be merged.
Great, excellent.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-08 15:58 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-08 15:58 UTC (permalink / raw)
To: linux-arm-kernel
* Santosh Shilimkar <santosh.shilimkar@ti.com> [120508 00:27]:
> On Tuesday 08 May 2012 03:56 AM, Tony Lindgren wrote:
> > * Santosh Shilimkar <santosh.shilimkar@ti.com> [120507 02:53]:
> >> Tony,
> >>
> >> On Thursday 03 May 2012 12:56 PM, R Sricharan wrote:
> >>> The series adds minimal OMAP5 support.
> >>> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> >>> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> >>> hence large part of the peripherals are re-used.
> >>>
> >>> OMAP5432 is another variant of OMAP5430, with a
> >>> memory controller supporting DDR3 and SATA.
> >>>
> >>> Series is generated against the 3.4-rc5. This has been rebased on
> >>> top of the OMAP2+ cleanup series [1]
> >>>
> >>> To get the boot working with omap2plus_defconfig,
> >>> OMAP5 hwmod/clock/prm/cm database needs to be added.
> >>> The data and the integrated tree are available in the
> >>> below git repository
> >>>
> >>> OMAP5_DATA:
> >>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> >>> omap5_data
> >>>
> >>> OMAP5_INTEGRATED:
> >>> git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
> >>> omap5_dt_integrated
> >>>
> >>> The series is boot tested on OMAP5430 ES1.0.
> >>> OMAP2/3/4 build and boot is tested as well to avoid any breakage
> >>> because of the series.
> >>>
> >>> Patch "TEMP: ARM: OMAP5: Add cpu_is_omap54xx() checks" is temporary and
> >>> can be dropped once rebased against [2]
> >>>
> >>> Patch "TEMP: ARM: OMAP5: Update the base address of the 32k-counter" is
> >>> temporary and can be dropped once rebased against [3]
> >>>
> >>>
> >>> [1] http://www.spinics.net/lists/linux-omap/msg69233.html
> >>> [2] http://www.spinics.net/lists/linux-omap/msg69013.html
> >>> [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67166.html
> >>>
> >> Do you have a branch where above dependencies are merged ?
> >
> > Seems like those should go into the cleanup branch, and then
> > that can be used as a base.
> >
> Yep. That will be a good base.
>
> >> How do you suggest to go about updating this series so
> >> that above dependencies plus DT support(3.3 based branch
> >> in arm-soc tree and needs to be updated against 3.4) is
> >> base tree for the patchset.
> >
> > Probably the DT patch should be separate, we can make dt branch
> > depend on the cleanup branch.
> >
> Sounds good. Btw, who is re-basing the omap-dt branch against 3.4 ?
That's already queued up, I can merge in some trivial v3.4 based patches
Benoit has and it gets updated automatically.
> > Then the data files should be first posted for reviews (and potentially
> > updated for what we have queued in hwmod-cleanup). Does this series
> > compile on it's own without the data now?
> >
> This series does compile on it's own without data patches. Data
> patches needs to re-based against Paul's clean-up and also we
> need to sort out ES1/ES2 diff so they can wait till then.
> Probably 3.6+
OK good.
> This series was intentionally made in such a way that it can
> be merged without data patches. Just for getting boot working
> on OMAP5 data patches needs to be merged.
Great, excellent.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* RE: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-03 7:26 ` R Sricharan
@ 2012-05-10 17:43 ` Sricharan R
-1 siblings, 0 replies; 126+ messages in thread
From: Sricharan R @ 2012-05-10 17:43 UTC (permalink / raw)
To: linux-omap; +Cc: linux-arm-kernel, Santosh Shilimkar, tony, Benoit Cousson
Hi Tony,
> -----Original Message-----
> From: R Sricharan [mailto:r.sricharan@ti.com]
> Sent: Thursday, May 03, 2012 12:56 PM
> To: linux-omap@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; santosh.shilimkar@ti.com;
> tony@atomide.com; b-cousson@ti.com; r.sricharan@ti.com
> Subject: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
>
> The series adds minimal OMAP5 support.
> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> hence large part of the peripherals are re-used.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
OMAP5 V2 series is ready with all comments addressed, but I have
below dependencies to be merged to apply my series against your
cleanup-soc branch
1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
3) https://github.com/hvaibhav/am335x-linux 32ksync-timer-cleanup
4) http://www.spinics.net/lists/arm-kernel/msg174461.html
Can you please let me know how you want me to prepare the series
with these dependencies.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-10 17:43 ` Sricharan R
0 siblings, 0 replies; 126+ messages in thread
From: Sricharan R @ 2012-05-10 17:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
> -----Original Message-----
> From: R Sricharan [mailto:r.sricharan at ti.com]
> Sent: Thursday, May 03, 2012 12:56 PM
> To: linux-omap at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; santosh.shilimkar at ti.com;
> tony at atomide.com; b-cousson at ti.com; r.sricharan at ti.com
> Subject: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
>
> The series adds minimal OMAP5 support.
> OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> hence large part of the peripherals are re-used.
>
> OMAP5432 is another variant of OMAP5430, with a
> memory controller supporting DDR3 and SATA.
>
OMAP5 V2 series is ready with all comments addressed, but I have
below dependencies to be merged to apply my series against your
cleanup-soc branch
1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
3) https://github.com/hvaibhav/am335x-linux 32ksync-timer-cleanup
4) http://www.spinics.net/lists/arm-kernel/msg174461.html
Can you please let me know how you want me to prepare the series
with these dependencies.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-10 17:43 ` Sricharan R
@ 2012-05-11 20:11 ` Tony Lindgren
-1 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-11 20:11 UTC (permalink / raw)
To: Sricharan R
Cc: linux-omap, linux-arm-kernel, Santosh Shilimkar, Benoit Cousson
Hi,
* Sricharan R <r.sricharan@ti.com> [120510 10:47]:
> Hi Tony,
>
> > -----Original Message-----
> > From: R Sricharan [mailto:r.sricharan@ti.com]
> > Sent: Thursday, May 03, 2012 12:56 PM
> > To: linux-omap@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org; santosh.shilimkar@ti.com;
> > tony@atomide.com; b-cousson@ti.com; r.sricharan@ti.com
> > Subject: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
> >
> > The series adds minimal OMAP5 support.
> > OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> > L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> > hence large part of the peripherals are re-used.
> >
> > OMAP5432 is another variant of OMAP5430, with a
> > memory controller supporting DDR3 and SATA.
> >
> OMAP5 V2 series is ready with all comments addressed, but I have
> below dependencies to be merged to apply my series against your
> cleanup-soc branch
OK
> 1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
This one is not merged in yet and it seems that we're out of time
for v3.5 unless it drags on and we have -rc8 after -rc7.
> 2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
> 3) https://github.com/hvaibhav/am335x-linux 32ksync-timer-cleanup
These two are merged in arm-soc now.
> 4) http://www.spinics.net/lists/arm-kernel/msg174461.html
I think this series still has some pending comments?
> Can you please let me know how you want me to prepare the series
> with these dependencies.
Until these dependencies get cleared out, it seems that the best
branch to base your patches is omap-cleanup-timer-for-v3.5 tag
and just carry the pending patches for a little bit longer.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-11 20:11 ` Tony Lindgren
0 siblings, 0 replies; 126+ messages in thread
From: Tony Lindgren @ 2012-05-11 20:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
* Sricharan R <r.sricharan@ti.com> [120510 10:47]:
> Hi Tony,
>
> > -----Original Message-----
> > From: R Sricharan [mailto:r.sricharan at ti.com]
> > Sent: Thursday, May 03, 2012 12:56 PM
> > To: linux-omap at vger.kernel.org
> > Cc: linux-arm-kernel at lists.infradead.org; santosh.shilimkar at ti.com;
> > tony at atomide.com; b-cousson at ti.com; r.sricharan at ti.com
> > Subject: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
> >
> > The series adds minimal OMAP5 support.
> > OMAP5430 has a dual core Cortex-A15 based MPU subsystem with 2MB
> > L2 cache. The SOC has many compatible blocks with OMAP4 SOCS and
> > hence large part of the peripherals are re-used.
> >
> > OMAP5432 is another variant of OMAP5430, with a
> > memory controller supporting DDR3 and SATA.
> >
> OMAP5 V2 series is ready with all comments addressed, but I have
> below dependencies to be merged to apply my series against your
> cleanup-soc branch
OK
> 1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
This one is not merged in yet and it seems that we're out of time
for v3.5 unless it drags on and we have -rc8 after -rc7.
> 2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
> 3) https://github.com/hvaibhav/am335x-linux 32ksync-timer-cleanup
These two are merged in arm-soc now.
> 4) http://www.spinics.net/lists/arm-kernel/msg174461.html
I think this series still has some pending comments?
> Can you please let me know how you want me to prepare the series
> with these dependencies.
Until these dependencies get cleared out, it seems that the best
branch to base your patches is omap-cleanup-timer-for-v3.5 tag
and just carry the pending patches for a little bit longer.
Regards,
Tony
^ permalink raw reply [flat|nested] 126+ messages in thread
* Re: [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
2012-05-11 20:11 ` Tony Lindgren
@ 2012-05-14 4:50 ` R, Sricharan
-1 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-14 4:50 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-omap, linux-arm-kernel, Santosh Shilimkar, Benoit Cousson
Tony,
Thanks for you suggestions
>> OMAP5 V2 series is ready with all comments addressed, but I have
>> below dependencies to be merged to apply my series against your
>> cleanup-soc branch
>
> OK
>
>> 1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
>
> This one is not merged in yet and it seems that we're out of time
> for v3.5 unless it drags on and we have -rc8 after -rc7.
>
OK
>> 2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
>> 3) https://github.com/hvaibhav/am335x-linux 32ksync-timer-cleanup
>
> These two are merged in arm-soc now.
>
OK
>> 4) http://www.spinics.net/lists/arm-kernel/msg174461.html
>
> I think this series still has some pending comments?
>
Yes, right. In fact except for the last patch,
others should not be needed when rebased against
paul's PRCM cleanups which is yet to be posted and
[1] which is already acked now.
1) http://www.spinics.net/lists/linux-omap/msg70192.html
>> Can you please let me know how you want me to prepare the series
>> with these dependencies.
>
> Until these dependencies get cleared out, it seems that the best
> branch to base your patches is omap-cleanup-timer-for-v3.5 tag
> and just carry the pending patches for a little bit longer.
>
Ok, will rebase against it then and then prepare the series with a couple
of temporary patches that can be dropped when the above mentioned dependencies
are sorted out.
Thanks,
Sricharan
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^ permalink raw reply [flat|nested] 126+ messages in thread
* [PATCH 00/13] ARM: OMAP5: Add minimal OMAP5 SOC support
@ 2012-05-14 4:50 ` R, Sricharan
0 siblings, 0 replies; 126+ messages in thread
From: R, Sricharan @ 2012-05-14 4:50 UTC (permalink / raw)
To: linux-arm-kernel
Tony,
Thanks for you suggestions
>> ?OMAP5 V2 series is ready with all comments addressed, but I have
>> ?below dependencies to be merged to apply my series against your
>> ?cleanup-soc branch
>
> OK
>
>> ?1) git://git.pwsan.com/linux-2.6 hwmod_soc_conditional_cleanup_3.5
>
> This one is not merged in yet and it seems that we're out of time
> for v3.5 unless it drags on and we have -rc8 after -rc7.
>
OK
>> ?2) git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.5
>> ?3) https://github.com/hvaibhav/am335x-linux ? 32ksync-timer-cleanup
>
> These two are merged in arm-soc now.
>
OK
>> ?4) http://www.spinics.net/lists/arm-kernel/msg174461.html
>
> I think this series still has some pending comments?
>
Yes, right. In fact except for the last patch,
others should not be needed when rebased against
paul's PRCM cleanups which is yet to be posted and
[1] which is already acked now.
1) http://www.spinics.net/lists/linux-omap/msg70192.html
>> ?Can you please let me know how you want me to prepare the series
>> ?with these dependencies.
>
> Until these dependencies get cleared out, it seems that the best
> branch to base your patches is omap-cleanup-timer-for-v3.5 tag
> and just carry the pending patches for a little bit longer.
>
Ok, will rebase against it then and then prepare the series with a couple
of temporary patches that can be dropped when the above mentioned dependencies
are sorted out.
Thanks,
Sricharan
^ permalink raw reply [flat|nested] 126+ messages in thread