* [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
This is v2 of the series to add initial support for the latest new SoC,
AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
detail can be found in the patch descriptions, also see AM64X Technical
Reference Manual (SPRUIM2, Nov 2020) for further details:
https://www.ti.com/lit/pdf/spruim2
Since v1, several new bindings have made it in linux-next so we can
now include those nodes using them here. The spi, i2c, and mmc nodes
have now been added along with DMA support. Specifics about changes
from v1 are included with each patch.
Regards,
Dave
[1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
Dave Gerlach (4):
dt-bindings: arm: ti: Add bindings for AM642 SoC
dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
arm64: dts: ti: Add support for AM642 SoC
arm64: dts: ti: Add support for AM642 EVM
Peter Ujfalusi (1):
arm64: dts: ti: k3-am64-main: Enable DMA support
.../devicetree/bindings/arm/ti/k3.yaml | 6 +
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
include/dt-bindings/pinctrl/k3.h | 5 +-
8 files changed, 920 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 1/5] dt-bindings: arm: ti: Add bindings for AM642 SoC
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 16:39 ` Dave Gerlach
-1 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Vignesh Raghavendra, Suman Anna, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20201125052004.17823-2-d-gerlach@ti.com/
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index c6e1c1e63e43..393f94a64f8d 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -33,6 +33,12 @@ properties:
items:
- const: ti,j7200
+ - description: K3 AM642 SoC
+ items:
+ - enum:
+ - ti,am642-evm
+ - const: ti,am642
+
additionalProperties: true
...
--
2.28.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v2 1/5] dt-bindings: arm: ti: Add bindings for AM642 SoC
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20201125052004.17823-2-d-gerlach@ti.com/
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index c6e1c1e63e43..393f94a64f8d 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -33,6 +33,12 @@ properties:
items:
- const: ti,j7200
+ - description: K3 AM642 SoC
+ items:
+ - enum:
+ - ti,am642-evm
+ - const: ti,am642
+
additionalProperties: true
...
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/5] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 16:39 ` Dave Gerlach
-1 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Vignesh Raghavendra, Suman Anna, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju
Add pinctrl macros for AM64 SoC. These macro definitions are similar to
that of previous platforms, but adding new definitions to avoid any
naming confusions in the soc dts files.
Unlike what checkpatch insists, we do not need parentheses enclosing
the values for this macro as we do intend it to generate two separate
values as has been done for other similar platforms.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* New patch to add needed macros for pinctrl in board dts.
include/dt-bindings/pinctrl/k3.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index b0eea7cc6e23..e085f102b283 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -3,7 +3,7 @@
* This header provides constants for pinctrl bindings for TI's K3 SoC
* family.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
#define _DT_BINDINGS_PINCTRL_TI_K3_H
@@ -35,4 +35,7 @@
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/5] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
Add pinctrl macros for AM64 SoC. These macro definitions are similar to
that of previous platforms, but adding new definitions to avoid any
naming confusions in the soc dts files.
Unlike what checkpatch insists, we do not need parentheses enclosing
the values for this macro as we do intend it to generate two separate
values as has been done for other similar platforms.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* New patch to add needed macros for pinctrl in board dts.
include/dt-bindings/pinctrl/k3.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index b0eea7cc6e23..e085f102b283 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -3,7 +3,7 @@
* This header provides constants for pinctrl bindings for TI's K3 SoC
* family.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
#define _DT_BINDINGS_PINCTRL_TI_K3_H
@@ -35,4 +35,7 @@
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 16:39 ` Dave Gerlach
-1 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Vignesh Raghavendra, Suman Anna, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable ramdisk or MMC
boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
under cbass_main and the i2c, spi, and uart MCU domain periperhals
under cbass_mcu.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* Add i2c. sdhci. and spi nodes to cbass_main
* Add cbass_mcu with uart, i2c, and spi nodes
* Add oc_sram node
* Add additional ranges for main_cbass to cover all use cases.
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++
arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++
4 files changed, 576 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
new file mode 100644
index 000000000000..e65fdb358c4c
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x70000000 0x200000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x1a000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ dmss: dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ dmsc: dmsc@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_pmx0: pinctrl@f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2d0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_conf: syscon@43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x43000000 0x20000>;
+
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00000014 0x4>;
+ };
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ dmas = <&main_pktdma 0x8000>, <&main_pktdma 0>;
+ dma-names = "tx0", "rx0";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ };
+
+ main_spi3: spi@20130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20130000 0x00 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 144 0>;
+ };
+
+ main_spi4: spi@20140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20140000 0x00 0x400>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 145 0>;
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am64-sdhci-8bit";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,otap-del-sel-hs400 = <0x4>;
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am64-sdhci-4bit";
+ reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,clkbuf-sel = <0x7>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
new file mode 100644
index 000000000000..1d2be485a669
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM64 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial@4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart1: serial@4a10000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a10000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_i2c0: i2c@4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ };
+
+ mcu_i2c1: i2c@4910000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04910000 0x00 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 2>;
+ clock-names = "fck";
+ };
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
new file mode 100644
index 000000000000..a35a0aff50f8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 AM642 SoC";
+ compatible = "ti,am642";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &mcu_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ };
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f4000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
+ <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
+ <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+ <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
+ <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
+
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am64-main.dtsi"
+#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
new file mode 100644
index 000000000000..e2b397c88401
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC family in Dual core configuration
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am64.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable ramdisk or MMC
boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
under cbass_main and the i2c, spi, and uart MCU domain periperhals
under cbass_mcu.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* Add i2c. sdhci. and spi nodes to cbass_main
* Add cbass_mcu with uart, i2c, and spi nodes
* Add oc_sram node
* Add additional ranges for main_cbass to cover all use cases.
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++
arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++
4 files changed, 576 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
new file mode 100644
index 000000000000..e65fdb358c4c
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x70000000 0x200000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x1a000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ dmss: dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ dmsc: dmsc@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_pmx0: pinctrl@f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2d0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_conf: syscon@43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x43000000 0x20000>;
+
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00000014 0x4>;
+ };
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ dmas = <&main_pktdma 0x8000>, <&main_pktdma 0>;
+ dma-names = "tx0", "rx0";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ };
+
+ main_spi3: spi@20130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20130000 0x00 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 144 0>;
+ };
+
+ main_spi4: spi@20140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20140000 0x00 0x400>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 145 0>;
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am64-sdhci-8bit";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,otap-del-sel-hs400 = <0x4>;
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am64-sdhci-4bit";
+ reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,clkbuf-sel = <0x7>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
new file mode 100644
index 000000000000..1d2be485a669
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM64 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial@4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart1: serial@4a10000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a10000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_i2c0: i2c@4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ };
+
+ mcu_i2c1: i2c@4910000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04910000 0x00 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 2>;
+ clock-names = "fck";
+ };
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
new file mode 100644
index 000000000000..a35a0aff50f8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 AM642 SoC";
+ compatible = "ti,am642";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &mcu_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ };
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f4000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
+ <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
+ <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+ <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
+ <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
+
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am64-main.dtsi"
+#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
new file mode 100644
index 000000000000..e2b397c88401
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC family in Dual core configuration
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am64.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+};
--
2.28.0
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 17:24 ` Sudeep Holla
-1 siblings, 0 replies; 28+ messages in thread
From: Sudeep Holla @ 2021-01-19 17:24 UTC (permalink / raw)
To: Dave Gerlach
Cc: Nishanth Menon, devicetree, Vignesh Raghavendra, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On Tue, Jan 19, 2021 at 10:39:25AM -0600, Dave Gerlach wrote:
> The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
> providing advanced system integration to enable applications such as
> Motor Drives, PLC, Remote IO and IoT Gateways.
>
> Some highlights of this SoC are:
> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
> MCUs, and a single Cortex-M4F.
> * Two Gigabit Industrial Communication Subsystems (ICSSG).
> * Integrated Ethernet switch supporting up to a total of two external
> ports.
> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
> peripherals.
> * Centralized System Controller for Security, Power, and Resource
> Management (DMSC).
>
> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
> for further details: https://www.ti.com/lit/pdf/spruim2
>
> Introduce basic support for the AM642 SoC to enable ramdisk or MMC
> boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
> under cbass_main and the i2c, spi, and uart MCU domain periperhals
> under cbass_mcu.
>
> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> v1 -> v2:
> * Add i2c. sdhci. and spi nodes to cbass_main
> * Add cbass_mcu with uart, i2c, and spi nodes
> * Add oc_sram node
> * Add additional ranges for main_cbass to cover all use cases.
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++
> 4 files changed, 576 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> new file mode 100644
> index 000000000000..a35a0aff50f8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for AM642 SoC Family
> + *
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +/ {
> + model = "Texas Instruments K3 AM642 SoC";
> + compatible = "ti,am642";
> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &mcu_uart0;
> + serial1 = &mcu_uart1;
> + serial2 = &main_uart0;
> + serial3 = &main_uart1;
> + serial4 = &main_uart2;
> + serial5 = &main_uart3;
> + serial6 = &main_uart4;
> + serial7 = &main_uart5;
> + serial8 = &main_uart6;
> + };
> +
> + chosen { };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> + };
> +
> + a53_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,armv8-pmuv3";
Is this just copy paste from some DTS or do we really don't know which CPU
this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ?
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
@ 2021-01-19 17:24 ` Sudeep Holla
0 siblings, 0 replies; 28+ messages in thread
From: Sudeep Holla @ 2021-01-19 17:24 UTC (permalink / raw)
To: Dave Gerlach
Cc: Nishanth Menon, devicetree, Vignesh Raghavendra, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On Tue, Jan 19, 2021 at 10:39:25AM -0600, Dave Gerlach wrote:
> The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
> providing advanced system integration to enable applications such as
> Motor Drives, PLC, Remote IO and IoT Gateways.
>
> Some highlights of this SoC are:
> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
> MCUs, and a single Cortex-M4F.
> * Two Gigabit Industrial Communication Subsystems (ICSSG).
> * Integrated Ethernet switch supporting up to a total of two external
> ports.
> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
> peripherals.
> * Centralized System Controller for Security, Power, and Resource
> Management (DMSC).
>
> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
> for further details: https://www.ti.com/lit/pdf/spruim2
>
> Introduce basic support for the AM642 SoC to enable ramdisk or MMC
> boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals
> under cbass_main and the i2c, spi, and uart MCU domain periperhals
> under cbass_mcu.
>
> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> v1 -> v2:
> * Add i2c. sdhci. and spi nodes to cbass_main
> * Add cbass_mcu with uart, i2c, and spi nodes
> * Add oc_sram node
> * Add additional ranges for main_cbass to cover all use cases.
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++
> 4 files changed, 576 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> new file mode 100644
> index 000000000000..a35a0aff50f8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for AM642 SoC Family
> + *
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +/ {
> + model = "Texas Instruments K3 AM642 SoC";
> + compatible = "ti,am642";
> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &mcu_uart0;
> + serial1 = &mcu_uart1;
> + serial2 = &main_uart0;
> + serial3 = &main_uart1;
> + serial4 = &main_uart2;
> + serial5 = &main_uart3;
> + serial6 = &main_uart4;
> + serial7 = &main_uart5;
> + serial8 = &main_uart6;
> + };
> +
> + chosen { };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> + };
> +
> + a53_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,armv8-pmuv3";
Is this just copy paste from some DTS or do we really don't know which CPU
this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ?
--
Regards,
Sudeep
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
2021-01-19 17:24 ` Sudeep Holla
@ 2021-01-19 18:35 ` Nishanth Menon
-1 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-19 18:35 UTC (permalink / raw)
To: Sudeep Holla
Cc: Dave Gerlach, devicetree, Vignesh Raghavendra, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 17:24-20210119, Sudeep Holla wrote:
[..]
> > + pmu: pmu {
> > + compatible = "arm,armv8-pmuv3";
>
> Is this just copy paste from some DTS or do we really don't know which CPU
> this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ?
Heh, Nice catch :).. yeah, this should be arm,cortex-a53-pmu -> I think the
original dts predates Documentation/devicetree/bindings/arm/pmu.yaml
I better fixup other dts as well (separate series ofcourse)..
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC
@ 2021-01-19 18:35 ` Nishanth Menon
0 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-19 18:35 UTC (permalink / raw)
To: Sudeep Holla
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 17:24-20210119, Sudeep Holla wrote:
[..]
> > + pmu: pmu {
> > + compatible = "arm,armv8-pmuv3";
>
> Is this just copy paste from some DTS or do we really don't know which CPU
> this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ?
Heh, Nice catch :).. yeah, this should be arm,cortex-a53-pmu -> I think the
original dts predates Documentation/devicetree/bindings/arm/pmu.yaml
I better fixup other dts as well (separate series ofcourse)..
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 16:39 ` Dave Gerlach
-1 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Vignesh Raghavendra, Suman Anna, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju
From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
DMAs in the system.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* New patch from v1
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index e65fdb358c4c..d0c804111079 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -49,6 +49,8 @@ dmss: dmss {
dma-ranges;
ranges;
+ ti,sci-dev-id = <25>;
+
secure_proxy_main: mailbox@4d000000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
@@ -59,6 +61,78 @@ secure_proxy_main: mailbox@4d000000 {
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #address-cells = <0>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <4 68 36>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>, /* SAUL_TX_1_CHAN */
+ <0x27>, /* ICSSG_0_TX_CHAN */
+ <0x28>; /* ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>, /* RING_SAUL_TX_1_CHAN */
+ <0x14>, /* RING_ICSSG_0_TX_CHAN */
+ <0x15>; /* RING_ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>, /* SAUL_RX_3_CHAN */
+ <0x35>, /* ICSSG_0_RX_CHAN */
+ <0x37>; /* ICSSG_1_RX_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+ <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+ <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+ };
};
dmsc: dmsc@44043000 {
--
2.28.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
DMAs in the system.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* New patch from v1
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index e65fdb358c4c..d0c804111079 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -49,6 +49,8 @@ dmss: dmss {
dma-ranges;
ranges;
+ ti,sci-dev-id = <25>;
+
secure_proxy_main: mailbox@4d000000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
@@ -59,6 +61,78 @@ secure_proxy_main: mailbox@4d000000 {
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #address-cells = <0>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <4 68 36>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>, /* SAUL_TX_1_CHAN */
+ <0x27>, /* ICSSG_0_TX_CHAN */
+ <0x28>; /* ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>, /* RING_SAUL_TX_1_CHAN */
+ <0x14>, /* RING_ICSSG_0_TX_CHAN */
+ <0x15>; /* RING_ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>, /* SAUL_RX_3_CHAN */
+ <0x35>, /* ICSSG_0_RX_CHAN */
+ <0x37>; /* ICSSG_1_RX_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+ <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+ <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+ };
};
dmsc: dmsc@44043000 {
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-21 13:27 ` Vignesh Raghavendra
-1 siblings, 0 replies; 28+ messages in thread
From: Vignesh Raghavendra @ 2021-01-21 13:27 UTC (permalink / raw)
To: Dave Gerlach, Nishanth Menon
Cc: linux-arm-kernel, devicetree, Rob Herring, Tony Lindgren,
Suman Anna, Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla,
Aswath Govindraju
On 1/19/21 10:09 PM, Dave Gerlach wrote:
> From: Peter Ujfalusi <peter.ujfalusi@ti.com>
>
> Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
> DMAs in the system.
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Regards
Vignesh
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
@ 2021-01-21 13:27 ` Vignesh Raghavendra
0 siblings, 0 replies; 28+ messages in thread
From: Vignesh Raghavendra @ 2021-01-21 13:27 UTC (permalink / raw)
To: Dave Gerlach, Nishanth Menon
Cc: devicetree, Tony Lindgren, Sekhar Nori, Kishon Vijay Abraham,
Lokesh Vutla, Rob Herring, Aswath Govindraju, linux-arm-kernel
On 1/19/21 10:09 PM, Dave Gerlach wrote:
> From: Peter Ujfalusi <peter.ujfalusi@ti.com>
>
> Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
> DMAs in the system.
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Regards
Vignesh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
2021-01-21 13:27 ` Vignesh Raghavendra
@ 2021-01-21 14:21 ` Nishanth Menon
-1 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-21 14:21 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Suman Anna, Sekhar Nori, Kishon Vijay Abraham,
Lokesh Vutla, Aswath Govindraju
On 18:57-20210121, Vignesh Raghavendra wrote:
>
>
> On 1/19/21 10:09 PM, Dave Gerlach wrote:
> > From: Peter Ujfalusi <peter.ujfalusi@ti.com>
> >
> > Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
> > DMAs in the system.
> >
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> > ---
>
> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Is V3 of this series valid as well?
https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-5-d-gerlach@ti.com/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
@ 2021-01-21 14:21 ` Nishanth Menon
0 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-21 14:21 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: devicetree, Dave Gerlach, Tony Lindgren, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 18:57-20210121, Vignesh Raghavendra wrote:
>
>
> On 1/19/21 10:09 PM, Dave Gerlach wrote:
> > From: Peter Ujfalusi <peter.ujfalusi@ti.com>
> >
> > Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
> > DMAs in the system.
> >
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> > Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> > ---
>
> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Is V3 of this series valid as well?
https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-5-d-gerlach@ti.com/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
2021-01-21 14:21 ` Nishanth Menon
@ 2021-01-21 15:03 ` Vignesh Raghavendra
-1 siblings, 0 replies; 28+ messages in thread
From: Vignesh Raghavendra @ 2021-01-21 15:03 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Suman Anna, Sekhar Nori, Kishon Vijay Abraham,
Lokesh Vutla, Aswath Govindraju
On 1/21/21 7:51 PM, Nishanth Menon wrote:
> On 18:57-20210121, Vignesh Raghavendra wrote:
>>
>>
>> On 1/19/21 10:09 PM, Dave Gerlach wrote:
>>> From: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>>
>>> Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
>>> DMAs in the system.
>>>
>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>>> ---
>>
>> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
>
> Is V3 of this series valid as well?
>
> https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-5-d-gerlach@ti.com/
>
>
Sorry, did not notice v3. However this patch has not changed. So, feel
free to carried forward the R-by to v3.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: ti: k3-am64-main: Enable DMA support
@ 2021-01-21 15:03 ` Vignesh Raghavendra
0 siblings, 0 replies; 28+ messages in thread
From: Vignesh Raghavendra @ 2021-01-21 15:03 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Dave Gerlach, Tony Lindgren, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 1/21/21 7:51 PM, Nishanth Menon wrote:
> On 18:57-20210121, Vignesh Raghavendra wrote:
>>
>>
>> On 1/19/21 10:09 PM, Dave Gerlach wrote:
>>> From: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>>
>>> Add the nodes for DMSS INTA, BCDMA and PKTDMA to enable the use of the
>>> DMAs in the system.
>>>
>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
>>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>>> ---
>>
>> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
>
> Is V3 of this series valid as well?
>
> https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-5-d-gerlach@ti.com/
>
>
Sorry, did not notice v3. However this patch has not changed. So, feel
free to carried forward the R-by to v3.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/5] arm64: dts: ti: Add support for AM642 EVM
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-19 16:39 ` Dave Gerlach
-1 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, linux-arm-kernel, devicetree, Rob Herring,
Tony Lindgren, Vignesh Raghavendra, Suman Anna, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Aswath Govindraju
The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.
Introduce support for the AM642 EVM to enable mmc boot, including
enabling UART, I2C, and SPI on the board.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* Add regulators on board needed to enable sdhci for mmc card
* Add pin settings for new nodes
* Add i2c1 and gpio exapnder needed for mmc
* Add support for OSD9616P0899-10 96x16 passive matrix display.
* Add support for onboard spi eeprom
* Mark mcu uart, i2c, and spi nodes as disabled
* Add sdhci nodes which enables mmc rootfs.
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 ++++++++++++++++++++++++
2 files changed, 260 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 65506f21ba30..c687739e2bca 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -11,3 +11,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
+
+dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
new file mode 100644
index 000000000000..50b1ae1314a1
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "k3-am642.dtsi"
+
+/ {
+ compatible = "ti,am642-evm", "ti,am642";
+ model = "Texas Instruments AM642 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixed-regulator-sd {
+ /* TPS2051BD */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vddb: fixedregulator-vddb {
+ compatible = "regulator-fixed";
+ regulator-name = "vddb_3v3_display";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "am64-evm:red:heartbeat";
+ gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "off";
+ };
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+ >;
+ };
+
+ main_spi0_pins_default: main-spi0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
+ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
+ AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
+ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+/* main_uart1 is reserved for firmware usage */
+&main_uart1 {
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&mcu_uart1 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* osd9616p0899-10 */
+ display@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&vddb>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
+};
+
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins_default>;
+ ti,pindir-d0-out-d1-in = <1>;
+ eeprom@0 {
+ compatible = "eeprom-93xx46";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cs-high;
+ data-size = <16>;
+ };
+};
+
+&mcu_spi0 {
+ status = "disabled";
+};
+
+&mcu_spi1 {
+ status = "disabled";
+};
+
+&sdhci0 {
+ /* emmc */
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v2 5/5] arm64: dts: ti: Add support for AM642 EVM
@ 2021-01-19 16:39 ` Dave Gerlach
0 siblings, 0 replies; 28+ messages in thread
From: Dave Gerlach @ 2021-01-19 16:39 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.
Introduce support for the AM642 EVM to enable mmc boot, including
enabling UART, I2C, and SPI on the board.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
v1 -> v2:
* Add regulators on board needed to enable sdhci for mmc card
* Add pin settings for new nodes
* Add i2c1 and gpio exapnder needed for mmc
* Add support for OSD9616P0899-10 96x16 passive matrix display.
* Add support for onboard spi eeprom
* Mark mcu uart, i2c, and spi nodes as disabled
* Add sdhci nodes which enables mmc rootfs.
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 ++++++++++++++++++++++++
2 files changed, 260 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 65506f21ba30..c687739e2bca 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -11,3 +11,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
+
+dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
new file mode 100644
index 000000000000..50b1ae1314a1
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "k3-am642.dtsi"
+
+/ {
+ compatible = "ti,am642-evm", "ti,am642";
+ model = "Texas Instruments AM642 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixed-regulator-sd {
+ /* TPS2051BD */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vddb: fixedregulator-vddb {
+ compatible = "regulator-fixed";
+ regulator-name = "vddb_3v3_display";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "am64-evm:red:heartbeat";
+ gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "off";
+ };
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+ >;
+ };
+
+ main_spi0_pins_default: main-spi0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
+ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
+ AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
+ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+/* main_uart1 is reserved for firmware usage */
+&main_uart1 {
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&mcu_uart1 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* osd9616p0899-10 */
+ display@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&vddb>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
+};
+
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_spi0_pins_default>;
+ ti,pindir-d0-out-d1-in = <1>;
+ eeprom@0 {
+ compatible = "eeprom-93xx46";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cs-high;
+ data-size = <16>;
+ };
+};
+
+&mcu_spi0 {
+ status = "disabled";
+};
+
+&mcu_spi1 {
+ status = "disabled";
+};
+
+&sdhci0 {
+ /* emmc */
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.28.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
2021-01-19 16:39 ` Dave Gerlach
@ 2021-01-21 13:22 ` Grygorii Strashko
-1 siblings, 0 replies; 28+ messages in thread
From: Grygorii Strashko @ 2021-01-21 13:22 UTC (permalink / raw)
To: Dave Gerlach, Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 19/01/2021 18:39, Dave Gerlach wrote:
> This is v2 of the series to add initial support for the latest new SoC,
> AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
> detail can be found in the patch descriptions, also see AM64X Technical
> Reference Manual (SPRUIM2, Nov 2020) for further details:
> https://www.ti.com/lit/pdf/spruim2
>
> Since v1, several new bindings have made it in linux-next so we can
> now include those nodes using them here. The spi, i2c, and mmc nodes
> have now been added along with DMA support. Specifics about changes
> from v1 are included with each patch.
>
> Regards,
> Dave
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
>
> Dave Gerlach (4):
> dt-bindings: arm: ti: Add bindings for AM642 SoC
> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> arm64: dts: ti: Add support for AM642 SoC
> arm64: dts: ti: Add support for AM642 EVM
>
> Peter Ujfalusi (1):
> arm64: dts: ti: k3-am64-main: Enable DMA support
>
> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> arch/arm64/boot/dts/ti/Makefile | 2 +
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
> include/dt-bindings/pinctrl/k3.h | 5 +-
> 8 files changed, 920 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
--
Best regards,
grygorii
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
@ 2021-01-21 13:22 ` Grygorii Strashko
0 siblings, 0 replies; 28+ messages in thread
From: Grygorii Strashko @ 2021-01-21 13:22 UTC (permalink / raw)
To: Dave Gerlach, Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Tony Lindgren, Sekhar Nori,
Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 19/01/2021 18:39, Dave Gerlach wrote:
> This is v2 of the series to add initial support for the latest new SoC,
> AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
> detail can be found in the patch descriptions, also see AM64X Technical
> Reference Manual (SPRUIM2, Nov 2020) for further details:
> https://www.ti.com/lit/pdf/spruim2
>
> Since v1, several new bindings have made it in linux-next so we can
> now include those nodes using them here. The spi, i2c, and mmc nodes
> have now been added along with DMA support. Specifics about changes
> from v1 are included with each patch.
>
> Regards,
> Dave
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
>
> Dave Gerlach (4):
> dt-bindings: arm: ti: Add bindings for AM642 SoC
> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> arm64: dts: ti: Add support for AM642 SoC
> arm64: dts: ti: Add support for AM642 EVM
>
> Peter Ujfalusi (1):
> arm64: dts: ti: k3-am64-main: Enable DMA support
>
> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> arch/arm64/boot/dts/ti/Makefile | 2 +
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
> include/dt-bindings/pinctrl/k3.h | 5 +-
> 8 files changed, 920 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
--
Best regards,
grygorii
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
2021-01-21 13:22 ` Grygorii Strashko
@ 2021-01-21 14:21 ` Nishanth Menon
-1 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-21 14:21 UTC (permalink / raw)
To: Grygorii Strashko
Cc: Dave Gerlach, devicetree, Vignesh Raghavendra, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 15:22-20210121, Grygorii Strashko wrote:
>
>
> On 19/01/2021 18:39, Dave Gerlach wrote:
> > This is v2 of the series to add initial support for the latest new SoC,
> > AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
> > detail can be found in the patch descriptions, also see AM64X Technical
> > Reference Manual (SPRUIM2, Nov 2020) for further details:
> > https://www.ti.com/lit/pdf/spruim2
> >
> > Since v1, several new bindings have made it in linux-next so we can
> > now include those nodes using them here. The spi, i2c, and mmc nodes
> > have now been added along with DMA support. Specifics about changes
> > from v1 are included with each patch.
> >
> > Regards,
> > Dave
> >
> > [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
> >
> > Dave Gerlach (4):
> > dt-bindings: arm: ti: Add bindings for AM642 SoC
> > dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> > arm64: dts: ti: Add support for AM642 SoC
> > arm64: dts: ti: Add support for AM642 EVM
> >
> > Peter Ujfalusi (1):
> > arm64: dts: ti: k3-am64-main: Enable DMA support
> >
> > .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> > arch/arm64/boot/dts/ti/Makefile | 2 +
> > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
> > arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
> > arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
> > arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
> > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
> > include/dt-bindings/pinctrl/k3.h | 5 +-
> > 8 files changed, 920 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
> >
>
> Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
>
Can you see if your reviews and tested apply to V3 of the series as well?
https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-1-d-gerlach@ti.com/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
@ 2021-01-21 14:21 ` Nishanth Menon
0 siblings, 0 replies; 28+ messages in thread
From: Nishanth Menon @ 2021-01-21 14:21 UTC (permalink / raw)
To: Grygorii Strashko
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 15:22-20210121, Grygorii Strashko wrote:
>
>
> On 19/01/2021 18:39, Dave Gerlach wrote:
> > This is v2 of the series to add initial support for the latest new SoC,
> > AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
> > detail can be found in the patch descriptions, also see AM64X Technical
> > Reference Manual (SPRUIM2, Nov 2020) for further details:
> > https://www.ti.com/lit/pdf/spruim2
> >
> > Since v1, several new bindings have made it in linux-next so we can
> > now include those nodes using them here. The spi, i2c, and mmc nodes
> > have now been added along with DMA support. Specifics about changes
> > from v1 are included with each patch.
> >
> > Regards,
> > Dave
> >
> > [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
> >
> > Dave Gerlach (4):
> > dt-bindings: arm: ti: Add bindings for AM642 SoC
> > dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> > arm64: dts: ti: Add support for AM642 SoC
> > arm64: dts: ti: Add support for AM642 EVM
> >
> > Peter Ujfalusi (1):
> > arm64: dts: ti: k3-am64-main: Enable DMA support
> >
> > .../devicetree/bindings/arm/ti/k3.yaml | 6 +
> > arch/arm64/boot/dts/ti/Makefile | 2 +
> > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
> > arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
> > arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
> > arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
> > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
> > include/dt-bindings/pinctrl/k3.h | 5 +-
> > 8 files changed, 920 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
> >
>
> Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
>
Can you see if your reviews and tested apply to V3 of the series as well?
https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-1-d-gerlach@ti.com/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
2021-01-21 14:21 ` Nishanth Menon
@ 2021-01-21 14:44 ` Grygorii Strashko
-1 siblings, 0 replies; 28+ messages in thread
From: Grygorii Strashko @ 2021-01-21 14:44 UTC (permalink / raw)
To: Nishanth Menon
Cc: Dave Gerlach, devicetree, Vignesh Raghavendra, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 21/01/2021 16:21, Nishanth Menon wrote:
> On 15:22-20210121, Grygorii Strashko wrote:
>>
>>
>> On 19/01/2021 18:39, Dave Gerlach wrote:
>>> This is v2 of the series to add initial support for the latest new SoC,
>>> AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
>>> detail can be found in the patch descriptions, also see AM64X Technical
>>> Reference Manual (SPRUIM2, Nov 2020) for further details:
>>> https://www.ti.com/lit/pdf/spruim2
>>>
>>> Since v1, several new bindings have made it in linux-next so we can
>>> now include those nodes using them here. The spi, i2c, and mmc nodes
>>> have now been added along with DMA support. Specifics about changes
>>> from v1 are included with each patch.
>>>
>>> Regards,
>>> Dave
>>>
>>> [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
>>>
>>> Dave Gerlach (4):
>>> dt-bindings: arm: ti: Add bindings for AM642 SoC
>>> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
>>> arm64: dts: ti: Add support for AM642 SoC
>>> arm64: dts: ti: Add support for AM642 EVM
>>>
>>> Peter Ujfalusi (1):
>>> arm64: dts: ti: k3-am64-main: Enable DMA support
>>>
>>> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
>>> arch/arm64/boot/dts/ti/Makefile | 2 +
>>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
>>> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
>>> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
>>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
>>> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
>>> include/dt-bindings/pinctrl/k3.h | 5 +-
>>> 8 files changed, 920 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>>>
>>
>> Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
>> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
>>
>
> Can you see if your reviews and tested apply to V3 of the series as well?
>
> https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-1-d-gerlach@ti.com/
>
Yes. They do apply.
--
Best regards,
grygorii
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] arm64: Initial support for Texas Instruments AM642 Platform
@ 2021-01-21 14:44 ` Grygorii Strashko
0 siblings, 0 replies; 28+ messages in thread
From: Grygorii Strashko @ 2021-01-21 14:44 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, Vignesh Raghavendra, Dave Gerlach, Tony Lindgren,
Sekhar Nori, Kishon Vijay Abraham, Lokesh Vutla, Rob Herring,
Aswath Govindraju, linux-arm-kernel
On 21/01/2021 16:21, Nishanth Menon wrote:
> On 15:22-20210121, Grygorii Strashko wrote:
>>
>>
>> On 19/01/2021 18:39, Dave Gerlach wrote:
>>> This is v2 of the series to add initial support for the latest new SoC,
>>> AM642, from Texas Instruments. Version 1 can be found at [1]. Additional
>>> detail can be found in the patch descriptions, also see AM64X Technical
>>> Reference Manual (SPRUIM2, Nov 2020) for further details:
>>> https://www.ti.com/lit/pdf/spruim2
>>>
>>> Since v1, several new bindings have made it in linux-next so we can
>>> now include those nodes using them here. The spi, i2c, and mmc nodes
>>> have now been added along with DMA support. Specifics about changes
>>> from v1 are included with each patch.
>>>
>>> Regards,
>>> Dave
>>>
>>> [1] https://lore.kernel.org/linux-arm-kernel/20201125052004.17823-1-d-gerlach@ti.com/
>>>
>>> Dave Gerlach (4):
>>> dt-bindings: arm: ti: Add bindings for AM642 SoC
>>> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
>>> arm64: dts: ti: Add support for AM642 SoC
>>> arm64: dts: ti: Add support for AM642 EVM
>>>
>>> Peter Ujfalusi (1):
>>> arm64: dts: ti: k3-am64-main: Enable DMA support
>>>
>>> .../devicetree/bindings/arm/ti/k3.yaml | 6 +
>>> arch/arm64/boot/dts/ti/Makefile | 2 +
>>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 406 ++++++++++++++++++
>>> arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++
>>> arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++
>>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 258 +++++++++++
>>> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++
>>> include/dt-bindings/pinctrl/k3.h | 5 +-
>>> 8 files changed, 920 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm.dts
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>>>
>>
>> Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
>> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
>>
>
> Can you see if your reviews and tested apply to V3 of the series as well?
>
> https://lore.kernel.org/linux-arm-kernel/20210120202532.9011-1-d-gerlach@ti.com/
>
Yes. They do apply.
--
Best regards,
grygorii
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