[PATCH net 0/7] Xilinx axienet fixes

[PATCH net 0/7] Xilinx axienet fixes

[Robert Hancock]

Various fixes for the Xilinx AXI Ethernet driver.

Robert Hancock (7):
  net: axienet: Reset core before accessing MAC and wait for core ready
  net: axienet: add missing memory barriers
  net: axienet: limit minimum TX ring size
  net: axienet: Fix TX ring slot available check
  net: axienet: fix number of TX ring slots for available check
  net: axienet: fix for TX busy handling
  net: axienet: increase default TX ring size to 128

 .../net/ethernet/xilinx/xilinx_axienet_main.c | 134 +++++++++++-------
 1 file changed, 83 insertions(+), 51 deletions(-)

-- 
2.31.1

[PATCH net 1/7] net: axienet: Reset core before accessing MAC and wait for core ready

[Robert Hancock]

In some cases where the Xilinx Ethernet core was used in 1000Base-X or
SGMII modes, which use the internal PCS/PMA PHY, and the MGT
transceiver clock source for the PCS was not running at the time the
FPGA logic was loaded, the core would come up in a state where the
PCS could not be found on the MDIO bus. To fix this, the Ethernet core
(including the PCS) should be reset after enabling the clocks, prior to
attempting to access the PCS using of_mdio_find_device.

Also, when resetting the device, wait for the PhyRstCmplt bit to be set
in the interrupt status register before continuing initialization, to
ensure that the core is actually ready. The MgtRdy bit could also be
waited for, but unfortunately when using 7-series devices, the bit does
not appear to work as documented (it seems to behave as some sort of
link state indication and not just an indication the transceiver is
ready) so it can't really be relied on.

Fixes: 3e08fd4a8298 (net: axienet: Properly handle PCS/PMA PHY for 1000BaseX mode)
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 34 +++++++++++++------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 90144ac7aee8..f4ae035bed35 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -496,7 +496,8 @@ static void axienet_setoptions(struct net_device *ndev, u32 options)
 
 static int __axienet_device_reset(struct axienet_local *lp)
 {
-	u32 timeout;
+	u32 value;
+	int ret;
 
 	/* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
 	 * process of Axi DMA takes a while to complete as all pending
@@ -506,15 +507,23 @@ static int __axienet_device_reset(struct axienet_local *lp)
 	 * they both reset the entire DMA core, so only one needs to be used.
 	 */
 	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
-	timeout = DELAY_OF_ONE_MILLISEC;
-	while (axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET) &
-				XAXIDMA_CR_RESET_MASK) {
-		udelay(1);
-		if (--timeout == 0) {
-			netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
-				   __func__);
-			return -ETIMEDOUT;
-		}
+	ret = read_poll_timeout(axienet_dma_in32, value,
+				!(value & XAXIDMA_CR_RESET_MASK),
+				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
+				XAXIDMA_TX_CR_OFFSET);
+	if (ret) {
+		dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__);
+		return ret;
+	}
+
+	/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */
+	ret = read_poll_timeout(axienet_ior, value,
+				value & XAE_INT_PHYRSTCMPLT_MASK,
+				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
+				XAE_IS_OFFSET);
+	if (ret) {
+		dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__);
+		return ret;
 	}
 
 	return 0;
@@ -2046,6 +2055,11 @@ static int axienet_probe(struct platform_device *pdev)
 	lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
 	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
 
+	/* Reset core now that clocks are enabled, prior to accessing MDIO */
+	ret = __axienet_device_reset(lp);
+	if (ret)
+		goto cleanup_clk;
+
 	lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
 	if (lp->phy_node) {
 		ret = axienet_mdio_setup(lp);
-- 
2.31.1

[PATCH net 2/7] net: axienet: add missing memory barriers

[Robert Hancock]

This driver was missing some required memory barriers:

Use dma_rmb to ensure we see all updates to the descriptor after we see
that an entry has been completed.

Use wmb and rmb to avoid stale descriptor status between the TX path and
TX complete IRQ path.

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index f4ae035bed35..de8f85175a6c 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -632,6 +632,8 @@ static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
 		if (nr_bds == -1 && !(status & XAXIDMA_BD_STS_COMPLETE_MASK))
 			break;
 
+		/* Ensure we see complete descriptor update */
+		dma_rmb();
 		phys = desc_get_phys_addr(lp, cur_p);
 		dma_unmap_single(ndev->dev.parent, phys,
 				 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
@@ -645,8 +647,10 @@ static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
 		cur_p->app1 = 0;
 		cur_p->app2 = 0;
 		cur_p->app4 = 0;
-		cur_p->status = 0;
 		cur_p->skb = NULL;
+		/* ensure our transmit path and device don't prematurely see status cleared */
+		wmb();
+		cur_p->status = 0;
 
 		if (sizep)
 			*sizep += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
@@ -704,6 +708,9 @@ static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
 					    int num_frag)
 {
 	struct axidma_bd *cur_p;
+
+	/* Ensure we see all descriptor updates from device or TX IRQ path */
+	rmb();
 	cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num];
 	if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
 		return NETDEV_TX_BUSY;
@@ -843,6 +850,8 @@ static void axienet_recv(struct net_device *ndev)
 
 		tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
 
+		/* Ensure we see complete descriptor update */
+		dma_rmb();
 		phys = desc_get_phys_addr(lp, cur_p);
 		dma_unmap_single(ndev->dev.parent, phys, lp->max_frm_size,
 				 DMA_FROM_DEVICE);
-- 
2.31.1

[PATCH net 3/7] net: axienet: limit minimum TX ring size

[Robert Hancock]

The driver will not work properly if the TX ring size is set to below
MAX_SKB_FRAGS + 1 since it needs to hold at least one full maximally
fragmented packet in the TX ring. Limit setting the ring size to below
this value.

Fixes: 8b09ca823ffb4 ("net: axienet: Make RX/TX ring sizes configurable")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index de8f85175a6c..8a60219d3bfb 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -43,6 +43,7 @@
 /* Descriptors defines for Tx and Rx DMA */
 #define TX_BD_NUM_DEFAULT		64
 #define RX_BD_NUM_DEFAULT		1024
+#define TX_BD_NUM_MIN			(MAX_SKB_FRAGS + 1)
 #define TX_BD_NUM_MAX			4096
 #define RX_BD_NUM_MAX			4096
 
@@ -1389,7 +1390,8 @@ axienet_ethtools_set_ringparam(struct net_device *ndev,
 	if (ering->rx_pending > RX_BD_NUM_MAX ||
 	    ering->rx_mini_pending ||
 	    ering->rx_jumbo_pending ||
-	    ering->rx_pending > TX_BD_NUM_MAX)
+	    ering->tx_pending < TX_BD_NUM_MIN ||
+	    ering->tx_pending > TX_BD_NUM_MAX)
 		return -EINVAL;
 
 	if (netif_running(ndev))
-- 
2.31.1

[PATCH net 4/7] net: axienet: Fix TX ring slot available check

[Robert Hancock]

The check for whether a TX ring slot was available was incorrect,
since a slot which had been loaded with transmit data but the device had
not started transmitting would be treated as available, potentially
causing non-transmitted slots to be overwritten. The control field in
the descriptor should be checked, rather than the status field (which may
only be updated when the device completes the entry).

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 8a60219d3bfb..ee8d656200b8 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -643,7 +643,6 @@ static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
 		if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK))
 			dev_consume_skb_irq(cur_p->skb);
 
-		cur_p->cntrl = 0;
 		cur_p->app0 = 0;
 		cur_p->app1 = 0;
 		cur_p->app2 = 0;
@@ -651,6 +650,7 @@ static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
 		cur_p->skb = NULL;
 		/* ensure our transmit path and device don't prematurely see status cleared */
 		wmb();
+		cur_p->cntrl = 0;
 		cur_p->status = 0;
 
 		if (sizep)
@@ -713,7 +713,7 @@ static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
 	/* Ensure we see all descriptor updates from device or TX IRQ path */
 	rmb();
 	cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num];
-	if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
+	if (cur_p->cntrl)
 		return NETDEV_TX_BUSY;
 	return 0;
 }
-- 
2.31.1

[PATCH net 5/7] net: axienet: fix number of TX ring slots for available check

[Robert Hancock]

The check for the number of available TX ring slots was off by 1 since a
slot is required for the skb header as well as each fragment. This could
result in overwriting a TX ring slot that was still in use.

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index ee8d656200b8..c5d214abd4d5 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -747,7 +747,7 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	num_frag = skb_shinfo(skb)->nr_frags;
 	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 
-	if (axienet_check_tx_bd_space(lp, num_frag)) {
+	if (axienet_check_tx_bd_space(lp, num_frag + 1)) {
 		if (netif_queue_stopped(ndev))
 			return NETDEV_TX_BUSY;
 
@@ -757,7 +757,7 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 		smp_mb();
 
 		/* Space might have just been freed - check again */
-		if (axienet_check_tx_bd_space(lp, num_frag))
+		if (axienet_check_tx_bd_space(lp, num_frag + 1))
 			return NETDEV_TX_BUSY;
 
 		netif_wake_queue(ndev);
-- 
2.31.1

[PATCH net 6/7] net: axienet: fix for TX busy handling

[Robert Hancock]

We should be avoiding returning NETDEV_TX_BUSY from ndo_start_xmit in
normal cases. Move the main check for a full TX ring to the end of the
function so that we stop the queue after the last available space is used
up, and only wake up the queue if enough space is available for a full
maximally fragmented packet. Print a warning if there is insufficient
space at the start of start_xmit, since this should no longer happen.

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 85 ++++++++++---------
 1 file changed, 46 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index c5d214abd4d5..2191f813ed78 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -660,6 +660,32 @@ static int axienet_free_tx_chain(struct net_device *ndev, u32 first_bd,
 	return i;
 }
 
+/**
+ * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
+ * @lp:		Pointer to the axienet_local structure
+ * @num_frag:	The number of BDs to check for
+ *
+ * Return: 0, on success
+ *	    NETDEV_TX_BUSY, if any of the descriptors are not free
+ *
+ * This function is invoked before BDs are allocated and transmission starts.
+ * This function returns 0 if a BD or group of BDs can be allocated for
+ * transmission. If the BD or any of the BDs are not free the function
+ * returns a busy status. This is invoked from axienet_start_xmit.
+ */
+static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
+					    int num_frag)
+{
+	struct axidma_bd *cur_p;
+
+	/* Ensure we see all descriptor updates from device or TX IRQ path */
+	rmb();
+	cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num];
+	if (cur_p->cntrl)
+		return NETDEV_TX_BUSY;
+	return 0;
+}
+
 /**
  * axienet_start_xmit_done - Invoked once a transmit is completed by the
  * Axi DMA Tx channel.
@@ -689,33 +715,8 @@ static void axienet_start_xmit_done(struct net_device *ndev)
 	/* Matches barrier in axienet_start_xmit */
 	smp_mb();
 
-	netif_wake_queue(ndev);
-}
-
-/**
- * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
- * @lp:		Pointer to the axienet_local structure
- * @num_frag:	The number of BDs to check for
- *
- * Return: 0, on success
- *	    NETDEV_TX_BUSY, if any of the descriptors are not free
- *
- * This function is invoked before BDs are allocated and transmission starts.
- * This function returns 0 if a BD or group of BDs can be allocated for
- * transmission. If the BD or any of the BDs are not free the function
- * returns a busy status. This is invoked from axienet_start_xmit.
- */
-static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
-					    int num_frag)
-{
-	struct axidma_bd *cur_p;
-
-	/* Ensure we see all descriptor updates from device or TX IRQ path */
-	rmb();
-	cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num];
-	if (cur_p->cntrl)
-		return NETDEV_TX_BUSY;
-	return 0;
+	if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
+		netif_wake_queue(ndev);
 }
 
 /**
@@ -748,19 +749,13 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 
 	if (axienet_check_tx_bd_space(lp, num_frag + 1)) {
-		if (netif_queue_stopped(ndev))
-			return NETDEV_TX_BUSY;
-
+		/* Should not happen as last start_xmit call should have
+		 * checked for sufficient space and queue should only be
+		 * woken when sufficient space is available.
+		 */
 		netif_stop_queue(ndev);
-
-		/* Matches barrier in axienet_start_xmit_done */
-		smp_mb();
-
-		/* Space might have just been freed - check again */
-		if (axienet_check_tx_bd_space(lp, num_frag + 1))
-			return NETDEV_TX_BUSY;
-
-		netif_wake_queue(ndev);
+		netdev_warn(ndev, "TX ring unexpectedly full\n");
+		return NETDEV_TX_BUSY;
 	}
 
 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
@@ -821,6 +816,18 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 	if (++lp->tx_bd_tail >= lp->tx_bd_num)
 		lp->tx_bd_tail = 0;
 
+	/* Stop queue if next transmit may not have space */
+	if (axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1)) {
+		netif_stop_queue(ndev);
+
+		/* Matches barrier in axienet_start_xmit_done */
+		smp_mb();
+
+		/* Space might have just been freed - check again */
+		if (!axienet_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
+			netif_wake_queue(ndev);
+	}
+
 	return NETDEV_TX_OK;
 }
 
-- 
2.31.1

[PATCH net 7/7] net: axienet: increase default TX ring size to 128

[Robert Hancock]

With previous changes to make the driver handle the TX ring size more
correctly, the default TX ring size of 64 appears to significantly
bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
Increasing this to 128 seems to bring performance up to near line rate and
shouldn't cause excess bufferbloat (this driver doesn't yet support modern
byte-based queue management).

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 2191f813ed78..580a4245f8da 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -41,7 +41,7 @@
 #include "xilinx_axienet.h"
 
 /* Descriptors defines for Tx and Rx DMA */
-#define TX_BD_NUM_DEFAULT		64
+#define TX_BD_NUM_DEFAULT		128
 #define RX_BD_NUM_DEFAULT		1024
 #define TX_BD_NUM_MIN			(MAX_SKB_FRAGS + 1)
 #define TX_BD_NUM_MAX			4096
-- 
2.31.1

Re: [PATCH net 1/7] net: axienet: Reset core before accessing MAC and wait for core ready

[Robert Hancock]

On Tue, 2022-01-11 at 15:13 -0600, Robert Hancock wrote:
> In some cases where the Xilinx Ethernet core was used in 1000Base-X or
> SGMII modes, which use the internal PCS/PMA PHY, and the MGT
> transceiver clock source for the PCS was not running at the time the
> FPGA logic was loaded, the core would come up in a state where the
> PCS could not be found on the MDIO bus. To fix this, the Ethernet core
> (including the PCS) should be reset after enabling the clocks, prior to
> attempting to access the PCS using of_mdio_find_device.
> 
> Also, when resetting the device, wait for the PhyRstCmplt bit to be set
> in the interrupt status register before continuing initialization, to
> ensure that the core is actually ready. The MgtRdy bit could also be
> waited for, but unfortunately when using 7-series devices, the bit does
> not appear to work as documented (it seems to behave as some sort of
> link state indication and not just an indication the transceiver is
> ready) so it can't really be relied on.
> 
> Fixes: 3e08fd4a8298 (net: axienet: Properly handle PCS/PMA PHY for 1000BaseX
> mode)

Patchwork points out that this commit doesn't exist in mainline, it's from the
5.10 stable tree. The corresponding mainline commit is
1a02556086fc0eb16e0a0d09043e9ffb0e31c7db.

> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 34 +++++++++++++------
>  1 file changed, 24 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 90144ac7aee8..f4ae035bed35 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -496,7 +496,8 @@ static void axienet_setoptions(struct net_device *ndev,
> u32 options)
>  
>  static int __axienet_device_reset(struct axienet_local *lp)
>  {
> -	u32 timeout;
> +	u32 value;
> +	int ret;
>  
>  	/* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
>  	 * process of Axi DMA takes a while to complete as all pending
> @@ -506,15 +507,23 @@ static int __axienet_device_reset(struct axienet_local
> *lp)
>  	 * they both reset the entire DMA core, so only one needs to be used.
>  	 */
>  	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
> -	timeout = DELAY_OF_ONE_MILLISEC;
> -	while (axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET) &
> -				XAXIDMA_CR_RESET_MASK) {
> -		udelay(1);
> -		if (--timeout == 0) {
> -			netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
> -				   __func__);
> -			return -ETIMEDOUT;
> -		}
> +	ret = read_poll_timeout(axienet_dma_in32, value,
> +				!(value & XAXIDMA_CR_RESET_MASK),
> +				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
> +				XAXIDMA_TX_CR_OFFSET);
> +	if (ret) {
> +		dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__);
> +		return ret;
> +	}
> +
> +	/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has
> finished */
> +	ret = read_poll_timeout(axienet_ior, value,
> +				value & XAE_INT_PHYRSTCMPLT_MASK,
> +				DELAY_OF_ONE_MILLISEC, 50000, false, lp,
> +				XAE_IS_OFFSET);
> +	if (ret) {
> +		dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n",
> __func__);
> +		return ret;
>  	}
>  
>  	return 0;
> @@ -2046,6 +2055,11 @@ static int axienet_probe(struct platform_device *pdev)
>  	lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
>  	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
>  
> +	/* Reset core now that clocks are enabled, prior to accessing MDIO */
> +	ret = __axienet_device_reset(lp);
> +	if (ret)
> +		goto cleanup_clk;
> +
>  	lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
>  	if (lp->phy_node) {
>  		ret = axienet_mdio_setup(lp);

Re: [PATCH net 1/7] net: axienet: Reset core before accessing MAC and wait for core ready

[Jakub Kicinski]

On Wed, 12 Jan 2022 00:30:33 +0000 Robert Hancock wrote:
> On Tue, 2022-01-11 at 15:13 -0600, Robert Hancock wrote:
> > In some cases where the Xilinx Ethernet core was used in 1000Base-X or
> > SGMII modes, which use the internal PCS/PMA PHY, and the MGT
> > transceiver clock source for the PCS was not running at the time the
> > FPGA logic was loaded, the core would come up in a state where the
> > PCS could not be found on the MDIO bus. To fix this, the Ethernet core
> > (including the PCS) should be reset after enabling the clocks, prior to
> > attempting to access the PCS using of_mdio_find_device.
> > 
> > Also, when resetting the device, wait for the PhyRstCmplt bit to be set
> > in the interrupt status register before continuing initialization, to
> > ensure that the core is actually ready. The MgtRdy bit could also be
> > waited for, but unfortunately when using 7-series devices, the bit does
> > not appear to work as documented (it seems to behave as some sort of
> > link state indication and not just an indication the transceiver is
> > ready) so it can't really be relied on.

Shouldn't these be two separate fixes?

Re: [PATCH net 6/7] net: axienet: fix for TX busy handling

[Jakub Kicinski]

On Tue, 11 Jan 2022 15:13:57 -0600 Robert Hancock wrote:
> We should be avoiding returning NETDEV_TX_BUSY from ndo_start_xmit in
> normal cases. Move the main check for a full TX ring to the end of the
> function so that we stop the queue after the last available space is used
> up, and only wake up the queue if enough space is available for a full
> maximally fragmented packet. Print a warning if there is insufficient
> space at the start of start_xmit, since this should no longer happen.
> 
> Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Feels a little more like an optimization than strictly a fix.
Can we apply this and the following patch to net-next in two
week's time? It's not too much of a stretch to take it in now
if it's a bit convenience but I don't think the Fixes tags should 
stay.

> -		netif_wake_queue(ndev);
> +		netdev_warn(ndev, "TX ring unexpectedly full\n");

Probably wise to make this netdev_warn_once() or at least rate limit it.

> +		return NETDEV_TX_BUSY;
>  	}
>  
>  	if (skb->ip_summed == CHECKSUM_PARTIAL) {

Re: [PATCH net 6/7] net: axienet: fix for TX busy handling

[Robert Hancock]

On Tue, 2022-01-11 at 19:49 -0800, Jakub Kicinski wrote:
> On Tue, 11 Jan 2022 15:13:57 -0600 Robert Hancock wrote:
> > We should be avoiding returning NETDEV_TX_BUSY from ndo_start_xmit in
> > normal cases. Move the main check for a full TX ring to the end of the
> > function so that we stop the queue after the last available space is used
> > up, and only wake up the queue if enough space is available for a full
> > maximally fragmented packet. Print a warning if there is insufficient
> > space at the start of start_xmit, since this should no longer happen.
> > 
> > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI
> > Ethernet driver")
> > Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> 
> Feels a little more like an optimization than strictly a fix.
> Can we apply this and the following patch to net-next in two
> week's time? It's not too much of a stretch to take it in now
> if it's a bit convenience but I don't think the Fixes tags should 
> stay.

Well it's a fix in the sense that it complies with what
Documentation/networking/driver.rst says drivers should do - I'm not too
familiar with the consequences of not doing that are, I guess mostly
performance from having to requeue the packet?

From that standpoint, I guess the concern with breaking those two patches out
is that the previous patches can introduce a bit of a performance hit (by
actually caring about the state of the TX ring instead of trampling over it in
some cases) and so without the last two you might end up with some performance 
regression. So I'd probably prefer to keep them together with the rest of the
patch set.

> 
> > -		netif_wake_queue(ndev);
> > +		netdev_warn(ndev, "TX ring unexpectedly full\n");
> 
> Probably wise to make this netdev_warn_once() or at least rate limit it.

Might want it more than once (so you can tell if it is a one-off or happening
more often), but I can put in a rate limit..

> 
> > +		return NETDEV_TX_BUSY;
> >  	}
> >  
> >  	if (skb->ip_summed == CHECKSUM_PARTIAL) {

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com

Re: [PATCH net 1/7] net: axienet: Reset core before accessing MAC and wait for core ready

[Robert Hancock]

On Tue, 2022-01-11 at 19:24 -0800, Jakub Kicinski wrote:
> On Wed, 12 Jan 2022 00:30:33 +0000 Robert Hancock wrote:
> > On Tue, 2022-01-11 at 15:13 -0600, Robert Hancock wrote:
> > > In some cases where the Xilinx Ethernet core was used in 1000Base-X or
> > > SGMII modes, which use the internal PCS/PMA PHY, and the MGT
> > > transceiver clock source for the PCS was not running at the time the
> > > FPGA logic was loaded, the core would come up in a state where the
> > > PCS could not be found on the MDIO bus. To fix this, the Ethernet core
> > > (including the PCS) should be reset after enabling the clocks, prior to
> > > attempting to access the PCS using of_mdio_find_device.
> > > 
> > > Also, when resetting the device, wait for the PhyRstCmplt bit to be set
> > > in the interrupt status register before continuing initialization, to
> > > ensure that the core is actually ready. The MgtRdy bit could also be
> > > waited for, but unfortunately when using 7-series devices, the bit does
> > > not appear to work as documented (it seems to behave as some sort of
> > > link state indication and not just an indication the transceiver is
> > > ready) so it can't really be relied on.
> 
> Shouldn't these be two separate fixes?

Yeah, this could likely be broken up into 2 patches (or possibly 3).

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com

Re: [PATCH net 6/7] net: axienet: fix for TX busy handling

[Jakub Kicinski]

On Wed, 12 Jan 2022 16:45:18 +0000 Robert Hancock wrote:
> On Tue, 2022-01-11 at 19:49 -0800, Jakub Kicinski wrote:
> > On Tue, 11 Jan 2022 15:13:57 -0600 Robert Hancock wrote:  
> > > We should be avoiding returning NETDEV_TX_BUSY from ndo_start_xmit in
> > > normal cases. Move the main check for a full TX ring to the end of the
> > > function so that we stop the queue after the last available space is used
> > > up, and only wake up the queue if enough space is available for a full
> > > maximally fragmented packet. Print a warning if there is insufficient
> > > space at the start of start_xmit, since this should no longer happen.
> > > 
> > > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI
> > > Ethernet driver")
> > > Signed-off-by: Robert Hancock <robert.hancock@calian.com>  
> > 
> > Feels a little more like an optimization than strictly a fix.
> > Can we apply this and the following patch to net-next in two
> > week's time? It's not too much of a stretch to take it in now
> > if it's a bit convenience but I don't think the Fixes tags should 
> > stay.  
> 
> Well it's a fix in the sense that it complies with what
> Documentation/networking/driver.rst says drivers should do - I'm not too
> familiar with the consequences of not doing that are, I guess mostly
> performance from having to requeue the packet?

Yes, it's just the re-queuing overhead AFAIU.

> From that standpoint, I guess the concern with breaking those two patches out
> is that the previous patches can introduce a bit of a performance hit (by
> actually caring about the state of the TX ring instead of trampling over it in
> some cases) and so without the last two you might end up with some performance 
> regression. So I'd probably prefer to keep them together with the rest of the
> patch set.

Alright, if you have any numbers on this it'd be great to include them
in the commit message.

Re: [PATCH net 6/7] net: axienet: fix for TX busy handling

[Robert Hancock]

On Wed, 2022-01-12 at 09:01 -0800, Jakub Kicinski wrote:
> On Wed, 12 Jan 2022 16:45:18 +0000 Robert Hancock wrote:
> > On Tue, 2022-01-11 at 19:49 -0800, Jakub Kicinski wrote:
> > > On Tue, 11 Jan 2022 15:13:57 -0600 Robert Hancock wrote:  
> > > > We should be avoiding returning NETDEV_TX_BUSY from ndo_start_xmit in
> > > > normal cases. Move the main check for a full TX ring to the end of the
> > > > function so that we stop the queue after the last available space is
> > > > used
> > > > up, and only wake up the queue if enough space is available for a full
> > > > maximally fragmented packet. Print a warning if there is insufficient
> > > > space at the start of start_xmit, since this should no longer happen.
> > > > 
> > > > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI
> > > > Ethernet driver")
> > > > Signed-off-by: Robert Hancock <robert.hancock@calian.com>  
> > > 
> > > Feels a little more like an optimization than strictly a fix.
> > > Can we apply this and the following patch to net-next in two
> > > week's time? It's not too much of a stretch to take it in now
> > > if it's a bit convenience but I don't think the Fixes tags should 
> > > stay.  
> > 
> > Well it's a fix in the sense that it complies with what
> > Documentation/networking/driver.rst says drivers should do - I'm not too
> > familiar with the consequences of not doing that are, I guess mostly
> > performance from having to requeue the packet?
> 
> Yes, it's just the re-queuing overhead AFAIU.
> 
> > From that standpoint, I guess the concern with breaking those two patches
> > out
> > is that the previous patches can introduce a bit of a performance hit (by
> > actually caring about the state of the TX ring instead of trampling over it
> > in
> > some cases) and so without the last two you might end up with some
> > performance 
> > regression. So I'd probably prefer to keep them together with the rest of
> > the
> > patch set.
> 
> Alright, if you have any numbers on this it'd be great to include them
> in the commit message.

I don't have any numbers from that individual change unfortunately, just from
both of the two together (the second change's commit message mentions the TX
rate went from 600 Mbps up to near 1 Gbps on a 1 Gbps link). But I'll add some
some more rationale to the commit message on this one.

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com