* [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Cover from Samuel Ortiz from (part 1) [1]:
This patchset allows for building and running ARM targets with TCG
disabled. [...]
The rationale behind this work comes from the NEMU project where we're
trying to only support x86 and ARM 64-bit architectures, without
including the TCG code base. We can only do so if we can build and run
ARM binaries with TCG disabled.
v3 almost 18 months later:
- Rebased
- Addressed Thomas review comments
- Added Travis-CI job to keep building --disable-tcg on ARM
v2 [2]:
- Addressed review comments from Richard and Thomas from v1 [3]
Regards,
Phil.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
[2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
[3]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
Based-on: <20200316120049.11225-1-philmd@redhat.com>
"accel: Allow targets to use Kconfig, disable semihosting by default"
https://lists.gnu.org/archive/html/qemu-devel/2020-03/msg04653.html
Philippe Mathieu-Daudé (15):
target/arm: Rename KVM set_feature() as kvm_set_feature()
target/arm: Restrict DC-CVAP instruction to TCG accel
target/arm: Restric the Address Translate operations to TCG accel
target/arm: Restrict Virtualization Host Extensions instructions to
TCG
target/arm: Move Makefile variable restricted to CONFIG_TCG
target/arm: Add semihosting stub to allow building without TCG
target/arm: Move ARM_V7M Kconfig from hw/ to target/
target/arm: Restrict ARMv4 cpus to TCG accel
target/arm: Restrict ARMv5 cpus to TCG accel
target/arm: Restrict ARMv6 cpus to TCG accel
target/arm: Restrict ARMv7 R-profile cpus to TCG accel
target/arm: Restrict ARMv7 M-profile cpus to TCG accel
hw/arm: Automatically select the 'virt' machine on KVM
hw/arm: Do not build to 'virt' machine on Xen
.travis.yml: Add a KVM-only Aarch64 job
Samuel Ortiz (1):
target/arm: Do not build TCG objects when TCG is off
Thomas Huth (3):
target/arm: Make set_feature() available for other files
target/arm: Make cpu_register() available for other files
target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
default-configs/aarch64-softmmu.mak | 1 -
default-configs/arm-softmmu.mak | 30 --
target/arm/cpu-qom.h | 9 +-
target/arm/cpu.h | 7 +
target/arm/internals.h | 10 +
target/arm/arm-semi-stub.c | 13 +
target/arm/cpu.c | 651 +---------------------------
target/arm/cpu64.c | 19 +-
target/arm/cpu_v4.c | 65 +++
target/arm/cpu_v5.c | 266 ++++++++++++
target/arm/cpu_v6.c | 171 ++++++++
target/arm/cpu_v7m.c | 207 +++++++++
target/arm/cpu_v7r.c | 83 ++++
target/arm/helper.c | 54 +--
target/arm/kvm32.c | 10 +-
target/arm/kvm64.c | 16 +-
target/arm/m_helper-stub.c | 59 +++
.travis.yml | 32 ++
hw/arm/Kconfig | 17 +-
target/Kconfig | 2 +-
target/arm/Kconfig | 19 +
target/arm/Makefile.objs | 17 +-
22 files changed, 1016 insertions(+), 742 deletions(-)
create mode 100644 target/arm/arm-semi-stub.c
create mode 100644 target/arm/cpu_v4.c
create mode 100644 target/arm/cpu_v5.c
create mode 100644 target/arm/cpu_v6.c
create mode 100644 target/arm/cpu_v7m.c
create mode 100644 target/arm/cpu_v7r.c
create mode 100644 target/arm/m_helper-stub.c
create mode 100644 target/arm/Kconfig
--
2.21.1
^ permalink raw reply [flat|nested] 122+ messages in thread
* [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Cover from Samuel Ortiz from (part 1) [1]:
This patchset allows for building and running ARM targets with TCG
disabled. [...]
The rationale behind this work comes from the NEMU project where we're
trying to only support x86 and ARM 64-bit architectures, without
including the TCG code base. We can only do so if we can build and run
ARM binaries with TCG disabled.
v3 almost 18 months later:
- Rebased
- Addressed Thomas review comments
- Added Travis-CI job to keep building --disable-tcg on ARM
v2 [2]:
- Addressed review comments from Richard and Thomas from v1 [3]
Regards,
Phil.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
[2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
[3]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
Based-on: <20200316120049.11225-1-philmd@redhat.com>
"accel: Allow targets to use Kconfig, disable semihosting by default"
https://lists.gnu.org/archive/html/qemu-devel/2020-03/msg04653.html
Philippe Mathieu-Daudé (15):
target/arm: Rename KVM set_feature() as kvm_set_feature()
target/arm: Restrict DC-CVAP instruction to TCG accel
target/arm: Restric the Address Translate operations to TCG accel
target/arm: Restrict Virtualization Host Extensions instructions to
TCG
target/arm: Move Makefile variable restricted to CONFIG_TCG
target/arm: Add semihosting stub to allow building without TCG
target/arm: Move ARM_V7M Kconfig from hw/ to target/
target/arm: Restrict ARMv4 cpus to TCG accel
target/arm: Restrict ARMv5 cpus to TCG accel
target/arm: Restrict ARMv6 cpus to TCG accel
target/arm: Restrict ARMv7 R-profile cpus to TCG accel
target/arm: Restrict ARMv7 M-profile cpus to TCG accel
hw/arm: Automatically select the 'virt' machine on KVM
hw/arm: Do not build to 'virt' machine on Xen
.travis.yml: Add a KVM-only Aarch64 job
Samuel Ortiz (1):
target/arm: Do not build TCG objects when TCG is off
Thomas Huth (3):
target/arm: Make set_feature() available for other files
target/arm: Make cpu_register() available for other files
target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
default-configs/aarch64-softmmu.mak | 1 -
default-configs/arm-softmmu.mak | 30 --
target/arm/cpu-qom.h | 9 +-
target/arm/cpu.h | 7 +
target/arm/internals.h | 10 +
target/arm/arm-semi-stub.c | 13 +
target/arm/cpu.c | 651 +---------------------------
target/arm/cpu64.c | 19 +-
target/arm/cpu_v4.c | 65 +++
target/arm/cpu_v5.c | 266 ++++++++++++
target/arm/cpu_v6.c | 171 ++++++++
target/arm/cpu_v7m.c | 207 +++++++++
target/arm/cpu_v7r.c | 83 ++++
target/arm/helper.c | 54 +--
target/arm/kvm32.c | 10 +-
target/arm/kvm64.c | 16 +-
target/arm/m_helper-stub.c | 59 +++
.travis.yml | 32 ++
hw/arm/Kconfig | 17 +-
target/Kconfig | 2 +-
target/arm/Kconfig | 19 +
target/arm/Makefile.objs | 17 +-
22 files changed, 1016 insertions(+), 742 deletions(-)
create mode 100644 target/arm/arm-semi-stub.c
create mode 100644 target/arm/cpu_v4.c
create mode 100644 target/arm/cpu_v5.c
create mode 100644 target/arm/cpu_v6.c
create mode 100644 target/arm/cpu_v7m.c
create mode 100644 target/arm/cpu_v7r.c
create mode 100644 target/arm/m_helper-stub.c
create mode 100644 target/arm/Kconfig
--
2.21.1
^ permalink raw reply [flat|nested] 122+ messages in thread
* [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/kvm32.c | 10 +++++-----
target/arm/kvm64.c | 16 ++++++++--------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index f271181ab8..0ab28b473a 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -22,7 +22,7 @@
#include "internals.h"
#include "qemu/log.h"
-static inline void set_feature(uint64_t *features, int feature)
+static inline void kvm_set_feature(uint64_t *features, int feature)
{
*features |= 1ULL << feature;
}
@@ -146,14 +146,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* timers; this in turn implies most of the other feature
* bits, but a few must be tested.
*/
- set_feature(&features, ARM_FEATURE_V7VE);
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
+ kvm_set_feature(&features, ARM_FEATURE_V7VE);
+ kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
if (extract32(id_pfr0, 12, 4) == 1) {
- set_feature(&features, ARM_FEATURE_THUMB2EE);
+ kvm_set_feature(&features, ARM_FEATURE_THUMB2EE);
}
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
- set_feature(&features, ARM_FEATURE_NEON);
+ kvm_set_feature(&features, ARM_FEATURE_NEON);
}
ahcf->features = features;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index be5b31c2b0..ad33e048e4 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -447,12 +447,12 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
}
}
-static inline void set_feature(uint64_t *features, int feature)
+static inline void kvm_set_feature(uint64_t *features, int feature)
{
*features |= 1ULL << feature;
}
-static inline void unset_feature(uint64_t *features, int feature)
+static inline void kvm_unset_feature(uint64_t *features, int feature)
{
*features &= ~(1ULL << feature);
}
@@ -648,11 +648,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* with VFPv4+Neon; this in turn implies most of the other
* feature bits.
*/
- set_feature(&features, ARM_FEATURE_V8);
- set_feature(&features, ARM_FEATURE_NEON);
- set_feature(&features, ARM_FEATURE_AARCH64);
- set_feature(&features, ARM_FEATURE_PMU);
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
+ kvm_set_feature(&features, ARM_FEATURE_V8);
+ kvm_set_feature(&features, ARM_FEATURE_NEON);
+ kvm_set_feature(&features, ARM_FEATURE_AARCH64);
+ kvm_set_feature(&features, ARM_FEATURE_PMU);
+ kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
ahcf->features = features;
@@ -802,7 +802,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (cpu->has_pmu) {
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
} else {
- unset_feature(&env->features, ARM_FEATURE_PMU);
+ kvm_unset_feature(&env->features, ARM_FEATURE_PMU);
}
if (cpu_isar_feature(aa64_sve, cpu)) {
assert(kvm_arm_sve_supported(cs));
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/kvm32.c | 10 +++++-----
target/arm/kvm64.c | 16 ++++++++--------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index f271181ab8..0ab28b473a 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -22,7 +22,7 @@
#include "internals.h"
#include "qemu/log.h"
-static inline void set_feature(uint64_t *features, int feature)
+static inline void kvm_set_feature(uint64_t *features, int feature)
{
*features |= 1ULL << feature;
}
@@ -146,14 +146,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* timers; this in turn implies most of the other feature
* bits, but a few must be tested.
*/
- set_feature(&features, ARM_FEATURE_V7VE);
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
+ kvm_set_feature(&features, ARM_FEATURE_V7VE);
+ kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
if (extract32(id_pfr0, 12, 4) == 1) {
- set_feature(&features, ARM_FEATURE_THUMB2EE);
+ kvm_set_feature(&features, ARM_FEATURE_THUMB2EE);
}
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
- set_feature(&features, ARM_FEATURE_NEON);
+ kvm_set_feature(&features, ARM_FEATURE_NEON);
}
ahcf->features = features;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index be5b31c2b0..ad33e048e4 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -447,12 +447,12 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
}
}
-static inline void set_feature(uint64_t *features, int feature)
+static inline void kvm_set_feature(uint64_t *features, int feature)
{
*features |= 1ULL << feature;
}
-static inline void unset_feature(uint64_t *features, int feature)
+static inline void kvm_unset_feature(uint64_t *features, int feature)
{
*features &= ~(1ULL << feature);
}
@@ -648,11 +648,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* with VFPv4+Neon; this in turn implies most of the other
* feature bits.
*/
- set_feature(&features, ARM_FEATURE_V8);
- set_feature(&features, ARM_FEATURE_NEON);
- set_feature(&features, ARM_FEATURE_AARCH64);
- set_feature(&features, ARM_FEATURE_PMU);
- set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
+ kvm_set_feature(&features, ARM_FEATURE_V8);
+ kvm_set_feature(&features, ARM_FEATURE_NEON);
+ kvm_set_feature(&features, ARM_FEATURE_AARCH64);
+ kvm_set_feature(&features, ARM_FEATURE_PMU);
+ kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
ahcf->features = features;
@@ -802,7 +802,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (cpu->has_pmu) {
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
} else {
- unset_feature(&env->features, ARM_FEATURE_PMU);
+ kvm_unset_feature(&env->features, ARM_FEATURE_PMU);
}
if (cpu_isar_feature(aa64_sve, cpu)) {
assert(kvm_arm_sve_supported(cs));
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 02/19] target/arm: Make set_feature() available for other files
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson, Eric Auger
From: Thomas Huth <thuth@redhat.com>
Move the common set_feature() and unset_feature() functions
from cpu.c and cpu64.c to internals.h.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
[PMD: Split Thomas's patch in two: set_feature, cpu_register (later)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/internals.h | 10 ++++++++++
target/arm/cpu.c | 10 ----------
target/arm/cpu64.c | 11 +----------
3 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e633aff36e..7341848e1d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -27,6 +27,16 @@
#include "hw/registerfields.h"
+static inline void set_feature(CPUARMState *env, int feature)
+{
+ env->features |= 1ULL << feature;
+}
+
+static inline void unset_feature(CPUARMState *env, int feature)
+{
+ env->features &= ~(1ULL << feature);
+}
+
/* register banks for CPU modes */
#define BANK_USRSYS 0
#define BANK_SVC 1
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3623ecefbd..c074364542 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -723,16 +723,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
#endif
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1ULL << feature;
-}
-
-static inline void unset_feature(CPUARMState *env, int feature)
-{
- env->features &= ~(1ULL << feature);
-}
-
static int
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
{
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 62d36f9e8d..622082eae2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#include "internals.h"
#include "qemu/module.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
@@ -29,16 +30,6 @@
#include "kvm_arm.h"
#include "qapi/visitor.h"
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1ULL << feature;
-}
-
-static inline void unset_feature(CPUARMState *env, int feature)
-{
- env->features &= ~(1ULL << feature);
-}
-
#ifndef CONFIG_USER_ONLY
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 02/19] target/arm: Make set_feature() available for other files
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Eric Auger, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
Move the common set_feature() and unset_feature() functions
from cpu.c and cpu64.c to internals.h.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
[PMD: Split Thomas's patch in two: set_feature, cpu_register (later)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/internals.h | 10 ++++++++++
target/arm/cpu.c | 10 ----------
target/arm/cpu64.c | 11 +----------
3 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e633aff36e..7341848e1d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -27,6 +27,16 @@
#include "hw/registerfields.h"
+static inline void set_feature(CPUARMState *env, int feature)
+{
+ env->features |= 1ULL << feature;
+}
+
+static inline void unset_feature(CPUARMState *env, int feature)
+{
+ env->features &= ~(1ULL << feature);
+}
+
/* register banks for CPU modes */
#define BANK_USRSYS 0
#define BANK_SVC 1
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3623ecefbd..c074364542 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -723,16 +723,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
#endif
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1ULL << feature;
-}
-
-static inline void unset_feature(CPUARMState *env, int feature)
-{
- env->features &= ~(1ULL << feature);
-}
-
static int
print_insn_thumb1(bfd_vma pc, disassemble_info *info)
{
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 62d36f9e8d..622082eae2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#include "internals.h"
#include "qemu/module.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
@@ -29,16 +30,6 @@
#include "kvm_arm.h"
#include "qapi/visitor.h"
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1ULL << feature;
-}
-
-static inline void unset_feature(CPUARMState *env, int feature)
-{
- env->features &= ~(1ULL << feature);
-}
-
#ifndef CONFIG_USER_ONLY
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Under KVM the 'Data or unified Cache line Clean by VA to PoP'
instruction will trap.
Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins")
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b61ee73d18..924deffd65 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = {
REGINFO_SENTINEL
};
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value)
{
@@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = {
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
REGINFO_SENTINEL
};
-#endif /*CONFIG_USER_ONLY*/
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
-#endif
+#endif /* TARGET_AARCH64 */
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
@@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_rndr, cpu)) {
define_arm_cp_regs(cpu, rndr_reginfo);
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* Data Cache clean instructions up to PoP */
if (cpu_isar_feature(aa64_dcpop, cpu)) {
define_one_arm_cp_reg(cpu, dcpop_reg);
@@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, dcpodp_reg);
}
}
-#endif /*CONFIG_USER_ONLY*/
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* TARGET_AARCH64 */
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Under KVM the 'Data or unified Cache line Clean by VA to PoP'
instruction will trap.
Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins")
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b61ee73d18..924deffd65 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = {
REGINFO_SENTINEL
};
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value)
{
@@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = {
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
REGINFO_SENTINEL
};
-#endif /*CONFIG_USER_ONLY*/
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
-#endif
+#endif /* TARGET_AARCH64 */
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
@@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_rndr, cpu)) {
define_arm_cp_regs(cpu, rndr_reginfo);
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* Data Cache clean instructions up to PoP */
if (cpu_isar_feature(aa64_dcpop, cpu)) {
define_one_arm_cp_reg(cpu, dcpop_reg);
@@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, dcpodp_reg);
}
}
-#endif /*CONFIG_USER_ONLY*/
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* TARGET_AARCH64 */
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Under KVM the ATS instruction will trap.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 924deffd65..a5280c091b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* get_phys_addr() isn't present for user-mode-only targets */
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
}
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
static const ARMCPRegInfo vapa_cp_reginfo[] = {
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
@@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write },
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
@@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
-#ifndef CONFIG_USER_ONLY
+
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* 64 bit address translation operations */
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
@@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
.writefn = par_write },
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+
/* TLB invalidate last level of translation table walk */
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
@@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae2is_write },
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* Unlike the other EL2-related AT operations, these must
* UNDEF from EL3 if EL2 is not implemented, which is why we
* define them here rather than with the rest of the AT ops.
@@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = {
REGINFO_SENTINEL
};
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static const ARMCPRegInfo ats1e1_reginfo[] = {
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
@@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_pan, cpu)) {
define_one_arm_cp_reg(cpu, &pan_reginfo);
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
if (cpu_isar_feature(aa64_ats1e1, cpu)) {
define_arm_cp_regs(cpu, ats1e1_reginfo);
}
if (cpu_isar_feature(aa32_ats1e1, cpu)) {
define_arm_cp_regs(cpu, ats1cp_reginfo);
}
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
if (cpu_isar_feature(aa64_uao, cpu)) {
define_one_arm_cp_reg(cpu, &uao_reginfo);
}
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Under KVM the ATS instruction will trap.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 924deffd65..a5280c091b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* get_phys_addr() isn't present for user-mode-only targets */
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
}
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
static const ARMCPRegInfo vapa_cp_reginfo[] = {
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
@@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
offsetoflow32(CPUARMState, cp15.par_ns) },
.writefn = par_write },
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* This underdecoding is safe because the reginfo is NO_RAW. */
{ .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_W, .accessfn = ats_access,
@@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
-#ifndef CONFIG_USER_ONLY
+
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* 64 bit address translation operations */
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
@@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
.writefn = par_write },
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+
/* TLB invalidate last level of translation table walk */
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
@@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae2is_write },
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* Unlike the other EL2-related AT operations, these must
* UNDEF from EL3 if EL2 is not implemented, which is why we
* define them here rather than with the rest of the AT ops.
@@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = {
REGINFO_SENTINEL
};
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static const ARMCPRegInfo ats1e1_reginfo[] = {
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
@@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_pan, cpu)) {
define_one_arm_cp_reg(cpu, &pan_reginfo);
}
-#ifndef CONFIG_USER_ONLY
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
if (cpu_isar_feature(aa64_ats1e1, cpu)) {
define_arm_cp_regs(cpu, ats1e1_reginfo);
}
if (cpu_isar_feature(aa32_ats1e1, cpu)) {
define_arm_cp_regs(cpu, ats1cp_reginfo);
}
-#endif
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
if (cpu_isar_feature(aa64_uao, cpu)) {
define_one_arm_cp_reg(cpu, &uao_reginfo);
}
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Under KVM the ARMv8.1-VHE instruction will trap.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a5280c091b..ce6778283d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_VIRT, value);
}
-static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- trace_arm_gt_cntvoff_write(value);
- raw_write(env, ri, value);
- gt_recalc_timer(cpu, GTIMER_VIRT);
-}
-
static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
const ARMCPRegInfo *ri)
{
@@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_ctl_write(env, ri, timeridx, value);
}
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ trace_arm_gt_cntvoff_write(value);
+ raw_write(env, ri, value);
+ gt_recalc_timer(cpu, GTIMER_VIRT);
+}
+
static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_HYP);
@@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
gt_ctl_write(env, ri, GTIMER_HYP, value);
}
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Under KVM the ARMv8.1-VHE instruction will trap.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a5280c091b..ce6778283d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_VIRT, value);
}
-static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- trace_arm_gt_cntvoff_write(value);
- raw_write(env, ri, value);
- gt_recalc_timer(cpu, GTIMER_VIRT);
-}
-
static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
const ARMCPRegInfo *ri)
{
@@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_ctl_write(env, ri, timeridx, value);
}
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ trace_arm_gt_cntvoff_write(value);
+ raw_write(env, ri, value);
+ gt_recalc_timer(cpu, GTIMER_VIRT);
+}
+
static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_HYP);
@@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
gt_ctl_write(env, ri, GTIMER_HYP, value);
}
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 06/19] target/arm: Move Makefile variable restricted to CONFIG_TCG
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Simple code movement which simplifies next commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/Makefile.objs | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index cf26c16f5f..0c6f8c248d 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -1,4 +1,3 @@
-obj-$(CONFIG_TCG) += arm-semi.o
obj-y += helper.o vfp_helper.o
obj-y += cpu.o gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
@@ -56,6 +55,12 @@ target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
target/arm/translate.o: target/arm/decode-t32.inc.c
target/arm/translate.o: target/arm/decode-t16.inc.c
+ifeq ($(CONFIG_TCG),y)
+
+obj-y += arm-semi.o
+
+endif # CONFIG_TCG
+
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 06/19] target/arm: Move Makefile variable restricted to CONFIG_TCG
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Simple code movement which simplifies next commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/Makefile.objs | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index cf26c16f5f..0c6f8c248d 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -1,4 +1,3 @@
-obj-$(CONFIG_TCG) += arm-semi.o
obj-y += helper.o vfp_helper.o
obj-y += cpu.o gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
@@ -56,6 +55,12 @@ target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
target/arm/translate.o: target/arm/decode-t32.inc.c
target/arm/translate.o: target/arm/decode-t16.inc.c
+ifeq ($(CONFIG_TCG),y)
+
+obj-y += arm-semi.o
+
+endif # CONFIG_TCG
+
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 07/19] target/arm: Make cpu_register() available for other files
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson, Eric Auger
From: Thomas Huth <thuth@redhat.com>
Make cpu_register() (renamed to arm_cpu_register()) available
from internals.h so we can register CPUs also from other files
in the future.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
[PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/cpu-qom.h | 9 ++++++++-
target/arm/cpu.c | 10 ++--------
target/arm/cpu64.c | 8 +-------
3 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 3a9d31ea9d..29c5e2f2c9 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -35,7 +35,14 @@ struct arm_boot_info;
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
-typedef struct ARMCPUInfo ARMCPUInfo;
+typedef struct ARMCPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+ void (*class_init)(ObjectClass *oc, void *data);
+} ARMCPUInfo;
+
+void arm_cpu_register(const ARMCPUInfo *info);
+void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c074364542..d2813eb81a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2698,12 +2698,6 @@ static void arm_max_initfn(Object *obj)
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
-struct ARMCPUInfo {
- const char *name;
- void (*initfn)(Object *obj);
- void (*class_init)(ObjectClass *oc, void *data);
-};
-
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
{ .name = "arm926", .initfn = arm926_initfn },
@@ -2869,7 +2863,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
}
-static void cpu_register(const ARMCPUInfo *info)
+void arm_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
@@ -2910,7 +2904,7 @@ static void arm_cpu_register_types(void)
type_register_static(&idau_interface_type_info);
while (info->name) {
- cpu_register(info);
+ arm_cpu_register(info);
info++;
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 622082eae2..e89388378b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj)
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
}
-struct ARMCPUInfo {
- const char *name;
- void (*initfn)(Object *obj);
- void (*class_init)(ObjectClass *oc, void *data);
-};
-
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
@@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
}
-static void aarch64_cpu_register(const ARMCPUInfo *info)
+void aarch64_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 07/19] target/arm: Make cpu_register() available for other files
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Eric Auger, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
Make cpu_register() (renamed to arm_cpu_register()) available
from internals.h so we can register CPUs also from other files
in the future.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-ID: <20190921150420.30743-2-thuth@redhat.com>
[PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/cpu-qom.h | 9 ++++++++-
target/arm/cpu.c | 10 ++--------
target/arm/cpu64.c | 8 +-------
3 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 3a9d31ea9d..29c5e2f2c9 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -35,7 +35,14 @@ struct arm_boot_info;
#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
-typedef struct ARMCPUInfo ARMCPUInfo;
+typedef struct ARMCPUInfo {
+ const char *name;
+ void (*initfn)(Object *obj);
+ void (*class_init)(ObjectClass *oc, void *data);
+} ARMCPUInfo;
+
+void arm_cpu_register(const ARMCPUInfo *info);
+void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c074364542..d2813eb81a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2698,12 +2698,6 @@ static void arm_max_initfn(Object *obj)
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
-struct ARMCPUInfo {
- const char *name;
- void (*initfn)(Object *obj);
- void (*class_init)(ObjectClass *oc, void *data);
-};
-
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
{ .name = "arm926", .initfn = arm926_initfn },
@@ -2869,7 +2863,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
}
-static void cpu_register(const ARMCPUInfo *info)
+void arm_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
@@ -2910,7 +2904,7 @@ static void arm_cpu_register_types(void)
type_register_static(&idau_interface_type_info);
while (info->name) {
- cpu_register(info);
+ arm_cpu_register(info);
info++;
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 622082eae2..e89388378b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj)
cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
}
-struct ARMCPUInfo {
- const char *name;
- void (*initfn)(Object *obj);
- void (*class_init)(ObjectClass *oc, void *data);
-};
-
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
@@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
}
-static void aarch64_cpu_register(const ARMCPUInfo *info)
+void aarch64_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Semihosting requires TCG. When configured with --disable-tcg, the
build fails because the 'do_arm_semihosting' is missing. Instead
of adding more few more #ifdeffery to the helper code, add a stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/arm-semi-stub.c | 13 +++++++++++++
target/arm/Makefile.objs | 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
create mode 100644 target/arm/arm-semi-stub.c
diff --git a/target/arm/arm-semi-stub.c b/target/arm/arm-semi-stub.c
new file mode 100644
index 0000000000..47d042f942
--- /dev/null
+++ b/target/arm/arm-semi-stub.c
@@ -0,0 +1,13 @@
+/*
+ * Arm "Angel" semihosting syscalls stubs
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/semihosting/semihost.h"
+
+target_ulong do_arm_semihosting(CPUARMState *env)
+{
+ abort();
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 0c6f8c248d..fa278bb4c1 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -57,7 +57,8 @@ target/arm/translate.o: target/arm/decode-t16.inc.c
ifeq ($(CONFIG_TCG),y)
-obj-y += arm-semi.o
+obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
+obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
endif # CONFIG_TCG
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Semihosting requires TCG. When configured with --disable-tcg, the
build fails because the 'do_arm_semihosting' is missing. Instead
of adding more few more #ifdeffery to the helper code, add a stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/arm-semi-stub.c | 13 +++++++++++++
target/arm/Makefile.objs | 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
create mode 100644 target/arm/arm-semi-stub.c
diff --git a/target/arm/arm-semi-stub.c b/target/arm/arm-semi-stub.c
new file mode 100644
index 0000000000..47d042f942
--- /dev/null
+++ b/target/arm/arm-semi-stub.c
@@ -0,0 +1,13 @@
+/*
+ * Arm "Angel" semihosting syscalls stubs
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/semihosting/semihost.h"
+
+target_ulong do_arm_semihosting(CPUARMState *env)
+{
+ abort();
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 0c6f8c248d..fa278bb4c1 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -57,7 +57,8 @@ target/arm/translate.o: target/arm/decode-t16.inc.c
ifeq ($(CONFIG_TCG),y)
-obj-y += arm-semi.o
+obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
+obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
endif # CONFIG_TCG
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
ARM_V7M is a concept tied to the architecture. Move it to the
target/arm/ directory to keep the hardware/architecture separation
clearer.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/arm/Kconfig | 3 ---
target/Kconfig | 2 +-
target/arm/Kconfig | 2 ++
3 files changed, 3 insertions(+), 4 deletions(-)
create mode 100644 target/arm/Kconfig
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e5a876c8d1..e3d7e7694a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -285,9 +285,6 @@ config ZYNQ
select XILINX_SPIPS
select ZYNQ_DEVCFG
-config ARM_V7M
- bool
-
config ALLWINNER_A10
bool
select AHCI
diff --git a/target/Kconfig b/target/Kconfig
index 8b13789179..130d0c7a85 100644
--- a/target/Kconfig
+++ b/target/Kconfig
@@ -1 +1 @@
-
+source arm/Kconfig
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
new file mode 100644
index 0000000000..e68c71a6ff
--- /dev/null
+++ b/target/arm/Kconfig
@@ -0,0 +1,2 @@
+config ARM_V7M
+ bool
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
ARM_V7M is a concept tied to the architecture. Move it to the
target/arm/ directory to keep the hardware/architecture separation
clearer.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/arm/Kconfig | 3 ---
target/Kconfig | 2 +-
target/arm/Kconfig | 2 ++
3 files changed, 3 insertions(+), 4 deletions(-)
create mode 100644 target/arm/Kconfig
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e5a876c8d1..e3d7e7694a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -285,9 +285,6 @@ config ZYNQ
select XILINX_SPIPS
select ZYNQ_DEVCFG
-config ARM_V7M
- bool
-
config ALLWINNER_A10
bool
select AHCI
diff --git a/target/Kconfig b/target/Kconfig
index 8b13789179..130d0c7a85 100644
--- a/target/Kconfig
+++ b/target/Kconfig
@@ -1 +1 @@
-
+source arm/Kconfig
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
new file mode 100644
index 0000000000..e68c71a6ff
--- /dev/null
+++ b/target/arm/Kconfig
@@ -0,0 +1,2 @@
+config ARM_V7M
+ bool
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 2 -
target/arm/cpu.c | 33 -----------------
target/arm/cpu_v4.c | 65 +++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 2 +
target/arm/Kconfig | 4 ++
target/arm/Makefile.objs | 2 +
6 files changed, 73 insertions(+), 35 deletions(-)
create mode 100644 target/arm/cpu_v4.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 8b89d8c4c0..0652396296 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d2813eb81a..b08b6933be 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2459,36 +2459,6 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
-static void ti925t_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V4T);
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
- cpu->midr = ARM_CPUID_TI925T;
- cpu->ctr = 0x5109149;
- cpu->reset_sctlr = 0x00000070;
-}
-
-static void sa1100_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "intel,sa1100";
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x4401A11B;
- cpu->reset_sctlr = 0x00000070;
-}
-
-static void sa1110_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x6901B119;
- cpu->reset_sctlr = 0x00000070;
-}
-
static void pxa250_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2727,9 +2697,6 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "ti925t", .initfn = ti925t_initfn },
- { .name = "sa1100", .initfn = sa1100_initfn },
- { .name = "sa1110", .initfn = sa1110_initfn },
{ .name = "pxa250", .initfn = pxa250_initfn },
{ .name = "pxa255", .initfn = pxa255_initfn },
{ .name = "pxa260", .initfn = pxa260_initfn },
diff --git a/target/arm/cpu_v4.c b/target/arm/cpu_v4.c
new file mode 100644
index 0000000000..1de00a03ee
--- /dev/null
+++ b/target/arm/cpu_v4.c
@@ -0,0 +1,65 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void ti925t_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
+ cpu->midr = ARM_CPUID_TI925T;
+ cpu->ctr = 0x5109149;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static void sa1100_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "intel,sa1100";
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x4401A11B;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static void sa1110_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x6901B119;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static const ARMCPUInfo arm_v4_cpus[] = {
+ { .name = "ti925t", .initfn = ti925t_initfn },
+ { .name = "sa1100", .initfn = sa1100_initfn },
+ { .name = "sa1110", .initfn = sa1110_initfn },
+ { .name = NULL }
+};
+
+static void arm_v4_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v4_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v4_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e3d7e7694a..7fc0cff776 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -28,6 +28,7 @@ config ARM_VIRT
config CHEETAH
bool
+ select ARM_V4
select OMAP
select TSC210X
@@ -242,6 +243,7 @@ config COLLIE
config SX1
bool
+ select ARM_V4
select OMAP
config VERSATILE
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index e68c71a6ff..0d496d318a 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -1,2 +1,6 @@
+config ARM_V4
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index fa278bb4c1..bc0f63ebbc 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -68,6 +68,8 @@ obj-y += crypto_helper.o
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
obj-y += m_helper.o
+obj-$(CONFIG_ARM_V4) += cpu_v4.o
+
obj-$(CONFIG_SOFTMMU) += psci.o
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 2 -
target/arm/cpu.c | 33 -----------------
target/arm/cpu_v4.c | 65 +++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 2 +
target/arm/Kconfig | 4 ++
target/arm/Makefile.objs | 2 +
6 files changed, 73 insertions(+), 35 deletions(-)
create mode 100644 target/arm/cpu_v4.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 8b89d8c4c0..0652396296 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d2813eb81a..b08b6933be 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2459,36 +2459,6 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
-static void ti925t_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V4T);
- set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
- cpu->midr = ARM_CPUID_TI925T;
- cpu->ctr = 0x5109149;
- cpu->reset_sctlr = 0x00000070;
-}
-
-static void sa1100_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "intel,sa1100";
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x4401A11B;
- cpu->reset_sctlr = 0x00000070;
-}
-
-static void sa1110_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x6901B119;
- cpu->reset_sctlr = 0x00000070;
-}
-
static void pxa250_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2727,9 +2697,6 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "ti925t", .initfn = ti925t_initfn },
- { .name = "sa1100", .initfn = sa1100_initfn },
- { .name = "sa1110", .initfn = sa1110_initfn },
{ .name = "pxa250", .initfn = pxa250_initfn },
{ .name = "pxa255", .initfn = pxa255_initfn },
{ .name = "pxa260", .initfn = pxa260_initfn },
diff --git a/target/arm/cpu_v4.c b/target/arm/cpu_v4.c
new file mode 100644
index 0000000000..1de00a03ee
--- /dev/null
+++ b/target/arm/cpu_v4.c
@@ -0,0 +1,65 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void ti925t_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V4T);
+ set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
+ cpu->midr = ARM_CPUID_TI925T;
+ cpu->ctr = 0x5109149;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static void sa1100_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "intel,sa1100";
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x4401A11B;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static void sa1110_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x6901B119;
+ cpu->reset_sctlr = 0x00000070;
+}
+
+static const ARMCPUInfo arm_v4_cpus[] = {
+ { .name = "ti925t", .initfn = ti925t_initfn },
+ { .name = "sa1100", .initfn = sa1100_initfn },
+ { .name = "sa1110", .initfn = sa1110_initfn },
+ { .name = NULL }
+};
+
+static void arm_v4_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v4_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v4_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e3d7e7694a..7fc0cff776 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -28,6 +28,7 @@ config ARM_VIRT
config CHEETAH
bool
+ select ARM_V4
select OMAP
select TSC210X
@@ -242,6 +243,7 @@ config COLLIE
config SX1
bool
+ select ARM_V4
select OMAP
config VERSATILE
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index e68c71a6ff..0d496d318a 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -1,2 +1,6 @@
+config ARM_V4
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index fa278bb4c1..bc0f63ebbc 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -68,6 +68,8 @@ obj-y += crypto_helper.o
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
obj-y += m_helper.o
+obj-$(CONFIG_ARM_V4) += cpu_v4.o
+
obj-$(CONFIG_SOFTMMU) += psci.o
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv5 CPUs when TCG is available:
- ARM926
- ARM946
- ARM1026
- XScale (PXA250/255/260/261/262/270)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 12 --
target/arm/cpu.c | 234 ----------------------------
target/arm/cpu_v5.c | 266 ++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 7 +
target/arm/Kconfig | 4 +
target/arm/Makefile.objs | 1 +
6 files changed, 278 insertions(+), 246 deletions(-)
create mode 100644 target/arm/cpu_v5.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 0652396296..f176a98296 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -13,32 +13,20 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_MPS2=y
CONFIG_RASPI=y
-CONFIG_DIGIC=y
CONFIG_SABRELITE=y
CONFIG_EMCRAFT_SF2=y
CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ALLWINNER_H3=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b08b6933be..f1d1ba8451 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1834,86 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm926_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm926";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = 0x41069265;
- cpu->reset_fpsid = 0x41011090;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00090078;
-
- /*
- * ARMv5 does not have the ID_ISAR registers, but we can still
- * set the field to indicate Jazelle support within QEMU.
- */
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
- /*
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
- * support even though ARMv5 doesn't have this register.
- */
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
-}
-
-static void arm946_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm946";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x41059461;
- cpu->ctr = 0x0f004006;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void arm1026_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1026";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = 0x4106a262;
- cpu->reset_fpsid = 0x410110a0;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00090078;
- cpu->reset_auxcr = 1;
-
- /*
- * ARMv5 does not have the ID_ISAR registers, but we can still
- * set the field to indicate Jazelle support within QEMU.
- */
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
- /*
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
- * support even though ARMv5 doesn't have this register.
- */
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
-
- {
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
- ARMCPRegInfo ifar = {
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
- .resetvalue = 0
- };
- define_one_arm_cp_reg(cpu, &ifar);
- }
-}
-
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2459,144 +2379,6 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
-static void pxa250_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052100;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa255_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d00;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa260_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052903;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa261_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d05;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa262_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d06;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270a0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054110;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270a1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054111;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270b0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054112;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270b1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054113;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270c0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054114;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270c5_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054117;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
#ifndef TARGET_AARCH64
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
@@ -2670,9 +2452,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- { .name = "arm926", .initfn = arm926_initfn },
- { .name = "arm946", .initfn = arm946_initfn },
- { .name = "arm1026", .initfn = arm1026_initfn },
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
@@ -2697,19 +2476,6 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "pxa250", .initfn = pxa250_initfn },
- { .name = "pxa255", .initfn = pxa255_initfn },
- { .name = "pxa260", .initfn = pxa260_initfn },
- { .name = "pxa261", .initfn = pxa261_initfn },
- { .name = "pxa262", .initfn = pxa262_initfn },
- /* "pxa270" is an alias for "pxa270-a0" */
- { .name = "pxa270", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
#ifndef TARGET_AARCH64
{ .name = "max", .initfn = arm_max_initfn },
#endif
diff --git a/target/arm/cpu_v5.c b/target/arm/cpu_v5.c
new file mode 100644
index 0000000000..7a231ef649
--- /dev/null
+++ b/target/arm/cpu_v5.c
@@ -0,0 +1,266 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void arm926_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm926";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+ cpu->midr = 0x41069265;
+ cpu->reset_fpsid = 0x41011090;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
+
+ /*
+ * ARMv5 does not have the ID_ISAR registers, but we can still
+ * set the field to indicate Jazelle support within QEMU.
+ */
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
+}
+
+static void arm946_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm946";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x41059461;
+ cpu->ctr = 0x0f004006;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void arm1026_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1026";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+ cpu->midr = 0x4106a262;
+ cpu->reset_fpsid = 0x410110a0;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
+ cpu->reset_auxcr = 1;
+
+ /*
+ * ARMv5 does not have the ID_ISAR registers, but we can still
+ * set the field to indicate Jazelle support within QEMU.
+ */
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
+
+ {
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
+ ARMCPRegInfo ifar = {
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
+ .resetvalue = 0
+ };
+ define_one_arm_cp_reg(cpu, &ifar);
+ }
+}
+
+static void pxa250_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052100;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa255_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d00;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa260_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052903;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa261_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d05;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa262_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d06;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270a0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054110;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270a1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054111;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270b0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054112;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270b1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054113;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270c0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054114;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270c5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054117;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static const ARMCPUInfo arm_v5_cpus[] = {
+ { .name = "arm926", .initfn = arm926_initfn },
+ { .name = "arm946", .initfn = arm946_initfn },
+ { .name = "arm1026", .initfn = arm1026_initfn },
+ { .name = "pxa250", .initfn = pxa250_initfn },
+ { .name = "pxa255", .initfn = pxa255_initfn },
+ { .name = "pxa260", .initfn = pxa260_initfn },
+ { .name = "pxa261", .initfn = pxa261_initfn },
+ { .name = "pxa262", .initfn = pxa262_initfn },
+ /* "pxa270" is an alias for "pxa270-a0" */
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
+ { .name = NULL }
+};
+
+static void arm_v5_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v5_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v5_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7fc0cff776..3b78471de0 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -38,6 +38,7 @@ config CUBIEBOARD
config DIGIC
bool
+ select ARM_V5
select PTIMER
select PFLASH_CFI02
@@ -67,6 +68,7 @@ config HIGHBANK
config INTEGRATOR
bool
+ select ARM_V5
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -93,6 +95,7 @@ config MUSCA
config MUSICPAL
bool
+ select ARM_V5
select BITBANG_I2C
select MARVELL_88W8618
select PTIMER
@@ -132,6 +135,7 @@ config OMAP
config PXA2XX
bool
+ select ARM_V5
select FRAMEBUFFER
select I2C
select SERIAL
@@ -248,6 +252,7 @@ config SX1
config VERSATILE
bool
+ select ARM_V5
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -354,6 +359,7 @@ config XLNX_VERSAL
config FSL_IMX25
bool
+ select ARM_V5
select IMX
select IMX_FEC
select IMX_I2C
@@ -376,6 +382,7 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ select ARM_V5
select DS1338
select FTGMAC100
select I2C
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 0d496d318a..028d8382fe 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -2,5 +2,9 @@ config ARM_V4
depends on TCG
bool
+config ARM_V5
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index bc0f63ebbc..f66f7f1158 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -69,6 +69,7 @@ obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
+obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv5 CPUs when TCG is available:
- ARM926
- ARM946
- ARM1026
- XScale (PXA250/255/260/261/262/270)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 12 --
target/arm/cpu.c | 234 ----------------------------
target/arm/cpu_v5.c | 266 ++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 7 +
target/arm/Kconfig | 4 +
target/arm/Makefile.objs | 1 +
6 files changed, 278 insertions(+), 246 deletions(-)
create mode 100644 target/arm/cpu_v5.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 0652396296..f176a98296 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -13,32 +13,20 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_MPS2=y
CONFIG_RASPI=y
-CONFIG_DIGIC=y
CONFIG_SABRELITE=y
CONFIG_EMCRAFT_SF2=y
CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ALLWINNER_H3=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b08b6933be..f1d1ba8451 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1834,86 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm926_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm926";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = 0x41069265;
- cpu->reset_fpsid = 0x41011090;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00090078;
-
- /*
- * ARMv5 does not have the ID_ISAR registers, but we can still
- * set the field to indicate Jazelle support within QEMU.
- */
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
- /*
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
- * support even though ARMv5 doesn't have this register.
- */
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
-}
-
-static void arm946_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm946";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x41059461;
- cpu->ctr = 0x0f004006;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void arm1026_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1026";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_AUXCR);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = 0x4106a262;
- cpu->reset_fpsid = 0x410110a0;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00090078;
- cpu->reset_auxcr = 1;
-
- /*
- * ARMv5 does not have the ID_ISAR registers, but we can still
- * set the field to indicate Jazelle support within QEMU.
- */
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
- /*
- * Similarly, we need to set MVFR0 fields to enable vfp and short vector
- * support even though ARMv5 doesn't have this register.
- */
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
-
- {
- /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
- ARMCPRegInfo ifar = {
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
- .resetvalue = 0
- };
- define_one_arm_cp_reg(cpu, &ifar);
- }
-}
-
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2459,144 +2379,6 @@ static void cortex_a15_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
-static void pxa250_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052100;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa255_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d00;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa260_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052903;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa261_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d05;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa262_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = 0x69052d06;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270a0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054110;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270a1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054111;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270b0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054112;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270b1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054113;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270c0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054114;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
-static void pxa270c5_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "marvell,xscale";
- set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = 0x69054117;
- cpu->ctr = 0xd172172;
- cpu->reset_sctlr = 0x00000078;
-}
-
#ifndef TARGET_AARCH64
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
@@ -2670,9 +2452,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- { .name = "arm926", .initfn = arm926_initfn },
- { .name = "arm946", .initfn = arm946_initfn },
- { .name = "arm1026", .initfn = arm1026_initfn },
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
@@ -2697,19 +2476,6 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "pxa250", .initfn = pxa250_initfn },
- { .name = "pxa255", .initfn = pxa255_initfn },
- { .name = "pxa260", .initfn = pxa260_initfn },
- { .name = "pxa261", .initfn = pxa261_initfn },
- { .name = "pxa262", .initfn = pxa262_initfn },
- /* "pxa270" is an alias for "pxa270-a0" */
- { .name = "pxa270", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
#ifndef TARGET_AARCH64
{ .name = "max", .initfn = arm_max_initfn },
#endif
diff --git a/target/arm/cpu_v5.c b/target/arm/cpu_v5.c
new file mode 100644
index 0000000000..7a231ef649
--- /dev/null
+++ b/target/arm/cpu_v5.c
@@ -0,0 +1,266 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void arm926_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm926";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+ cpu->midr = 0x41069265;
+ cpu->reset_fpsid = 0x41011090;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
+
+ /*
+ * ARMv5 does not have the ID_ISAR registers, but we can still
+ * set the field to indicate Jazelle support within QEMU.
+ */
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
+}
+
+static void arm946_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm946";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x41059461;
+ cpu->ctr = 0x0f004006;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void arm1026_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1026";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_AUXCR);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+ cpu->midr = 0x4106a262;
+ cpu->reset_fpsid = 0x410110a0;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
+ cpu->reset_auxcr = 1;
+
+ /*
+ * ARMv5 does not have the ID_ISAR registers, but we can still
+ * set the field to indicate Jazelle support within QEMU.
+ */
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ /*
+ * Similarly, we need to set MVFR0 fields to enable vfp and short vector
+ * support even though ARMv5 doesn't have this register.
+ */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
+
+ {
+ /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
+ ARMCPRegInfo ifar = {
+ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
+ .resetvalue = 0
+ };
+ define_one_arm_cp_reg(cpu, &ifar);
+ }
+}
+
+static void pxa250_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052100;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa255_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d00;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa260_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052903;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa261_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d05;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa262_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ cpu->midr = 0x69052d06;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270a0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054110;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270a1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054111;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270b0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054112;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270b1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054113;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270c0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054114;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static void pxa270c5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "marvell,xscale";
+ set_feature(&cpu->env, ARM_FEATURE_V5);
+ set_feature(&cpu->env, ARM_FEATURE_XSCALE);
+ set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
+ cpu->midr = 0x69054117;
+ cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
+}
+
+static const ARMCPUInfo arm_v5_cpus[] = {
+ { .name = "arm926", .initfn = arm926_initfn },
+ { .name = "arm946", .initfn = arm946_initfn },
+ { .name = "arm1026", .initfn = arm1026_initfn },
+ { .name = "pxa250", .initfn = pxa250_initfn },
+ { .name = "pxa255", .initfn = pxa255_initfn },
+ { .name = "pxa260", .initfn = pxa260_initfn },
+ { .name = "pxa261", .initfn = pxa261_initfn },
+ { .name = "pxa262", .initfn = pxa262_initfn },
+ /* "pxa270" is an alias for "pxa270-a0" */
+ { .name = "pxa270", .initfn = pxa270a0_initfn },
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
+ { .name = NULL }
+};
+
+static void arm_v5_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v5_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v5_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7fc0cff776..3b78471de0 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -38,6 +38,7 @@ config CUBIEBOARD
config DIGIC
bool
+ select ARM_V5
select PTIMER
select PFLASH_CFI02
@@ -67,6 +68,7 @@ config HIGHBANK
config INTEGRATOR
bool
+ select ARM_V5
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -93,6 +95,7 @@ config MUSCA
config MUSICPAL
bool
+ select ARM_V5
select BITBANG_I2C
select MARVELL_88W8618
select PTIMER
@@ -132,6 +135,7 @@ config OMAP
config PXA2XX
bool
+ select ARM_V5
select FRAMEBUFFER
select I2C
select SERIAL
@@ -248,6 +252,7 @@ config SX1
config VERSATILE
bool
+ select ARM_V5
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -354,6 +359,7 @@ config XLNX_VERSAL
config FSL_IMX25
bool
+ select ARM_V5
select IMX
select IMX_FEC
select IMX_I2C
@@ -376,6 +382,7 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ select ARM_V5
select DS1338
select FTGMAC100
select I2C
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 0d496d318a..028d8382fe 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -2,5 +2,9 @@ config ARM_V4
depends on TCG
bool
+config ARM_V5
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index bc0f63ebbc..f66f7f1158 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -69,6 +69,7 @@ obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
+obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 2 -
target/arm/cpu.c | 137 -------------------------
target/arm/cpu_v6.c | 171 ++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 2 +
target/arm/Kconfig | 4 +
target/arm/Makefile.objs | 1 +
6 files changed, 178 insertions(+), 139 deletions(-)
create mode 100644 target/arm/cpu_v6.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f176a98296..3aa27f3b40 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -13,9 +13,7 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_FSL_IMX31=y
CONFIG_MUSCA=y
-CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f1d1ba8451..34908828a0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1834,135 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm1136_r2_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- * These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
-
- cpu->dtb_compatible = "arm,arm1136";
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = 0x4107b362;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0x2;
- cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm1136_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1136";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = 0x4117b363;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0x2;
- cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm1176_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1176";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- cpu->midr = 0x410fb767;
- cpu->reset_fpsid = 0x410120b5;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x11;
- cpu->isar.id_dfr0 = 0x33;
- cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222100;
- cpu->isar.id_isar0 = 0x0140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231121;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x01141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm11mpcore_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm11mpcore";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x410fb022;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0;
- cpu->id_afr0 = 0x2;
- cpu->isar.id_mmfr0 = 0x01100103;
- cpu->isar.id_mmfr1 = 0x10020302;
- cpu->isar.id_mmfr2 = 0x01222000;
- cpu->isar.id_isar0 = 0x00100011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11221011;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 1;
-}
-
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2452,14 +2323,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
- { .name = "arm1136", .initfn = arm1136_initfn },
- { .name = "arm1176", .initfn = arm1176_initfn },
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
diff --git a/target/arm/cpu_v6.c b/target/arm/cpu_v6.c
new file mode 100644
index 0000000000..1c73c881f3
--- /dev/null
+++ b/target/arm/cpu_v6.c
@@ -0,0 +1,171 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void arm1136_r2_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ /*
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ * These ID register values are correct for 1136 but may be wrong
+ * for 1136_r2 (in particular r0p2 does not actually implement most
+ * of the ID registers).
+ */
+
+ cpu->dtb_compatible = "arm,arm1136";
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ cpu->midr = 0x4107b362;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222110;
+ cpu->isar.id_isar0 = 0x00140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231111;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm1136_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1136";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ cpu->midr = 0x4117b363;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222110;
+ cpu->isar.id_isar0 = 0x00140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231111;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm1176_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1176";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->midr = 0x410fb767;
+ cpu->reset_fpsid = 0x410120b5;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x11;
+ cpu->isar.id_dfr0 = 0x33;
+ cpu->id_afr0 = 0;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222100;
+ cpu->isar.id_isar0 = 0x0140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231121;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x01141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm11mpcore_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm11mpcore";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x410fb022;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0;
+ cpu->id_afr0 = 0x2;
+ cpu->isar.id_mmfr0 = 0x01100103;
+ cpu->isar.id_mmfr1 = 0x10020302;
+ cpu->isar.id_mmfr2 = 0x01222000;
+ cpu->isar.id_isar0 = 0x00100011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11221011;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 1;
+}
+
+static const ARMCPUInfo arm_v6_cpus[] = {
+ /*
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e.
+ * an older core than plain "arm1136". In particular this does
+ * not have the v6K features.
+ */
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
+ { .name = "arm1136", .initfn = arm1136_initfn },
+ { .name = "arm1176", .initfn = arm1176_initfn },
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+ { .name = NULL }
+};
+
+static void arm_v6_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v6_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v6_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3b78471de0..e87dd611f2 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -113,6 +113,7 @@ config NETDUINOPLUS2
config NSERIES
bool
+ select ARM_V6
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -367,6 +368,7 @@ config FSL_IMX25
config FSL_IMX31
bool
+ select ARM_V6
select SERIAL
select IMX
select IMX_I2C
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 028d8382fe..df5f8dff42 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -6,5 +6,9 @@ config ARM_V5
depends on TCG
bool
+config ARM_V6
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index f66f7f1158..0473c559c6 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -70,6 +70,7 @@ obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
+obj-$(CONFIG_ARM_V6) += cpu_v6.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 2 -
target/arm/cpu.c | 137 -------------------------
target/arm/cpu_v6.c | 171 ++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 2 +
target/arm/Kconfig | 4 +
target/arm/Makefile.objs | 1 +
6 files changed, 178 insertions(+), 139 deletions(-)
create mode 100644 target/arm/cpu_v6.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f176a98296..3aa27f3b40 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -13,9 +13,7 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_FSL_IMX31=y
CONFIG_MUSCA=y
-CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f1d1ba8451..34908828a0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1834,135 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void arm1136_r2_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- * These ID register values are correct for 1136 but may be wrong
- * for 1136_r2 (in particular r0p2 does not actually implement most
- * of the ID registers).
- */
-
- cpu->dtb_compatible = "arm,arm1136";
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = 0x4107b362;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0x2;
- cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm1136_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1136";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = 0x4117b363;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0x2;
- cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm1176_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm1176";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
- set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- cpu->midr = 0x410fb767;
- cpu->reset_fpsid = 0x410120b5;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
- cpu->reset_sctlr = 0x00050078;
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x11;
- cpu->isar.id_dfr0 = 0x33;
- cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222100;
- cpu->isar.id_isar0 = 0x0140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231121;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x01141;
- cpu->reset_auxcr = 7;
-}
-
-static void arm11mpcore_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,arm11mpcore";
- set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VAPA);
- set_feature(&cpu->env, ARM_FEATURE_MPIDR);
- set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = 0x410fb022;
- cpu->reset_fpsid = 0x410120b4;
- cpu->isar.mvfr0 = 0x11111111;
- cpu->isar.mvfr1 = 0x00000000;
- cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
- cpu->id_pfr0 = 0x111;
- cpu->id_pfr1 = 0x1;
- cpu->isar.id_dfr0 = 0;
- cpu->id_afr0 = 0x2;
- cpu->isar.id_mmfr0 = 0x01100103;
- cpu->isar.id_mmfr1 = 0x10020302;
- cpu->isar.id_mmfr2 = 0x01222000;
- cpu->isar.id_isar0 = 0x00100011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11221011;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
- cpu->reset_auxcr = 1;
-}
-
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -2452,14 +2323,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
- * older core than plain "arm1136". In particular this does not
- * have the v6K features.
- */
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
- { .name = "arm1136", .initfn = arm1136_initfn },
- { .name = "arm1176", .initfn = arm1176_initfn },
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
diff --git a/target/arm/cpu_v6.c b/target/arm/cpu_v6.c
new file mode 100644
index 0000000000..1c73c881f3
--- /dev/null
+++ b/target/arm/cpu_v6.c
@@ -0,0 +1,171 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static void arm1136_r2_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ /*
+ * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
+ * older core than plain "arm1136". In particular this does not
+ * have the v6K features.
+ * These ID register values are correct for 1136 but may be wrong
+ * for 1136_r2 (in particular r0p2 does not actually implement most
+ * of the ID registers).
+ */
+
+ cpu->dtb_compatible = "arm,arm1136";
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ cpu->midr = 0x4107b362;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222110;
+ cpu->isar.id_isar0 = 0x00140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231111;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm1136_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1136";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ cpu->midr = 0x4117b363;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0x2;
+ cpu->id_afr0 = 0x3;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222110;
+ cpu->isar.id_isar0 = 0x00140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231111;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm1176_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm1176";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
+ set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->midr = 0x410fb767;
+ cpu->reset_fpsid = 0x410120b5;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x11;
+ cpu->isar.id_dfr0 = 0x33;
+ cpu->id_afr0 = 0;
+ cpu->isar.id_mmfr0 = 0x01130003;
+ cpu->isar.id_mmfr1 = 0x10030302;
+ cpu->isar.id_mmfr2 = 0x01222100;
+ cpu->isar.id_isar0 = 0x0140011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11231121;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x01141;
+ cpu->reset_auxcr = 7;
+}
+
+static void arm11mpcore_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,arm11mpcore";
+ set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VAPA);
+ set_feature(&cpu->env, ARM_FEATURE_MPIDR);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ cpu->midr = 0x410fb022;
+ cpu->reset_fpsid = 0x410120b4;
+ cpu->isar.mvfr0 = 0x11111111;
+ cpu->isar.mvfr1 = 0x00000000;
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
+ cpu->id_pfr0 = 0x111;
+ cpu->id_pfr1 = 0x1;
+ cpu->isar.id_dfr0 = 0;
+ cpu->id_afr0 = 0x2;
+ cpu->isar.id_mmfr0 = 0x01100103;
+ cpu->isar.id_mmfr1 = 0x10020302;
+ cpu->isar.id_mmfr2 = 0x01222000;
+ cpu->isar.id_isar0 = 0x00100011;
+ cpu->isar.id_isar1 = 0x12002111;
+ cpu->isar.id_isar2 = 0x11221011;
+ cpu->isar.id_isar3 = 0x01102131;
+ cpu->isar.id_isar4 = 0x141;
+ cpu->reset_auxcr = 1;
+}
+
+static const ARMCPUInfo arm_v6_cpus[] = {
+ /*
+ * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e.
+ * an older core than plain "arm1136". In particular this does
+ * not have the v6K features.
+ */
+ { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
+ { .name = "arm1136", .initfn = arm1136_initfn },
+ { .name = "arm1176", .initfn = arm1176_initfn },
+ { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
+ { .name = NULL }
+};
+
+static void arm_v6_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v6_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v6_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3b78471de0..e87dd611f2 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -113,6 +113,7 @@ config NETDUINOPLUS2
config NSERIES
bool
+ select ARM_V6
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -367,6 +368,7 @@ config FSL_IMX25
config FSL_IMX31
bool
+ select ARM_V6
select SERIAL
select IMX
select IMX_I2C
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 028d8382fe..df5f8dff42 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -6,5 +6,9 @@ config ARM_V5
depends on TCG
bool
+config ARM_V6
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index f66f7f1158..0473c559c6 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -70,6 +70,7 @@ obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
+obj-$(CONFIG_ARM_V6) += cpu_v6.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
A KVM-only build won't be able to run R-profile cpus.
Only enable the following ARMv7 R-Profile CPUs when TCG is available:
- Cortex-R5
- Cortex-R5F
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/aarch64-softmmu.mak | 1 -
target/arm/cpu.c | 51 ------------------
target/arm/cpu_v7r.c | 83 +++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
target/arm/Kconfig | 4 ++
target/arm/Makefile.objs | 1 +
6 files changed, 89 insertions(+), 52 deletions(-)
create mode 100644 target/arm/cpu_v7r.c
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
index 958b1e08e4..a4202f5681 100644
--- a/default-configs/aarch64-softmmu.mak
+++ b/default-configs/aarch64-softmmu.mak
@@ -3,6 +3,5 @@
# We support all the 32 bit boards so need all their config
include arm-softmmu.mak
-CONFIG_XLNX_ZYNQMP_ARM=y
CONFIG_XLNX_VERSAL=y
CONFIG_SBSA_REF=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 34908828a0..84be8792f6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1975,55 +1975,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
- /* Dummy the TCM region regs for the moment */
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST },
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST },
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
- REGINFO_SENTINEL
-};
-
-static void cortex_r5_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x411fc153; /* r1p3 */
- cpu->id_pfr0 = 0x0131;
- cpu->id_pfr1 = 0x001;
- cpu->isar.id_dfr0 = 0x010400;
- cpu->id_afr0 = 0x0;
- cpu->isar.id_mmfr0 = 0x0210030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0x0211;
- cpu->isar.id_isar0 = 0x02101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232141;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x0010142;
- cpu->isar.id_isar5 = 0x0;
- cpu->isar.id_isar6 = 0x0;
- cpu->mp_is_up = true;
- cpu->pmsav7_dregion = 16;
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
-}
-
-static void cortex_r5f_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cortex_r5_initfn(obj);
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x00000011;
-}
-
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2333,8 +2284,6 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init },
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
diff --git a/target/arm/cpu_v7r.c b/target/arm/cpu_v7r.c
new file mode 100644
index 0000000000..9576844b5c
--- /dev/null
+++ b/target/arm/cpu_v7r.c
@@ -0,0 +1,83 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
+ /* Dummy the TCM region regs for the moment */
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
+ REGINFO_SENTINEL
+};
+
+static void cortex_r5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x411fc153; /* r1p3 */
+ cpu->id_pfr0 = 0x0131;
+ cpu->id_pfr1 = 0x001;
+ cpu->isar.id_dfr0 = 0x010400;
+ cpu->id_afr0 = 0x0;
+ cpu->isar.id_mmfr0 = 0x0210030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01200000;
+ cpu->isar.id_mmfr3 = 0x0211;
+ cpu->isar.id_isar0 = 0x02101111;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232141;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x0010142;
+ cpu->isar.id_isar5 = 0x0;
+ cpu->isar.id_isar6 = 0x0;
+ cpu->mp_is_up = true;
+ cpu->pmsav7_dregion = 16;
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+}
+
+static void cortex_r5f_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cortex_r5_initfn(obj);
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x00000011;
+}
+
+static const ARMCPUInfo arm_v7r_cpus[] = {
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
+ { .name = NULL }
+};
+
+static void arm_v7r_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v7r_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v7r_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e87dd611f2..d0903d8544 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -340,6 +340,7 @@ config XLNX_ZYNQMP_ARM
bool
select AHCI
select ARM_GIC
+ select ARM_V7R
select CADENCE
select DDC
select DPCD
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index df5f8dff42..9768f9180f 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -10,5 +10,9 @@ config ARM_V6
depends on TCG
bool
+config ARM_V7R
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 0473c559c6..a2508f0655 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -71,6 +71,7 @@ obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_ARM_V6) += cpu_v6.o
+obj-$(CONFIG_ARM_V7R) += cpu_v7r.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
A KVM-only build won't be able to run R-profile cpus.
Only enable the following ARMv7 R-Profile CPUs when TCG is available:
- Cortex-R5
- Cortex-R5F
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/aarch64-softmmu.mak | 1 -
target/arm/cpu.c | 51 ------------------
target/arm/cpu_v7r.c | 83 +++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
target/arm/Kconfig | 4 ++
target/arm/Makefile.objs | 1 +
6 files changed, 89 insertions(+), 52 deletions(-)
create mode 100644 target/arm/cpu_v7r.c
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
index 958b1e08e4..a4202f5681 100644
--- a/default-configs/aarch64-softmmu.mak
+++ b/default-configs/aarch64-softmmu.mak
@@ -3,6 +3,5 @@
# We support all the 32 bit boards so need all their config
include arm-softmmu.mak
-CONFIG_XLNX_ZYNQMP_ARM=y
CONFIG_XLNX_VERSAL=y
CONFIG_SBSA_REF=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 34908828a0..84be8792f6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1975,55 +1975,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
-static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
- /* Dummy the TCM region regs for the moment */
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST },
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST },
- { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
- .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
- REGINFO_SENTINEL
-};
-
-static void cortex_r5_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x411fc153; /* r1p3 */
- cpu->id_pfr0 = 0x0131;
- cpu->id_pfr1 = 0x001;
- cpu->isar.id_dfr0 = 0x010400;
- cpu->id_afr0 = 0x0;
- cpu->isar.id_mmfr0 = 0x0210030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0x0211;
- cpu->isar.id_isar0 = 0x02101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232141;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x0010142;
- cpu->isar.id_isar5 = 0x0;
- cpu->isar.id_isar6 = 0x0;
- cpu->mp_is_up = true;
- cpu->pmsav7_dregion = 16;
- define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
-}
-
-static void cortex_r5f_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cortex_r5_initfn(obj);
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x00000011;
-}
-
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2333,8 +2284,6 @@ static const ARMCPUInfo arm_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init },
- { .name = "cortex-r5", .initfn = cortex_r5_initfn },
- { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
diff --git a/target/arm/cpu_v7r.c b/target/arm/cpu_v7r.c
new file mode 100644
index 0000000000..9576844b5c
--- /dev/null
+++ b/target/arm/cpu_v7r.c
@@ -0,0 +1,83 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
+ /* Dummy the TCM region regs for the moment */
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
+ REGINFO_SENTINEL
+};
+
+static void cortex_r5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x411fc153; /* r1p3 */
+ cpu->id_pfr0 = 0x0131;
+ cpu->id_pfr1 = 0x001;
+ cpu->isar.id_dfr0 = 0x010400;
+ cpu->id_afr0 = 0x0;
+ cpu->isar.id_mmfr0 = 0x0210030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01200000;
+ cpu->isar.id_mmfr3 = 0x0211;
+ cpu->isar.id_isar0 = 0x02101111;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232141;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x0010142;
+ cpu->isar.id_isar5 = 0x0;
+ cpu->isar.id_isar6 = 0x0;
+ cpu->mp_is_up = true;
+ cpu->pmsav7_dregion = 16;
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+}
+
+static void cortex_r5f_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cortex_r5_initfn(obj);
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x00000011;
+}
+
+static const ARMCPUInfo arm_v7r_cpus[] = {
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
+ { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
+ { .name = NULL }
+};
+
+static void arm_v7r_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v7r_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v7r_cpu_register_types)
+
+#endif
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e87dd611f2..d0903d8544 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -340,6 +340,7 @@ config XLNX_ZYNQMP_ARM
bool
select AHCI
select ARM_GIC
+ select ARM_V7R
select CADENCE
select DDC
select DPCD
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index df5f8dff42..9768f9180f 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -10,5 +10,9 @@ config ARM_V6
depends on TCG
bool
+config ARM_V7R
+ depends on TCG
+ bool
+
config ARM_V7M
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 0473c559c6..a2508f0655 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -71,6 +71,7 @@ obj-y += m_helper.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_ARM_V6) += cpu_v6.o
+obj-$(CONFIG_ARM_V7R) += cpu_v7r.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
A KVM-only build won't be able to run M-profile cpus.
Only enable the following ARMv7 M-Profile CPUs when TCG is available:
- Cortex-M3
- Cortex-M4
- Cortex-M33
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 8 --
target/arm/cpu.c | 176 ---------------------------
target/arm/cpu_v7m.c | 207 ++++++++++++++++++++++++++++++++
target/arm/Kconfig | 1 +
target/arm/Makefile.objs | 1 +
5 files changed, 209 insertions(+), 184 deletions(-)
create mode 100644 target/arm/cpu_v7m.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 3aa27f3b40..511d74da58 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -12,19 +12,11 @@ CONFIG_ARM_V7M=y
CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ALLWINNER_H3=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 84be8792f6..dfa7e64c7e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -573,31 +573,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- CPUClass *cc = CPU_GET_CLASS(cs);
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- bool ret = false;
-
- /* ARMv7-M interrupt masking works differently than -A or -R.
- * There is no FIQ/IRQ distinction. Instead of I and F bits
- * masking FIQ and IRQ interrupts, an exception is taken only
- * if it is higher priority than the current execution priority
- * (which depends on state like BASEPRI, FAULTMASK and the
- * currently active exception).
- */
- if (interrupt_request & CPU_INTERRUPT_HARD
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
- cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
- ret = true;
- }
- return ret;
-}
-#endif
-
void arm_cpu_update_virq(ARMCPU *cpu)
{
/*
@@ -1834,147 +1809,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void cortex_m0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_M);
-
- cpu->midr = 0x410cc200;
-}
-
-static void cortex_m3_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- cpu->midr = 0x410fc231;
- cpu->pmsav7_dregion = 8;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m4_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fc240; /* r0p0 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000000;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m7_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x411fc272; /* r1p2 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00100030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02112000;
- cpu->isar.id_isar2 = 0x20232231;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m33_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fd213; /* r0p3 */
- cpu->pmsav7_dregion = 16;
- cpu->sau_sregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000210;
- cpu->isar.id_dfr0 = 0x00200000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00101F40;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
- cpu->clidr = 0x00000000;
- cpu->ctr = 0x8000c000;
-}
-
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
-{
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- acc->info = data;
-#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
-#endif
-
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
-}
-
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2274,16 +2108,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
- .class_init = arm_v7m_class_init },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
diff --git a/target/arm/cpu_v7m.c b/target/arm/cpu_v7m.c
new file mode 100644
index 0000000000..529259b9cd
--- /dev/null
+++ b/target/arm/cpu_v7m.c
@@ -0,0 +1,207 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ bool ret = false;
+
+ /*
+ * ARMv7-M interrupt masking works differently than -A or -R.
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
+ * masking FIQ and IRQ interrupts, an exception is taken only
+ * if it is higher priority than the current execution priority
+ * (which depends on state like BASEPRI, FAULTMASK and the
+ * currently active exception).
+ */
+ if (interrupt_request & CPU_INTERRUPT_HARD
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
+ cs->exception_index = EXCP_IRQ;
+ cc->do_interrupt(cs);
+ ret = true;
+ }
+ return ret;
+}
+
+static void cortex_m0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+
+ cpu->midr = 0x410cc200;
+}
+
+static void cortex_m3_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ cpu->midr = 0x410fc231;
+ cpu->pmsav7_dregion = 8;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m4_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fc240; /* r0p0 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000000;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x411fc272; /* r1p2 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00100030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02112000;
+ cpu->isar.id_isar2 = 0x20232231;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m33_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd213; /* r0p3 */
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000210;
+ cpu->isar.id_dfr0 = 0x00200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00101F40;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000;
+ cpu->ctr = 0x8000c000;
+}
+
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
+{
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ acc->info = data;
+#ifndef CONFIG_USER_ONLY
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+#endif
+
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+}
+
+static const ARMCPUInfo arm_v7m_cpus[] = {
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = NULL }
+};
+
+static void arm_v7m_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v7m_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v7m_cpu_register_types)
+
+#endif
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 9768f9180f..929e252d89 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -15,4 +15,5 @@ config ARM_V7R
bool
config ARM_V7M
+ depends on TCG
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index a2508f0655..a0df58526b 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -72,6 +72,7 @@ obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_ARM_V6) += cpu_v6.o
obj-$(CONFIG_ARM_V7R) += cpu_v7r.o
+obj-$(CONFIG_ARM_V7M) += cpu_v7m.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
A KVM-only build won't be able to run M-profile cpus.
Only enable the following ARMv7 M-Profile CPUs when TCG is available:
- Cortex-M3
- Cortex-M4
- Cortex-M33
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 8 --
target/arm/cpu.c | 176 ---------------------------
target/arm/cpu_v7m.c | 207 ++++++++++++++++++++++++++++++++
target/arm/Kconfig | 1 +
target/arm/Makefile.objs | 1 +
5 files changed, 209 insertions(+), 184 deletions(-)
create mode 100644 target/arm/cpu_v7m.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 3aa27f3b40..511d74da58 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -12,19 +12,11 @@ CONFIG_ARM_V7M=y
CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ALLWINNER_H3=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 84be8792f6..dfa7e64c7e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -573,31 +573,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- CPUClass *cc = CPU_GET_CLASS(cs);
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- bool ret = false;
-
- /* ARMv7-M interrupt masking works differently than -A or -R.
- * There is no FIQ/IRQ distinction. Instead of I and F bits
- * masking FIQ and IRQ interrupts, an exception is taken only
- * if it is higher priority than the current execution priority
- * (which depends on state like BASEPRI, FAULTMASK and the
- * currently active exception).
- */
- if (interrupt_request & CPU_INTERRUPT_HARD
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
- cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
- ret = true;
- }
- return ret;
-}
-#endif
-
void arm_cpu_update_virq(ARMCPU *cpu)
{
/*
@@ -1834,147 +1809,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void cortex_m0_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_M);
-
- cpu->midr = 0x410cc200;
-}
-
-static void cortex_m3_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- cpu->midr = 0x410fc231;
- cpu->pmsav7_dregion = 8;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m4_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fc240; /* r0p0 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000000;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m7_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x411fc272; /* r1p2 */
- cpu->pmsav7_dregion = 8;
- cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000200;
- cpu->isar.id_dfr0 = 0x00100000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00100030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02112000;
- cpu->isar.id_isar2 = 0x20232231;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
-}
-
-static void cortex_m33_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_M);
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- cpu->midr = 0x410fd213; /* r0p3 */
- cpu->pmsav7_dregion = 16;
- cpu->sau_sregion = 8;
- cpu->isar.mvfr0 = 0x10110021;
- cpu->isar.mvfr1 = 0x11000011;
- cpu->isar.mvfr2 = 0x00000040;
- cpu->id_pfr0 = 0x00000030;
- cpu->id_pfr1 = 0x00000210;
- cpu->isar.id_dfr0 = 0x00200000;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00101F40;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
- cpu->clidr = 0x00000000;
- cpu->ctr = 0x8000c000;
-}
-
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
-{
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
- CPUClass *cc = CPU_CLASS(oc);
-
- acc->info = data;
-#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
-#endif
-
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
-}
-
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2274,16 +2108,6 @@ static void arm_max_initfn(Object *obj)
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
- .class_init = arm_v7m_class_init },
{ .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
diff --git a/target/arm/cpu_v7m.c b/target/arm/cpu_v7m.c
new file mode 100644
index 0000000000..529259b9cd
--- /dev/null
+++ b/target/arm/cpu_v7m.c
@@ -0,0 +1,207 @@
+/*
+ * ARM generic helpers.
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internals.h"
+
+/* CPU models. These are not needed for the AArch64 linux-user build. */
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ bool ret = false;
+
+ /*
+ * ARMv7-M interrupt masking works differently than -A or -R.
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
+ * masking FIQ and IRQ interrupts, an exception is taken only
+ * if it is higher priority than the current execution priority
+ * (which depends on state like BASEPRI, FAULTMASK and the
+ * currently active exception).
+ */
+ if (interrupt_request & CPU_INTERRUPT_HARD
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
+ cs->exception_index = EXCP_IRQ;
+ cc->do_interrupt(cs);
+ ret = true;
+ }
+ return ret;
+}
+
+static void cortex_m0_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V6);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+
+ cpu->midr = 0x410cc200;
+}
+
+static void cortex_m3_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ cpu->midr = 0x410fc231;
+ cpu->pmsav7_dregion = 8;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m4_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fc240; /* r0p0 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000000;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x411fc272; /* r1p2 */
+ cpu->pmsav7_dregion = 8;
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00100030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02112000;
+ cpu->isar.id_isar2 = 0x20232231;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+}
+
+static void cortex_m33_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd213; /* r0p3 */
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ cpu->isar.mvfr0 = 0x10110021;
+ cpu->isar.mvfr1 = 0x11000011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->id_pfr0 = 0x00000030;
+ cpu->id_pfr1 = 0x00000210;
+ cpu->isar.id_dfr0 = 0x00200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00101F40;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01101110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000;
+ cpu->ctr = 0x8000c000;
+}
+
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
+{
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+
+ acc->info = data;
+#ifndef CONFIG_USER_ONLY
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+#endif
+
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+}
+
+static const ARMCPUInfo arm_v7m_cpus[] = {
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
+ .class_init = arm_v7m_class_init },
+ { .name = NULL }
+};
+
+static void arm_v7m_cpu_register_types(void)
+{
+ const ARMCPUInfo *info = arm_v7m_cpus;
+
+ while (info->name) {
+ arm_cpu_register(info);
+ info++;
+ }
+}
+
+type_init(arm_v7m_cpu_register_types)
+
+#endif
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 9768f9180f..929e252d89 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -15,4 +15,5 @@ config ARM_V7R
bool
config ARM_V7M
+ depends on TCG
bool
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index a2508f0655..a0df58526b 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -72,6 +72,7 @@ obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
obj-$(CONFIG_ARM_V6) += cpu_v6.o
obj-$(CONFIG_ARM_V7R) += cpu_v7r.o
+obj-$(CONFIG_ARM_V7M) += cpu_v7m.o
obj-$(CONFIG_SOFTMMU) += psci.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
From: Thomas Huth <thuth@redhat.com>
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other code without CONFIG_ARM_V7M.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190903154810.27365-4-thuth@redhat.com>
[PMD: add write_v7m_exception() stub when not using TCG,
remove CONFIG_ARM_V7M=y in default-configs/arm-softmmu.mak]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 6 ----
target/arm/cpu.h | 7 ++++
target/arm/m_helper-stub.c | 59 +++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 3 +-
4 files changed, 68 insertions(+), 7 deletions(-)
create mode 100644 target/arm/m_helper-stub.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 511d74da58..7ae8006556 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -1,11 +1,5 @@
# Default configuration for arm-softmmu
-# CONFIG_SEMIHOSTING is always required on this architecture
-CONFIG_SEMIHOSTING=y
-
-# TODO: ARM_V7M is currently always required - make this more flexible!
-CONFIG_ARM_V7M=y
-
# CONFIG_PCI_DEVICES=n
# CONFIG_TEST_DEVICES=n
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4ffd991b6f..84e14ce5a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1278,7 +1278,14 @@ void pmu_init(ARMCPU *cpu);
/* Write a new value to v7m.exception, thus transitioning into or out
* of Handler mode; this may result in a change of active stack pointer.
*/
+#if !defined(CONFIG_TCG)
+static inline void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ g_assert_not_reached();
+}
+#else
void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
+#endif
/* Map EL and handler into a PSTATE_MODE. */
static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c
new file mode 100644
index 0000000000..9316a9995b
--- /dev/null
+++ b/target/arm/m_helper-stub.c
@@ -0,0 +1,59 @@
+/*
+ * ARM V7M related stubs.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "internals.h"
+
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+{
+ abort();
+}
+
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+ abort();
+}
+
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+{
+ abort();
+}
+
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+{
+ abort();
+}
+
+uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+{
+ abort();
+}
+
+void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
+{
+ abort();
+}
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ abort();
+}
+
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ abort();
+}
+
+void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
+{
+ abort();
+}
+
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+ abort();
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index a0df58526b..993899d731 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -66,7 +66,8 @@ obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
-obj-y += m_helper.o
+obj-$(CONFIG_ARM_V7M) += m_helper.o
+obj-$(call lnot,$(CONFIG_ARM_V7M)) += m_helper-stub.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other code without CONFIG_ARM_V7M.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190903154810.27365-4-thuth@redhat.com>
[PMD: add write_v7m_exception() stub when not using TCG,
remove CONFIG_ARM_V7M=y in default-configs/arm-softmmu.mak]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/arm-softmmu.mak | 6 ----
target/arm/cpu.h | 7 ++++
target/arm/m_helper-stub.c | 59 +++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 3 +-
4 files changed, 68 insertions(+), 7 deletions(-)
create mode 100644 target/arm/m_helper-stub.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 511d74da58..7ae8006556 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -1,11 +1,5 @@
# Default configuration for arm-softmmu
-# CONFIG_SEMIHOSTING is always required on this architecture
-CONFIG_SEMIHOSTING=y
-
-# TODO: ARM_V7M is currently always required - make this more flexible!
-CONFIG_ARM_V7M=y
-
# CONFIG_PCI_DEVICES=n
# CONFIG_TEST_DEVICES=n
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4ffd991b6f..84e14ce5a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1278,7 +1278,14 @@ void pmu_init(ARMCPU *cpu);
/* Write a new value to v7m.exception, thus transitioning into or out
* of Handler mode; this may result in a change of active stack pointer.
*/
+#if !defined(CONFIG_TCG)
+static inline void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ g_assert_not_reached();
+}
+#else
void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
+#endif
/* Map EL and handler into a PSTATE_MODE. */
static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c
new file mode 100644
index 0000000000..9316a9995b
--- /dev/null
+++ b/target/arm/m_helper-stub.c
@@ -0,0 +1,59 @@
+/*
+ * ARM V7M related stubs.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "internals.h"
+
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+{
+ abort();
+}
+
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+ abort();
+}
+
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+{
+ abort();
+}
+
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+{
+ abort();
+}
+
+uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+{
+ abort();
+}
+
+void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
+{
+ abort();
+}
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ abort();
+}
+
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ abort();
+}
+
+void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
+{
+ abort();
+}
+
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+ abort();
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index a0df58526b..993899d731 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -66,7 +66,8 @@ obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
-obj-y += m_helper.o
+obj-$(CONFIG_ARM_V7M) += m_helper.o
+obj-$(call lnot,$(CONFIG_ARM_V7M)) += m_helper-stub.o
obj-$(CONFIG_ARM_V4) += cpu_v4.o
obj-$(CONFIG_ARM_V5) += cpu_v5.o
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 16/19] target/arm: Do not build TCG objects when TCG is off
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson, Samuel Ortiz
From: Samuel Ortiz <sameo@linux.intel.com>
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
[PMD: Heavily rebased during 18 months]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/Makefile.objs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 993899d731..0178431549 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -60,8 +60,6 @@ ifeq ($(CONFIG_TCG),y)
obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
-endif # CONFIG_TCG
-
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
@@ -80,3 +78,5 @@ obj-$(CONFIG_SOFTMMU) += psci.o
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
obj-$(TARGET_AARCH64) += pauth_helper.o
+
+endif # CONFIG_TCG
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 16/19] target/arm: Do not build TCG objects when TCG is off
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Samuel Ortiz, kvm,
Alex Bennée, Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
From: Samuel Ortiz <sameo@linux.intel.com>
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
[PMD: Heavily rebased during 18 months]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/Makefile.objs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 993899d731..0178431549 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -60,8 +60,6 @@ ifeq ($(CONFIG_TCG),y)
obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
-endif # CONFIG_TCG
-
obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o
obj-y += crypto_helper.o
@@ -80,3 +78,5 @@ obj-$(CONFIG_SOFTMMU) += psci.o
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
obj-$(TARGET_AARCH64) += pauth_helper.o
+
+endif # CONFIG_TCG
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
When building a KVM-only QEMU, the 'virt' machine is a good
default :)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index d0903d8544..8e801cd15f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,5 +1,6 @@
config ARM_VIRT
bool
+ default y if KVM
imply PCI_DEVICES
imply TEST_DEVICES
imply VFIO_AMD_XGBE
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
When building a KVM-only QEMU, the 'virt' machine is a good
default :)
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index d0903d8544..8e801cd15f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,5 +1,6 @@
config ARM_VIRT
bool
+ default y if KVM
imply PCI_DEVICES
imply TEST_DEVICES
imply VFIO_AMD_XGBE
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
2020-03-16 16:06 ` Philippe Mathieu-Daudé
(?)
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson,
Stefano Stabellini, Anthony Perard, Paul Durrant, xen-devel
Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
machine there to avoid odd errors such:
CC i386-softmmu/hw/cpu/a15mpcore.o
hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
[*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Paul Durrant <paul@xen.org>
Cc: xen-devel@lists.xenproject.org
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 8e801cd15f..69a8e30125 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,5 +1,6 @@
config ARM_VIRT
bool
+ depends on !XEN
default y if KVM
imply PCI_DEVICES
imply TEST_DEVICES
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Stefano Stabellini, kvm,
Paul Durrant, Alex Bennée, Richard Henderson, qemu-arm,
xen-devel, Anthony Perard, Paolo Bonzini,
Philippe Mathieu-Daudé
Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
machine there to avoid odd errors such:
CC i386-softmmu/hw/cpu/a15mpcore.o
hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
[*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Paul Durrant <paul@xen.org>
Cc: xen-devel@lists.xenproject.org
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 8e801cd15f..69a8e30125 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,5 +1,6 @@
config ARM_VIRT
bool
+ depends on !XEN
default y if KVM
imply PCI_DEVICES
imply TEST_DEVICES
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [Xen-devel] [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Stefano Stabellini, kvm,
Paul Durrant, Alex Bennée, Richard Henderson, qemu-arm,
xen-devel, Anthony Perard, Paolo Bonzini,
Philippe Mathieu-Daudé
Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
machine there to avoid odd errors such:
CC i386-softmmu/hw/cpu/a15mpcore.o
hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
[*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Paul Durrant <paul@xen.org>
Cc: xen-devel@lists.xenproject.org
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 8e801cd15f..69a8e30125 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,5 +1,6 @@
config ARM_VIRT
bool
+ depends on !XEN
default y if KVM
imply PCI_DEVICES
imply TEST_DEVICES
--
2.21.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 19/19] .travis.yml: Add a KVM-only Aarch64 job
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Philippe Mathieu-Daudé,
Paolo Bonzini, Peter Maydell, Richard Henderson
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Job ran for 13 min 1 sec
https://travis-ci.org/github/philmd/qemu/jobs/663122258
---
.travis.yml | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index b92798ac3b..ea3c0df185 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -450,6 +450,38 @@ jobs:
- TEST_CMD="make check check-tcg V=1"
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
+ - name: "[aarch64] GCC check (KVM)"
+ arch: arm64
+ dist: xenial
+ addons:
+ apt_packages:
+ - libaio-dev
+ - libattr1-dev
+ - libcap-ng-dev
+ - libgcrypt20-dev
+ - libgnutls28-dev
+ - libiscsi-dev
+ - liblttng-ust-dev
+ - libnfs-dev
+ - libnss3-dev
+ - libpixman-1-dev
+ - libpng-dev
+ - librados-dev
+ - libseccomp-dev
+ - liburcu-dev
+ - libusb-1.0-0-dev
+ - libvdeplug-dev
+ - libvte-2.91-dev
+ # Tests dependencies
+ - genisoimage
+ env:
+ - CONFIG="--disable-containers --disable-tcg --enable-kvm --enable-fdt --disable-tools"
+ - TEST_CMD="make check-unit"
+ script:
+ # Only select the 'virt' machine.
+ - echo CONFIG_ARM_VIRT=y > ${SRC_DIR}/default-configs/aarch64-softmmu.mak
+ - make -j3 && travis_retry ${TEST_CMD}
+
- name: "[ppc64] GCC check-tcg"
arch: ppc64le
dist: xenial
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* [PATCH v3 19/19] .travis.yml: Add a KVM-only Aarch64 job
@ 2020-03-16 16:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 16:06 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Paolo Bonzini,
Philippe Mathieu-Daudé
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Job ran for 13 min 1 sec
https://travis-ci.org/github/philmd/qemu/jobs/663122258
---
.travis.yml | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index b92798ac3b..ea3c0df185 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -450,6 +450,38 @@ jobs:
- TEST_CMD="make check check-tcg V=1"
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
+ - name: "[aarch64] GCC check (KVM)"
+ arch: arm64
+ dist: xenial
+ addons:
+ apt_packages:
+ - libaio-dev
+ - libattr1-dev
+ - libcap-ng-dev
+ - libgcrypt20-dev
+ - libgnutls28-dev
+ - libiscsi-dev
+ - liblttng-ust-dev
+ - libnfs-dev
+ - libnss3-dev
+ - libpixman-1-dev
+ - libpng-dev
+ - librados-dev
+ - libseccomp-dev
+ - liburcu-dev
+ - libusb-1.0-0-dev
+ - libvdeplug-dev
+ - libvte-2.91-dev
+ # Tests dependencies
+ - genisoimage
+ env:
+ - CONFIG="--disable-containers --disable-tcg --enable-kvm --enable-fdt --disable-tools"
+ - TEST_CMD="make check-unit"
+ script:
+ # Only select the 'virt' machine.
+ - echo CONFIG_ARM_VIRT=y > ${SRC_DIR}/default-configs/aarch64-softmmu.mak
+ - make -j3 && travis_retry ${TEST_CMD}
+
- name: "[ppc64] GCC check-tcg"
arch: ppc64le
dist: xenial
--
2.21.1
^ permalink raw reply related [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
2020-03-16 16:06 ` Philippe Mathieu-Daudé
(?)
@ 2020-03-16 17:05 ` Stefano Stabellini
-1 siblings, 0 replies; 122+ messages in thread
From: Stefano Stabellini @ 2020-03-16 17:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Alex Bennée, kvm, Thomas Huth, qemu-arm,
Fam Zheng, Paolo Bonzini, Peter Maydell, Richard Henderson,
Stefano Stabellini, Anthony Perard, Paul Durrant, xen-devel
[-- Attachment #1: Type: text/plain, Size: 1581 bytes --]
On Mon, 16 Mar 2020, Philippe Mathieu-Daudé wrote:
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
I confirm that what's written on that wikipage is correct: Xen on ARM
doesn't use QEMU for emulation, only as a PV backends provider. As such,
and also because the code is a bit entangled with the x86 platform, even
on ARM we are building and running qemu-system-i386 to get the PV disk
and PV framebuffer. Of course, no x86 emulation is actually done.
Ideally we would have a non-arch-specific machine type for the PV
backends, but that doesn't exist today.
In short, I think this patch is fine, at least until somebody comes
around and tries to add emulation to Xen on ARM.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
> 2.21.1
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 17:05 ` Stefano Stabellini
0 siblings, 0 replies; 122+ messages in thread
From: Stefano Stabellini @ 2020-03-16 17:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Stefano Stabellini, kvm,
Paul Durrant, Richard Henderson, qemu-devel, qemu-arm, xen-devel,
Anthony Perard, Paolo Bonzini, Alex Bennée
[-- Attachment #1: Type: text/plain, Size: 1628 bytes --]
On Mon, 16 Mar 2020, Philippe Mathieu-Daudé wrote:
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
I confirm that what's written on that wikipage is correct: Xen on ARM
doesn't use QEMU for emulation, only as a PV backends provider. As such,
and also because the code is a bit entangled with the x86 platform, even
on ARM we are building and running qemu-system-i386 to get the PV disk
and PV framebuffer. Of course, no x86 emulation is actually done.
Ideally we would have a non-arch-specific machine type for the PV
backends, but that doesn't exist today.
In short, I think this patch is fine, at least until somebody comes
around and tries to add emulation to Xen on ARM.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
> 2.21.1
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [Xen-devel] [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 17:05 ` Stefano Stabellini
0 siblings, 0 replies; 122+ messages in thread
From: Stefano Stabellini @ 2020-03-16 17:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Stefano Stabellini, kvm,
Paul Durrant, Richard Henderson, qemu-devel, qemu-arm, xen-devel,
Anthony Perard, Paolo Bonzini, Alex Bennée
[-- Attachment #1: Type: text/plain, Size: 1581 bytes --]
On Mon, 16 Mar 2020, Philippe Mathieu-Daudé wrote:
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
I confirm that what's written on that wikipage is correct: Xen on ARM
doesn't use QEMU for emulation, only as a PV backends provider. As such,
and also because the code is a bit entangled with the x86 platform, even
on ARM we are building and running qemu-system-i386 to get the PV disk
and PV framebuffer. Of course, no x86 emulation is actually done.
Ideally we would have a non-arch-specific machine type for the PV
backends, but that doesn't exist today.
In short, I think this patch is fine, at least until somebody comes
around and tries to add emulation to Xen on ARM.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
> 2.21.1
>
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
2020-03-16 16:06 ` Philippe Mathieu-Daudé
(?)
@ 2020-03-16 17:11 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-03-16 17:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini, Richard Henderson,
Stefano Stabellini, Anthony Perard, Paul Durrant, open list:X86
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
This seems odd to me:
(1) the error message you quote is for a15mpcore.c, not virt.c
(2) shouldn't this be prevented by something saying "don't build
guest architecture X boards into Y-softmmu", rather than a specific
flag for a specific arm board ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 17:11 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-03-16 17:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, Stefano Stabellini, kvm-devel,
Paul Durrant, Richard Henderson, QEMU Developers, qemu-arm,
open list:X86, Anthony Perard, Paolo Bonzini, Alex Bennée
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
This seems odd to me:
(1) the error message you quote is for a15mpcore.c, not virt.c
(2) shouldn't this be prevented by something saying "don't build
guest architecture X boards into Y-softmmu", rather than a specific
flag for a specific arm board ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [Xen-devel] [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 17:11 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-03-16 17:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, Stefano Stabellini, kvm-devel,
Paul Durrant, Richard Henderson, QEMU Developers, qemu-arm,
open list:X86, Anthony Perard, Paolo Bonzini, Alex Bennée
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
> machine there to avoid odd errors such:
>
> CC i386-softmmu/hw/cpu/a15mpcore.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> Cc: Stefano Stabellini <sstabellini@kernel.org>
> Cc: Anthony Perard <anthony.perard@citrix.com>
> Cc: Paul Durrant <paul@xen.org>
> Cc: xen-devel@lists.xenproject.org
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8e801cd15f..69a8e30125 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + depends on !XEN
> default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> --
This seems odd to me:
(1) the error message you quote is for a15mpcore.c, not virt.c
(2) shouldn't this be prevented by something saying "don't build
guest architecture X boards into Y-softmmu", rather than a specific
flag for a specific arm board ?
thanks
-- PMM
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
2020-03-16 17:11 ` Peter Maydell
(?)
@ 2020-03-16 19:00 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 19:00 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini, Richard Henderson,
Stefano Stabellini, Anthony Perard, Paul Durrant, open list:X86
On 3/16/20 6:11 PM, Peter Maydell wrote:
> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
>> machine there to avoid odd errors such:
>>
>> CC i386-softmmu/hw/cpu/a15mpcore.o
>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>
>> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> Cc: Stefano Stabellini <sstabellini@kernel.org>
>> Cc: Anthony Perard <anthony.perard@citrix.com>
>> Cc: Paul Durrant <paul@xen.org>
>> Cc: xen-devel@lists.xenproject.org
>> ---
>> hw/arm/Kconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index 8e801cd15f..69a8e30125 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -1,5 +1,6 @@
>> config ARM_VIRT
>> bool
>> + depends on !XEN
>> default y if KVM
>> imply PCI_DEVICES
>> imply TEST_DEVICES
>> --
>
> This seems odd to me:
> (1) the error message you quote is for a15mpcore.c, not virt.c
This is the first device the virt board selects:
config ARM_VIRT
bool
imply PCI_DEVICES
imply TEST_DEVICES
imply VFIO_AMD_XGBE
imply VFIO_PLATFORM
imply VFIO_XGMAC
imply TPM_TIS_SYSBUS
select A15MPCORE
...
> (2) shouldn't this be prevented by something saying "don't build
> guest architecture X boards into Y-softmmu", rather than a specific
> flag for a specific arm board ?
Yes, agreed. This surgical change was quicker for my testing, but we
don't need this patch right now, so let's drop it.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 19:00 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 19:00 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, Stefano Stabellini, kvm-devel,
Paul Durrant, Richard Henderson, QEMU Developers, qemu-arm,
open list:X86, Anthony Perard, Paolo Bonzini, Alex Bennée
On 3/16/20 6:11 PM, Peter Maydell wrote:
> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
>> machine there to avoid odd errors such:
>>
>> CC i386-softmmu/hw/cpu/a15mpcore.o
>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>
>> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> Cc: Stefano Stabellini <sstabellini@kernel.org>
>> Cc: Anthony Perard <anthony.perard@citrix.com>
>> Cc: Paul Durrant <paul@xen.org>
>> Cc: xen-devel@lists.xenproject.org
>> ---
>> hw/arm/Kconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index 8e801cd15f..69a8e30125 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -1,5 +1,6 @@
>> config ARM_VIRT
>> bool
>> + depends on !XEN
>> default y if KVM
>> imply PCI_DEVICES
>> imply TEST_DEVICES
>> --
>
> This seems odd to me:
> (1) the error message you quote is for a15mpcore.c, not virt.c
This is the first device the virt board selects:
config ARM_VIRT
bool
imply PCI_DEVICES
imply TEST_DEVICES
imply VFIO_AMD_XGBE
imply VFIO_PLATFORM
imply VFIO_XGMAC
imply TPM_TIS_SYSBUS
select A15MPCORE
...
> (2) shouldn't this be prevented by something saying "don't build
> guest architecture X boards into Y-softmmu", rather than a specific
> flag for a specific arm board ?
Yes, agreed. This surgical change was quicker for my testing, but we
don't need this patch right now, so let's drop it.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [Xen-devel] [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen
@ 2020-03-16 19:00 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-16 19:00 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, Stefano Stabellini, kvm-devel,
Paul Durrant, Richard Henderson, QEMU Developers, qemu-arm,
open list:X86, Anthony Perard, Paolo Bonzini, Alex Bennée
On 3/16/20 6:11 PM, Peter Maydell wrote:
> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
>> machine there to avoid odd errors such:
>>
>> CC i386-softmmu/hw/cpu/a15mpcore.o
>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>
>> [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> Cc: Stefano Stabellini <sstabellini@kernel.org>
>> Cc: Anthony Perard <anthony.perard@citrix.com>
>> Cc: Paul Durrant <paul@xen.org>
>> Cc: xen-devel@lists.xenproject.org
>> ---
>> hw/arm/Kconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index 8e801cd15f..69a8e30125 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -1,5 +1,6 @@
>> config ARM_VIRT
>> bool
>> + depends on !XEN
>> default y if KVM
>> imply PCI_DEVICES
>> imply TEST_DEVICES
>> --
>
> This seems odd to me:
> (1) the error message you quote is for a15mpcore.c, not virt.c
This is the first device the virt board selects:
config ARM_VIRT
bool
imply PCI_DEVICES
imply TEST_DEVICES
imply VFIO_AMD_XGBE
imply VFIO_PLATFORM
imply VFIO_XGMAC
imply TPM_TIS_SYSBUS
select A15MPCORE
...
> (2) shouldn't this be prevented by something saying "don't build
> guest architecture X boards into Y-softmmu", rather than a specific
> flag for a specific arm board ?
Yes, agreed. This surgical change was quicker for my testing, but we
don't need this patch right now, so let's drop it.
>
> thanks
> -- PMM
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:36 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:36 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the 'Data or unified Cache line Clean by VA to PoP'
> instruction will trap.
>
> Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index b61ee73d18..924deffd65 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
> uint64_t value)
> {
> @@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = {
> .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
> REGINFO_SENTINEL
> };
> -#endif /*CONFIG_USER_ONLY*/
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
I'm not 100% sure how the system regs function under kvm.
If they are not used at all, then we should avoid them all en masse an not
piecemeal like this.
If they are used for something, then we should keep them registered and change
the writefn like so:
#ifdef CONFIG_TCG
/* existing stuff */
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
#endif
r~
>
> -#endif
> +#endif /* TARGET_AARCH64 */
>
> static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
> bool isread)
> @@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> if (cpu_isar_feature(aa64_rndr, cpu)) {
> define_arm_cp_regs(cpu, rndr_reginfo);
> }
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* Data Cache clean instructions up to PoP */
> if (cpu_isar_feature(aa64_dcpop, cpu)) {
> define_one_arm_cp_reg(cpu, dcpop_reg);
> @@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> define_one_arm_cp_reg(cpu, dcpodp_reg);
> }
> }
> -#endif /*CONFIG_USER_ONLY*/
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> +#endif /* TARGET_AARCH64 */
>
> if (cpu_isar_feature(any_predinv, cpu)) {
> define_arm_cp_regs(cpu, predinv_reginfo);
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-03-16 19:36 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:36 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the 'Data or unified Cache line Clean by VA to PoP'
> instruction will trap.
>
> Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index b61ee73d18..924deffd65 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
> uint64_t value)
> {
> @@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] = {
> .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
> REGINFO_SENTINEL
> };
> -#endif /*CONFIG_USER_ONLY*/
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
I'm not 100% sure how the system regs function under kvm.
If they are not used at all, then we should avoid them all en masse an not
piecemeal like this.
If they are used for something, then we should keep them registered and change
the writefn like so:
#ifdef CONFIG_TCG
/* existing stuff */
#else
/* Handled by hardware accelerator. */
g_assert_not_reached();
#endif
r~
>
> -#endif
> +#endif /* TARGET_AARCH64 */
>
> static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
> bool isread)
> @@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> if (cpu_isar_feature(aa64_rndr, cpu)) {
> define_arm_cp_regs(cpu, rndr_reginfo);
> }
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* Data Cache clean instructions up to PoP */
> if (cpu_isar_feature(aa64_dcpop, cpu)) {
> define_one_arm_cp_reg(cpu, dcpop_reg);
> @@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> define_one_arm_cp_reg(cpu, dcpodp_reg);
> }
> }
> -#endif /*CONFIG_USER_ONLY*/
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> +#endif /* TARGET_AARCH64 */
>
> if (cpu_isar_feature(any_predinv, cpu)) {
> define_arm_cp_regs(cpu, predinv_reginfo);
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:37 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ATS instruction will trap.
Not trap, they'll just work.
Otherwise similar comment as for dcpop.
r~
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 924deffd65..a5280c091b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> }
> }
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* get_phys_addr() isn't present for user-mode-only targets */
>
> static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
>
> env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
> }
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> static const ARMCPRegInfo vapa_cp_reginfo[] = {
> { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
> @@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
> .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
> offsetoflow32(CPUARMState, cp15.par_ns) },
> .writefn = par_write },
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* This underdecoding is safe because the reginfo is NO_RAW. */
> { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
> .access = PL1_W, .accessfn = ats_access,
> @@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
> .access = PL2_W, .type = ARM_CP_NO_RAW,
> .writefn = tlbi_aa64_alle1is_write },
> -#ifndef CONFIG_USER_ONLY
> +
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* 64 bit address translation operations */
> { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
> .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
> @@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .access = PL1_RW, .resetvalue = 0,
> .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
> .writefn = par_write },
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> +
> /* TLB invalidate last level of translation table walk */
> { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
> @@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
> .access = PL2_W, .type = ARM_CP_NO_RAW,
> .writefn = tlbi_aa64_vae2is_write },
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* Unlike the other EL2-related AT operations, these must
> * UNDEF from EL3 if EL2 is not implemented, which is why we
> * define them here rather than with the rest of the AT ops.
> @@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> static const ARMCPRegInfo ats1e1_reginfo[] = {
> { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
> .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
> @@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> if (cpu_isar_feature(aa64_pan, cpu)) {
> define_one_arm_cp_reg(cpu, &pan_reginfo);
> }
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> if (cpu_isar_feature(aa64_ats1e1, cpu)) {
> define_arm_cp_regs(cpu, ats1e1_reginfo);
> }
> if (cpu_isar_feature(aa32_ats1e1, cpu)) {
> define_arm_cp_regs(cpu, ats1cp_reginfo);
> }
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> if (cpu_isar_feature(aa64_uao, cpu)) {
> define_one_arm_cp_reg(cpu, &uao_reginfo);
> }
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel
@ 2020-03-16 19:37 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ATS instruction will trap.
Not trap, they'll just work.
Otherwise similar comment as for dcpop.
r~
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 924deffd65..a5280c091b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> }
> }
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* get_phys_addr() isn't present for user-mode-only targets */
>
> static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
>
> env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
> }
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> static const ARMCPRegInfo vapa_cp_reginfo[] = {
> { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
> @@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
> .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
> offsetoflow32(CPUARMState, cp15.par_ns) },
> .writefn = par_write },
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* This underdecoding is safe because the reginfo is NO_RAW. */
> { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
> .access = PL1_W, .accessfn = ats_access,
> @@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
> .access = PL2_W, .type = ARM_CP_NO_RAW,
> .writefn = tlbi_aa64_alle1is_write },
> -#ifndef CONFIG_USER_ONLY
> +
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* 64 bit address translation operations */
> { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
> .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
> @@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .access = PL1_RW, .resetvalue = 0,
> .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
> .writefn = par_write },
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> +
> /* TLB invalidate last level of translation table walk */
> { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
> @@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
> .access = PL2_W, .type = ARM_CP_NO_RAW,
> .writefn = tlbi_aa64_vae2is_write },
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> /* Unlike the other EL2-related AT operations, these must
> * UNDEF from EL3 if EL2 is not implemented, which is why we
> * define them here rather than with the rest of the AT ops.
> @@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> static const ARMCPRegInfo ats1e1_reginfo[] = {
> { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
> .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
> @@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> if (cpu_isar_feature(aa64_pan, cpu)) {
> define_one_arm_cp_reg(cpu, &pan_reginfo);
> }
> -#ifndef CONFIG_USER_ONLY
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> if (cpu_isar_feature(aa64_ats1e1, cpu)) {
> define_arm_cp_regs(cpu, ats1e1_reginfo);
> }
> if (cpu_isar_feature(aa32_ats1e1, cpu)) {
> define_arm_cp_regs(cpu, ats1cp_reginfo);
> }
> -#endif
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
> if (cpu_isar_feature(aa64_uao, cpu)) {
> define_one_arm_cp_reg(cpu, &uao_reginfo);
> }
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:46 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Semihosting requires TCG. When configured with --disable-tcg, the
> build fails because the 'do_arm_semihosting' is missing. Instead
> of adding more few more #ifdeffery to the helper code, add a stub.
...
> ifeq ($(CONFIG_TCG),y)
>
> -obj-y += arm-semi.o
> +obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
> +obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
>
> endif # CONFIG_TCG
This code doesn't match the comment.
Why isn't this
obj-$(call land,$(CONFIG_TCG),$(CONFIG_SEMIHOSTING)) += arm-semi.o
obj-$(call lnot,$(call land ...)) += arm-semi-stub.o
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG
@ 2020-03-16 19:46 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Semihosting requires TCG. When configured with --disable-tcg, the
> build fails because the 'do_arm_semihosting' is missing. Instead
> of adding more few more #ifdeffery to the helper code, add a stub.
...
> ifeq ($(CONFIG_TCG),y)
>
> -obj-y += arm-semi.o
> +obj-$(CONFIG_SEMIHOSTING) += arm-semi.o
> +obj-$(call lnot,$(CONFIG_SEMIHOSTING)) += arm-semi-stub.o
>
> endif # CONFIG_TCG
This code doesn't match the comment.
Why isn't this
obj-$(call land,$(CONFIG_TCG),$(CONFIG_SEMIHOSTING)) += arm-semi.o
obj-$(call lnot,$(call land ...)) += arm-semi-stub.o
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:50 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static const ARMCPUInfo arm_v4_cpus[] = {
> + { .name = "ti925t", .initfn = ti925t_initfn },
> + { .name = "sa1100", .initfn = sa1100_initfn },
> + { .name = "sa1110", .initfn = sa1110_initfn },
> + { .name = NULL }
> +};
> +
> +static void arm_v4_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v4_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
I much prefer ARRAY_SIZE() to sentinels.
I know the existing code make much use of them,
but we don't need to replicate that here.
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2020-03-16 19:50 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static const ARMCPUInfo arm_v4_cpus[] = {
> + { .name = "ti925t", .initfn = ti925t_initfn },
> + { .name = "sa1100", .initfn = sa1100_initfn },
> + { .name = "sa1110", .initfn = sa1110_initfn },
> + { .name = NULL }
> +};
> +
> +static void arm_v4_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v4_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
I much prefer ARRAY_SIZE() to sentinels.
I know the existing code make much use of them,
but we don't need to replicate that here.
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
2020-03-16 19:50 ` Richard Henderson
@ 2020-03-16 19:51 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 12:50 PM, Richard Henderson wrote:
> I much prefer ARRAY_SIZE() to sentinels.
> I know the existing code make much use of them,
> but we don't need to replicate that here.
... but otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2020-03-16 19:51 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 12:50 PM, Richard Henderson wrote:
> I much prefer ARRAY_SIZE() to sentinels.
> I know the existing code make much use of them,
> but we don't need to replicate that here.
... but otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:52 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v5_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v5_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Similarly wrt ARRAY_SIZE. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel
@ 2020-03-16 19:52 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v5_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v5_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Similarly wrt ARRAY_SIZE. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:54 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v6_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v6_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel
@ 2020-03-16 19:54 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v6_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v6_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:55 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7r_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v7r_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
@ 2020-03-16 19:55 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7r_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v7r_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:57 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7m_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v7m_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
@ 2020-03-16 19:57 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7m_cpu_register_types(void)
> +{
> + const ARMCPUInfo *info = arm_v7m_cpus;
> +
> + while (info->name) {
> + arm_cpu_register(info);
> + info++;
> + }
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 19:59 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> @@ -1,11 +1,5 @@
> # Default configuration for arm-softmmu
>
> -# CONFIG_SEMIHOSTING is always required on this architecture
> -CONFIG_SEMIHOSTING=y
This doesn't belong to this patch. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
@ 2020-03-16 19:59 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 19:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> @@ -1,11 +1,5 @@
> # Default configuration for arm-softmmu
>
> -# CONFIG_SEMIHOSTING is always required on this architecture
> -CONFIG_SEMIHOSTING=y
This doesn't belong to this patch. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:03 ` no-reply
-1 siblings, 0 replies; 122+ messages in thread
From: no-reply @ 2020-03-16 20:03 UTC (permalink / raw)
To: philmd
Cc: qemu-devel, fam, peter.maydell, thuth, kvm, alex.bennee,
richard.henderson, qemu-arm, pbonzini, philmd
Patchew URL: https://patchew.org/QEMU/20200316160634.3386-1-philmd@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
missing object type 'or-irq'
Broken pipe
/tmp/qemu-test/src/tests/qtest/libqtest.c:175: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
ERROR - too few tests run (expected 6, got 5)
make: *** [check-qtest-aarch64] Error 1
make: *** Waiting for unfinished jobs....
Could not access KVM kernel module: No such file or directory
qemu-system-x86_64: -accel kvm: failed to initialize kvm: No such file or directory
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=08bd1beebdb64d78b4b65d35e7611a89', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-t2n0p0f3/src/docker-src.2020-03-16-15.51.58.19896:/var/tmp/qemu:z,ro', 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=08bd1beebdb64d78b4b65d35e7611a89
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-t2n0p0f3/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 11m59.274s
user 0m8.577s
The full log is available at
http://patchew.org/logs/20200316160634.3386-1-philmd@redhat.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
@ 2020-03-16 20:03 ` no-reply
0 siblings, 0 replies; 122+ messages in thread
From: no-reply @ 2020-03-16 20:03 UTC (permalink / raw)
To: philmd
Cc: fam, peter.maydell, thuth, kvm, philmd, richard.henderson,
qemu-devel, qemu-arm, pbonzini, alex.bennee
Patchew URL: https://patchew.org/QEMU/20200316160634.3386-1-philmd@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
missing object type 'or-irq'
Broken pipe
/tmp/qemu-test/src/tests/qtest/libqtest.c:175: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
ERROR - too few tests run (expected 6, got 5)
make: *** [check-qtest-aarch64] Error 1
make: *** Waiting for unfinished jobs....
Could not access KVM kernel module: No such file or directory
qemu-system-x86_64: -accel kvm: failed to initialize kvm: No such file or directory
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=08bd1beebdb64d78b4b65d35e7611a89', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-t2n0p0f3/src/docker-src.2020-03-16-15.51.58.19896:/var/tmp/qemu:z,ro', 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=08bd1beebdb64d78b4b65d35e7611a89
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-t2n0p0f3/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 11m59.274s
user 0m8.577s
The full log is available at
http://patchew.org/logs/20200316160634.3386-1-philmd@redhat.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:06 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> When building a KVM-only QEMU, the 'virt' machine is a good
> default :)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index d0903d8544..8e801cd15f 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> imply VFIO_AMD_XGBE
>
Likewise SBSA_REF? Otherwise, what is this for?
Did you remove ARM_VIRT from default-config/*?
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-03-16 20:06 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> When building a KVM-only QEMU, the 'virt' machine is a good
> default :)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index d0903d8544..8e801cd15f 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> imply VFIO_AMD_XGBE
>
Likewise SBSA_REF? Otherwise, what is this for?
Did you remove ARM_VIRT from default-config/*?
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:09 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> ARM_V7M is a concept tied to the architecture. Move it to the
> target/arm/ directory to keep the hardware/architecture separation
> clearer.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 3 ---
> target/Kconfig | 2 +-
> target/arm/Kconfig | 2 ++
> 3 files changed, 3 insertions(+), 4 deletions(-)
> create mode 100644 target/arm/Kconfig
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/
@ 2020-03-16 20:09 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> ARM_V7M is a concept tied to the architecture. Move it to the
> target/arm/ directory to keep the hardware/architecture separation
> clearer.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 3 ---
> target/Kconfig | 2 +-
> target/arm/Kconfig | 2 ++
> 3 files changed, 3 insertions(+), 4 deletions(-)
> create mode 100644 target/arm/Kconfig
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 07/19] target/arm: Make cpu_register() available for other files
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:10 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell, Eric Auger
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> From: Thomas Huth <thuth@redhat.com>
>
> Make cpu_register() (renamed to arm_cpu_register()) available
> from internals.h so we can register CPUs also from other files
> in the future.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Message-ID: <20190921150420.30743-2-thuth@redhat.com>
> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/cpu-qom.h | 9 ++++++++-
> target/arm/cpu.c | 10 ++--------
> target/arm/cpu64.c | 8 +-------
> 3 files changed, 11 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 07/19] target/arm: Make cpu_register() available for other files
@ 2020-03-16 20:10 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:10 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Eric Auger, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> From: Thomas Huth <thuth@redhat.com>
>
> Make cpu_register() (renamed to arm_cpu_register()) available
> from internals.h so we can register CPUs also from other files
> in the future.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Message-ID: <20190921150420.30743-2-thuth@redhat.com>
> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/cpu-qom.h | 9 ++++++++-
> target/arm/cpu.c | 10 ++--------
> target/arm/cpu64.c | 8 +-------
> 3 files changed, 11 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-03-16 19:36 ` Richard Henderson
@ 2020-03-16 20:11 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-03-16 20:11 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé,
QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini
On Mon, 16 Mar 2020 at 19:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I'm not 100% sure how the system regs function under kvm.
>
> If they are not used at all, then we should avoid them all en masse an not
> piecemeal like this.
>
> If they are used for something, then we should keep them registered and change
> the writefn like so:
>
> #ifdef CONFIG_TCG
> /* existing stuff */
> #else
> /* Handled by hardware accelerator. */
> g_assert_not_reached();
> #endif
(1) for those registers where we need to know the value within
QEMU code (notably anything involved in VA-to-PA translation,
as this is used by gdbstub accesses, etc, but sometimes we
want other register values too): the sysreg struct is
what lets us map from the KVM register to the field in the
CPU struct when we do a sync of data to/from the kernel.
(2) for other registers, the sync lets us make the register
visible as an r/o register in the gdbstub. (this is not
very important, but it's nice)
(3) Either way, the sync works via the raw_read/raw_write
accessors (this is a big part of what they're for), which are
supposed to just stuff the data into/out of the underlying
CPU struct field. (But watch out because we fall back to
using the non-raw read/writefn if there's no raw version
provided for a particular register.) If a regdef is marked
as NO_RAW then it means there is no raw access and we don't
sync the value.
(4) I think that in KVM mode we won't deliberately do
non-raw accesses, and a quick grep through of the places
that do 'readfn' accesses supports that.
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-03-16 20:11 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-03-16 20:11 UTC (permalink / raw)
To: Richard Henderson
Cc: Fam Zheng, Thomas Huth, kvm-devel, Philippe Mathieu-Daudé,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Mon, 16 Mar 2020 at 19:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I'm not 100% sure how the system regs function under kvm.
>
> If they are not used at all, then we should avoid them all en masse an not
> piecemeal like this.
>
> If they are used for something, then we should keep them registered and change
> the writefn like so:
>
> #ifdef CONFIG_TCG
> /* existing stuff */
> #else
> /* Handled by hardware accelerator. */
> g_assert_not_reached();
> #endif
(1) for those registers where we need to know the value within
QEMU code (notably anything involved in VA-to-PA translation,
as this is used by gdbstub accesses, etc, but sometimes we
want other register values too): the sysreg struct is
what lets us map from the KVM register to the field in the
CPU struct when we do a sync of data to/from the kernel.
(2) for other registers, the sync lets us make the register
visible as an r/o register in the gdbstub. (this is not
very important, but it's nice)
(3) Either way, the sync works via the raw_read/raw_write
accessors (this is a big part of what they're for), which are
supposed to just stuff the data into/out of the underlying
CPU struct field. (But watch out because we fall back to
using the non-raw read/writefn if there's no raw version
provided for a particular register.) If a regdef is marked
as NO_RAW then it means there is no raw access and we don't
sync the value.
(4) I think that in KVM mode we won't deliberately do
non-raw accesses, and a quick grep through of the places
that do 'readfn' accesses supports that.
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:16 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +++ b/target/arm/kvm32.c
> @@ -22,7 +22,7 @@
> #include "internals.h"
> #include "qemu/log.h"
>
> -static inline void set_feature(uint64_t *features, int feature)
> +static inline void kvm_set_feature(uint64_t *features, int feature)
Why, what's wrong with the existing name?
Plus, with patch 2, you can just remove these.
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-03-16 20:16 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +++ b/target/arm/kvm32.c
> @@ -22,7 +22,7 @@
> #include "internals.h"
> #include "qemu/log.h"
>
> -static inline void set_feature(uint64_t *features, int feature)
> +static inline void kvm_set_feature(uint64_t *features, int feature)
Why, what's wrong with the existing name?
Plus, with patch 2, you can just remove these.
r~
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 20:17 ` Richard Henderson
-1 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ARMv8.1-VHE instruction will trap.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
What happened to the uses of these functions?
r~
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index a5280c091b..ce6778283d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> gt_ctl_write(env, ri, GTIMER_VIRT, value);
> }
>
> -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> - uint64_t value)
> -{
> - ARMCPU *cpu = env_archcpu(env);
> -
> - trace_arm_gt_cntvoff_write(value);
> - raw_write(env, ri, value);
> - gt_recalc_timer(cpu, GTIMER_VIRT);
> -}
> -
> static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
> const ARMCPRegInfo *ri)
> {
> @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> gt_ctl_write(env, ri, timeridx, value);
> }
>
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + ARMCPU *cpu = env_archcpu(env);
> +
> + trace_arm_gt_cntvoff_write(value);
> + raw_write(env, ri, value);
> + gt_recalc_timer(cpu, GTIMER_VIRT);
> +}
> +
> static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> gt_timer_reset(env, ri, GTIMER_HYP);
> @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> {
> gt_ctl_write(env, ri, GTIMER_HYP, value);
> }
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> {
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
@ 2020-03-16 20:17 ` Richard Henderson
0 siblings, 0 replies; 122+ messages in thread
From: Richard Henderson @ 2020-03-16 20:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ARMv8.1-VHE instruction will trap.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
What happened to the uses of these functions?
r~
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index a5280c091b..ce6778283d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> gt_ctl_write(env, ri, GTIMER_VIRT, value);
> }
>
> -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> - uint64_t value)
> -{
> - ARMCPU *cpu = env_archcpu(env);
> -
> - trace_arm_gt_cntvoff_write(value);
> - raw_write(env, ri, value);
> - gt_recalc_timer(cpu, GTIMER_VIRT);
> -}
> -
> static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
> const ARMCPRegInfo *ri)
> {
> @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> gt_ctl_write(env, ri, timeridx, value);
> }
>
> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
> +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + ARMCPU *cpu = env_archcpu(env);
> +
> + trace_arm_gt_cntvoff_write(value);
> + raw_write(env, ri, value);
> + gt_recalc_timer(cpu, GTIMER_VIRT);
> +}
> +
> static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> gt_timer_reset(env, ri, GTIMER_HYP);
> @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> {
> gt_ctl_write(env, ri, GTIMER_HYP, value);
> }
> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> {
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-03-16 23:10 ` no-reply
-1 siblings, 0 replies; 122+ messages in thread
From: no-reply @ 2020-03-16 23:10 UTC (permalink / raw)
To: philmd
Cc: qemu-devel, fam, peter.maydell, thuth, kvm, alex.bennee,
richard.henderson, qemu-arm, pbonzini, philmd
Patchew URL: https://patchew.org/QEMU/20200316160634.3386-1-philmd@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
missing object type 'or-irq'
Broken pipe
/tmp/qemu-test/src/tests/qtest/libqtest.c:175: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
ERROR - too few tests run (expected 6, got 5)
make: *** [check-qtest-aarch64] Error 1
make: *** Waiting for unfinished jobs....
Could not access KVM kernel module: No such file or directory
qemu-system-x86_64: -accel kvm: failed to initialize kvm: No such file or directory
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=d51fe73160644e0ba6a0f3cf1c1d6208', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-u8ju4ssp/src/docker-src.2020-03-16-18.57.13.21007:/var/tmp/qemu:z,ro', 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=d51fe73160644e0ba6a0f3cf1c1d6208
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-u8ju4ssp/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 13m16.228s
user 0m8.763s
The full log is available at
http://patchew.org/logs/20200316160634.3386-1-philmd@redhat.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 00/19] Support disabling TCG on ARM (part 2)
@ 2020-03-16 23:10 ` no-reply
0 siblings, 0 replies; 122+ messages in thread
From: no-reply @ 2020-03-16 23:10 UTC (permalink / raw)
To: philmd
Cc: fam, peter.maydell, thuth, kvm, philmd, richard.henderson,
qemu-devel, qemu-arm, pbonzini, alex.bennee
Patchew URL: https://patchew.org/QEMU/20200316160634.3386-1-philmd@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
missing object type 'or-irq'
Broken pipe
/tmp/qemu-test/src/tests/qtest/libqtest.c:175: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
ERROR - too few tests run (expected 6, got 5)
make: *** [check-qtest-aarch64] Error 1
make: *** Waiting for unfinished jobs....
Could not access KVM kernel module: No such file or directory
qemu-system-x86_64: -accel kvm: failed to initialize kvm: No such file or directory
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=d51fe73160644e0ba6a0f3cf1c1d6208', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-u8ju4ssp/src/docker-src.2020-03-16-18.57.13.21007:/var/tmp/qemu:z,ro', 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=d51fe73160644e0ba6a0f3cf1c1d6208
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-u8ju4ssp/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 13m16.228s
user 0m8.763s
The full log is available at
http://patchew.org/logs/20200316160634.3386-1-philmd@redhat.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-03-16 20:16 ` Richard Henderson
@ 2020-03-17 9:09 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-17 9:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:16 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> +++ b/target/arm/kvm32.c
>> @@ -22,7 +22,7 @@
>> #include "internals.h"
>> #include "qemu/log.h"
>>
>> -static inline void set_feature(uint64_t *features, int feature)
>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>
> Why, what's wrong with the existing name?
> Plus, with patch 2, you can just remove these.
The prototypes are different:
void set_feature(uint64_t *features, int feature)
void set_feature(CPUARMState *env, int feature)
Anyway you are right, I'll use the later prototype instead, thanks.
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-03-17 9:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-03-17 9:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:16 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> +++ b/target/arm/kvm32.c
>> @@ -22,7 +22,7 @@
>> #include "internals.h"
>> #include "qemu/log.h"
>>
>> -static inline void set_feature(uint64_t *features, int feature)
>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>
> Why, what's wrong with the existing name?
> Plus, with patch 2, you can just remove these.
The prototypes are different:
void set_feature(uint64_t *features, int feature)
void set_feature(CPUARMState *env, int feature)
Anyway you are right, I'll use the later prototype instead, thanks.
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-03-16 20:11 ` Peter Maydell
@ 2020-04-17 13:49 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-17 13:49 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini
On 3/16/20 9:11 PM, Peter Maydell wrote:
> On Mon, 16 Mar 2020 at 19:36, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> I'm not 100% sure how the system regs function under kvm.
>>
>> If they are not used at all, then we should avoid them all en masse an not
>> piecemeal like this.
>>
>> If they are used for something, then we should keep them registered and change
>> the writefn like so:
>>
>> #ifdef CONFIG_TCG
>> /* existing stuff */
>> #else
>> /* Handled by hardware accelerator. */
>> g_assert_not_reached();
>> #endif
I ended with that patch because dccvap_writefn() calls probe_read()
which is an inlined call to probe_access(), which itself is only defined
when using TCG. So with KVM either linking fails or I get:
target/arm/helper.c: In function ‘dccvap_writefn’:
target/arm/helper.c:6898:13: error: implicit declaration of function
‘probe_read’;
haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
^~~~~~~~~~
I'll use your suggestion which works for me:
-- >8 --
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -330,8 +330,20 @@ static inline void
tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
{
}
#endif
+
+#ifdef CONFIG_TCG
void *probe_access(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t
retaddr);
+#else
+static inline void *probe_access(CPUArchState *env,
+ target_ulong addr, int size,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+}
+#endif /* CONFIG_TCG */
static inline void *probe_write(CPUArchState *env, target_ulong addr,
int size,
int mmu_idx, uintptr_t retaddr)
---
>
> (1) for those registers where we need to know the value within
> QEMU code (notably anything involved in VA-to-PA translation,
> as this is used by gdbstub accesses, etc, but sometimes we
> want other register values too): the sysreg struct is
> what lets us map from the KVM register to the field in the
> CPU struct when we do a sync of data to/from the kernel.
>
> (2) for other registers, the sync lets us make the register
> visible as an r/o register in the gdbstub. (this is not
> very important, but it's nice)
>
> (3) Either way, the sync works via the raw_read/raw_write
> accessors (this is a big part of what they're for), which are
> supposed to just stuff the data into/out of the underlying
> CPU struct field. (But watch out because we fall back to
> using the non-raw read/writefn if there's no raw version
> provided for a particular register.) If a regdef is marked
> as NO_RAW then it means there is no raw access and we don't
> sync the value.
>
> (4) I think that in KVM mode we won't deliberately do
> non-raw accesses, and a quick grep through of the places
> that do 'readfn' accesses supports that.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-04-17 13:49 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-17 13:49 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson
Cc: Fam Zheng, Thomas Huth, kvm-devel, QEMU Developers, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:11 PM, Peter Maydell wrote:
> On Mon, 16 Mar 2020 at 19:36, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> I'm not 100% sure how the system regs function under kvm.
>>
>> If they are not used at all, then we should avoid them all en masse an not
>> piecemeal like this.
>>
>> If they are used for something, then we should keep them registered and change
>> the writefn like so:
>>
>> #ifdef CONFIG_TCG
>> /* existing stuff */
>> #else
>> /* Handled by hardware accelerator. */
>> g_assert_not_reached();
>> #endif
I ended with that patch because dccvap_writefn() calls probe_read()
which is an inlined call to probe_access(), which itself is only defined
when using TCG. So with KVM either linking fails or I get:
target/arm/helper.c: In function ‘dccvap_writefn’:
target/arm/helper.c:6898:13: error: implicit declaration of function
‘probe_read’;
haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
^~~~~~~~~~
I'll use your suggestion which works for me:
-- >8 --
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -330,8 +330,20 @@ static inline void
tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
{
}
#endif
+
+#ifdef CONFIG_TCG
void *probe_access(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t
retaddr);
+#else
+static inline void *probe_access(CPUArchState *env,
+ target_ulong addr, int size,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+}
+#endif /* CONFIG_TCG */
static inline void *probe_write(CPUArchState *env, target_ulong addr,
int size,
int mmu_idx, uintptr_t retaddr)
---
>
> (1) for those registers where we need to know the value within
> QEMU code (notably anything involved in VA-to-PA translation,
> as this is used by gdbstub accesses, etc, but sometimes we
> want other register values too): the sysreg struct is
> what lets us map from the KVM register to the field in the
> CPU struct when we do a sync of data to/from the kernel.
>
> (2) for other registers, the sync lets us make the register
> visible as an r/o register in the gdbstub. (this is not
> very important, but it's nice)
>
> (3) Either way, the sync works via the raw_read/raw_write
> accessors (this is a big part of what they're for), which are
> supposed to just stuff the data into/out of the underlying
> CPU struct field. (But watch out because we fall back to
> using the non-raw read/writefn if there's no raw version
> provided for a particular register.) If a regdef is marked
> as NO_RAW then it means there is no raw access and we don't
> sync the value.
>
> (4) I think that in KVM mode we won't deliberately do
> non-raw accesses, and a quick grep through of the places
> that do 'readfn' accesses supports that.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-04-17 13:49 ` Philippe Mathieu-Daudé
@ 2020-04-17 13:54 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-17 13:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Paolo Bonzini
On Fri, 17 Apr 2020 at 14:49, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 3/16/20 9:11 PM, Peter Maydell wrote:
> > On Mon, 16 Mar 2020 at 19:36, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >> I'm not 100% sure how the system regs function under kvm.
> >>
> >> If they are not used at all, then we should avoid them all en masse an not
> >> piecemeal like this.
> >>
> >> If they are used for something, then we should keep them registered and change
> >> the writefn like so:
> >>
> >> #ifdef CONFIG_TCG
> >> /* existing stuff */
> >> #else
> >> /* Handled by hardware accelerator. */
> >> g_assert_not_reached();
> >> #endif
>
> I ended with that patch because dccvap_writefn() calls probe_read()
> which is an inlined call to probe_access(), which itself is only defined
> when using TCG. So with KVM either linking fails or I get:
>
> target/arm/helper.c: In function ‘dccvap_writefn’:
> target/arm/helper.c:6898:13: error: implicit declaration of function
> ‘probe_read’;
> haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
> ^~~~~~~~~~
IN this particular case, DC CVAP is really a system insn rather
than a 'register'; our register struct for it is marked up as
ARM_CP_NO_RAW, which means we'll effectively ignore it when
running KVM (it will not be migrated, have its state synced
against the kernel, or be visible in gdb). If dccvap_writefn()
ever gets called somehow that's a bug, so having it end up
with an assert is the right thing.
> I'll use your suggestion which works for me:
Your suggested patch isn't quite the same as RTH's suggestion,
because it puts the assert inside a stub probe_read()
implementation rather than having the ifdef at the level
of the writefn body. I have no opinion on whether one or
the other of these is preferable.
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-04-17 13:54 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-17 13:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Fri, 17 Apr 2020 at 14:49, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 3/16/20 9:11 PM, Peter Maydell wrote:
> > On Mon, 16 Mar 2020 at 19:36, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >> I'm not 100% sure how the system regs function under kvm.
> >>
> >> If they are not used at all, then we should avoid them all en masse an not
> >> piecemeal like this.
> >>
> >> If they are used for something, then we should keep them registered and change
> >> the writefn like so:
> >>
> >> #ifdef CONFIG_TCG
> >> /* existing stuff */
> >> #else
> >> /* Handled by hardware accelerator. */
> >> g_assert_not_reached();
> >> #endif
>
> I ended with that patch because dccvap_writefn() calls probe_read()
> which is an inlined call to probe_access(), which itself is only defined
> when using TCG. So with KVM either linking fails or I get:
>
> target/arm/helper.c: In function ‘dccvap_writefn’:
> target/arm/helper.c:6898:13: error: implicit declaration of function
> ‘probe_read’;
> haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
> ^~~~~~~~~~
IN this particular case, DC CVAP is really a system insn rather
than a 'register'; our register struct for it is marked up as
ARM_CP_NO_RAW, which means we'll effectively ignore it when
running KVM (it will not be migrated, have its state synced
against the kernel, or be visible in gdb). If dccvap_writefn()
ever gets called somehow that's a bug, so having it end up
with an assert is the right thing.
> I'll use your suggestion which works for me:
Your suggested patch isn't quite the same as RTH's suggestion,
because it puts the assert inside a stub probe_read()
implementation rather than having the ifdef at the level
of the writefn body. I have no opinion on whether one or
the other of these is preferable.
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-04-17 13:54 ` Peter Maydell
@ 2020-04-17 14:19 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-17 14:19 UTC (permalink / raw)
To: Peter Maydell
Cc: Richard Henderson, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Paolo Bonzini
On 4/17/20 3:54 PM, Peter Maydell wrote:
> On Fri, 17 Apr 2020 at 14:49, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> On 3/16/20 9:11 PM, Peter Maydell wrote:
>>> On Mon, 16 Mar 2020 at 19:36, Richard Henderson
>>> <richard.henderson@linaro.org> wrote:
>>>> I'm not 100% sure how the system regs function under kvm.
>>>>
>>>> If they are not used at all, then we should avoid them all en masse an not
>>>> piecemeal like this.
>>>>
>>>> If they are used for something, then we should keep them registered and change
>>>> the writefn like so:
>>>>
>>>> #ifdef CONFIG_TCG
>>>> /* existing stuff */
>>>> #else
>>>> /* Handled by hardware accelerator. */
>>>> g_assert_not_reached();
>>>> #endif
>>
>> I ended with that patch because dccvap_writefn() calls probe_read()
>> which is an inlined call to probe_access(), which itself is only defined
>> when using TCG. So with KVM either linking fails or I get:
>>
>> target/arm/helper.c: In function ‘dccvap_writefn’:
>> target/arm/helper.c:6898:13: error: implicit declaration of function
>> ‘probe_read’;
>> haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
>> ^~~~~~~~~~
>
> IN this particular case, DC CVAP is really a system insn rather
> than a 'register'; our register struct for it is marked up as
> ARM_CP_NO_RAW, which means we'll effectively ignore it when
> running KVM (it will not be migrated, have its state synced
> against the kernel, or be visible in gdb). If dccvap_writefn()
> ever gets called somehow that's a bug, so having it end up
> with an assert is the right thing.
>
>> I'll use your suggestion which works for me:
>
> Your suggested patch isn't quite the same as RTH's suggestion,
> because it puts the assert inside a stub probe_read()
> implementation rather than having the ifdef at the level
> of the writefn body. I have no opinion on whether one or
> the other of these is preferable.
I'll let Richard modify the writefn() bodies if required, as he
understand what they do :)
Btw since we have this rule:
obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o
I'll use the following patch which is less intrusive:
-- >8 --
index 677191a69c..e4bbf997aa 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -22,3 +22,10 @@ void tb_flush(CPUState *cpu)
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
{
}
+
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t
retaddr)
+{
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+}
---
>
> thanks
> -- PMM
>
^ permalink raw reply related [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-04-17 14:19 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-17 14:19 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On 4/17/20 3:54 PM, Peter Maydell wrote:
> On Fri, 17 Apr 2020 at 14:49, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> On 3/16/20 9:11 PM, Peter Maydell wrote:
>>> On Mon, 16 Mar 2020 at 19:36, Richard Henderson
>>> <richard.henderson@linaro.org> wrote:
>>>> I'm not 100% sure how the system regs function under kvm.
>>>>
>>>> If they are not used at all, then we should avoid them all en masse an not
>>>> piecemeal like this.
>>>>
>>>> If they are used for something, then we should keep them registered and change
>>>> the writefn like so:
>>>>
>>>> #ifdef CONFIG_TCG
>>>> /* existing stuff */
>>>> #else
>>>> /* Handled by hardware accelerator. */
>>>> g_assert_not_reached();
>>>> #endif
>>
>> I ended with that patch because dccvap_writefn() calls probe_read()
>> which is an inlined call to probe_access(), which itself is only defined
>> when using TCG. So with KVM either linking fails or I get:
>>
>> target/arm/helper.c: In function ‘dccvap_writefn’:
>> target/arm/helper.c:6898:13: error: implicit declaration of function
>> ‘probe_read’;
>> haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
>> ^~~~~~~~~~
>
> IN this particular case, DC CVAP is really a system insn rather
> than a 'register'; our register struct for it is marked up as
> ARM_CP_NO_RAW, which means we'll effectively ignore it when
> running KVM (it will not be migrated, have its state synced
> against the kernel, or be visible in gdb). If dccvap_writefn()
> ever gets called somehow that's a bug, so having it end up
> with an assert is the right thing.
>
>> I'll use your suggestion which works for me:
>
> Your suggested patch isn't quite the same as RTH's suggestion,
> because it puts the assert inside a stub probe_read()
> implementation rather than having the ifdef at the level
> of the writefn body. I have no opinion on whether one or
> the other of these is preferable.
I'll let Richard modify the writefn() bodies if required, as he
understand what they do :)
Btw since we have this rule:
obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o
I'll use the following patch which is less intrusive:
-- >8 --
index 677191a69c..e4bbf997aa 100644
--- a/accel/stubs/tcg-stub.c
+++ b/accel/stubs/tcg-stub.c
@@ -22,3 +22,10 @@ void tb_flush(CPUState *cpu)
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
{
}
+
+void *probe_access(CPUArchState *env, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t
retaddr)
+{
+ /* Handled by hardware accelerator. */
+ g_assert_not_reached();
+}
---
>
> thanks
> -- PMM
>
^ permalink raw reply related [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
2020-04-17 14:19 ` Philippe Mathieu-Daudé
@ 2020-04-17 14:24 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-17 14:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Paolo Bonzini
On Fri, 17 Apr 2020 at 15:19, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 4/17/20 3:54 PM, Peter Maydell wrote:
> > Your suggested patch isn't quite the same as RTH's suggestion,
> > because it puts the assert inside a stub probe_read()
> > implementation rather than having the ifdef at the level
> > of the writefn body. I have no opinion on whether one or
> > the other of these is preferable.
>
> I'll let Richard modify the writefn() bodies if required, as he
> understand what they do :)
RTH is suggesting
static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value)
{
#ifdef CONFIG_TCG
entire current body of function goes here
#else
g_assert_not_reached();
#endif
}
If we take that approach then the stub probe_read() would
be pointless, so we should do one or the other, not both.
> Btw since we have this rule:
>
> obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o
>
> I'll use the following patch which is less intrusive:
This is temptingly less ifdeffery, certainly
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel
@ 2020-04-17 14:24 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-17 14:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Fri, 17 Apr 2020 at 15:19, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 4/17/20 3:54 PM, Peter Maydell wrote:
> > Your suggested patch isn't quite the same as RTH's suggestion,
> > because it puts the assert inside a stub probe_read()
> > implementation rather than having the ifdef at the level
> > of the writefn body. I have no opinion on whether one or
> > the other of these is preferable.
>
> I'll let Richard modify the writefn() bodies if required, as he
> understand what they do :)
RTH is suggesting
static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value)
{
#ifdef CONFIG_TCG
entire current body of function goes here
#else
g_assert_not_reached();
#endif
}
If we take that approach then the stub probe_read() would
be pointless, so we should do one or the other, not both.
> Btw since we have this rule:
>
> obj-$(call lnot,$(CONFIG_TCG)) += tcg-stub.o
>
> I'll use the following patch which is less intrusive:
This is temptingly less ifdeffery, certainly
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-03-17 9:09 ` Philippe Mathieu-Daudé
@ 2020-04-19 16:31 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-19 16:31 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
> On 3/16/20 9:16 PM, Richard Henderson wrote:
>> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>>> +++ b/target/arm/kvm32.c
>>> @@ -22,7 +22,7 @@
>>> #include "internals.h"
>>> #include "qemu/log.h"
>>> -static inline void set_feature(uint64_t *features, int feature)
>>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>>
>> Why, what's wrong with the existing name?
Peter suggested the rename here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
>> Plus, with patch 2, you can just remove these.
Since they don't have the same prototype, they clash:
target/arm/kvm64.c:450:20: error: conflicting types for ‘set_feature’
static inline void set_feature(uint64_t *features, int feature)
^~~~~~~~~~~
In file included from target/arm/kvm64.c:30:0:
target/arm/internals.h:30:20: note: previous definition of ‘set_feature’
was here
static inline void set_feature(CPUARMState *env, int feature)
^~~~~~~~~~~
target/arm/kvm64.c:455:20: error: conflicting types for ‘unset_feature’
static inline void unset_feature(uint64_t *features, int feature)
^~~~~~~~~~~~~
In file included from target/arm/kvm64.c:30:0:
target/arm/internals.h:35:20: note: previous definition of
‘unset_feature’ was here
static inline void unset_feature(CPUARMState *env, int feature)
^~~~~~~~~~~~~
rules.mak:69: recipe for target 'target/arm/kvm64.o' failed
make[1]: *** [target/arm/kvm64.o] Error 1
>
> The prototypes are different:
>
> void set_feature(uint64_t *features, int feature)
>
> void set_feature(CPUARMState *env, int feature)
>
> Anyway you are right, I'll use the later prototype instead, thanks.
There are ~180 uses of set_feature(CPUARMState,...) and 10 of
set_feature(uint64_t,...) (kvm32:4 kvm64:6).
We are going to remove kvm32, so replacing 180 set_feature(env) by
set_feature(env->features) seems a waste.
If you prefer to avoid renaming as kvm_set_feature() another option is
to move the declaration in a local "features.h" header that would not be
included by kvm*.c.
The main problem is the use of the ARMHostCPUFeatures structure which
apparently was introduced similar to a CPUClass (commit a96c0514ab7)
then lost this in commit c4487d76d52.
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-04-19 16:31 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-19 16:31 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
> On 3/16/20 9:16 PM, Richard Henderson wrote:
>> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>>> +++ b/target/arm/kvm32.c
>>> @@ -22,7 +22,7 @@
>>> #include "internals.h"
>>> #include "qemu/log.h"
>>> -static inline void set_feature(uint64_t *features, int feature)
>>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>>
>> Why, what's wrong with the existing name?
Peter suggested the rename here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
>> Plus, with patch 2, you can just remove these.
Since they don't have the same prototype, they clash:
target/arm/kvm64.c:450:20: error: conflicting types for ‘set_feature’
static inline void set_feature(uint64_t *features, int feature)
^~~~~~~~~~~
In file included from target/arm/kvm64.c:30:0:
target/arm/internals.h:30:20: note: previous definition of ‘set_feature’
was here
static inline void set_feature(CPUARMState *env, int feature)
^~~~~~~~~~~
target/arm/kvm64.c:455:20: error: conflicting types for ‘unset_feature’
static inline void unset_feature(uint64_t *features, int feature)
^~~~~~~~~~~~~
In file included from target/arm/kvm64.c:30:0:
target/arm/internals.h:35:20: note: previous definition of
‘unset_feature’ was here
static inline void unset_feature(CPUARMState *env, int feature)
^~~~~~~~~~~~~
rules.mak:69: recipe for target 'target/arm/kvm64.o' failed
make[1]: *** [target/arm/kvm64.o] Error 1
>
> The prototypes are different:
>
> void set_feature(uint64_t *features, int feature)
>
> void set_feature(CPUARMState *env, int feature)
>
> Anyway you are right, I'll use the later prototype instead, thanks.
There are ~180 uses of set_feature(CPUARMState,...) and 10 of
set_feature(uint64_t,...) (kvm32:4 kvm64:6).
We are going to remove kvm32, so replacing 180 set_feature(env) by
set_feature(env->features) seems a waste.
If you prefer to avoid renaming as kvm_set_feature() another option is
to move the declaration in a local "features.h" header that would not be
included by kvm*.c.
The main problem is the use of the ARMHostCPUFeatures structure which
apparently was introduced similar to a CPUClass (commit a96c0514ab7)
then lost this in commit c4487d76d52.
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-04-19 16:31 ` Philippe Mathieu-Daudé
@ 2020-04-19 19:58 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-19 19:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Paolo Bonzini
On Sun, 19 Apr 2020 at 17:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
> > On 3/16/20 9:16 PM, Richard Henderson wrote:
> >> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> >>> +++ b/target/arm/kvm32.c
> >>> @@ -22,7 +22,7 @@
> >>> #include "internals.h"
> >>> #include "qemu/log.h"
> >>> -static inline void set_feature(uint64_t *features, int feature)
> >>> +static inline void kvm_set_feature(uint64_t *features, int feature)
> >>
> >> Why, what's wrong with the existing name?
>
> Peter suggested the rename here:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
In that message I suggest that if you move the set_feature()
function to cpu.h (which is included in lots of places) then
that is too generic a name to use for it. The function of
the same name here in kvm32.c is fine, because it's
'static inline' and only visible in this file, so the bar
for naming is lower. (In fact, it's a demonstration of why
you don't want a generic name like 'set_feature' in a widely
included header file.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-04-19 19:58 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-04-19 19:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Sun, 19 Apr 2020 at 17:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
> > On 3/16/20 9:16 PM, Richard Henderson wrote:
> >> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> >>> +++ b/target/arm/kvm32.c
> >>> @@ -22,7 +22,7 @@
> >>> #include "internals.h"
> >>> #include "qemu/log.h"
> >>> -static inline void set_feature(uint64_t *features, int feature)
> >>> +static inline void kvm_set_feature(uint64_t *features, int feature)
> >>
> >> Why, what's wrong with the existing name?
>
> Peter suggested the rename here:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
In that message I suggest that if you move the set_feature()
function to cpu.h (which is included in lots of places) then
that is too generic a name to use for it. The function of
the same name here in kvm32.c is fine, because it's
'static inline' and only visible in this file, so the bar
for naming is lower. (In fact, it's a demonstration of why
you don't want a generic name like 'set_feature' in a widely
included header file.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
2020-04-19 19:58 ` Peter Maydell
@ 2020-04-20 10:44 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-20 10:44 UTC (permalink / raw)
To: Peter Maydell
Cc: Richard Henderson, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Paolo Bonzini
On 4/19/20 9:58 PM, Peter Maydell wrote:
> On Sun, 19 Apr 2020 at 17:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
>>> On 3/16/20 9:16 PM, Richard Henderson wrote:
>>>> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>>>>> +++ b/target/arm/kvm32.c
>>>>> @@ -22,7 +22,7 @@
>>>>> #include "internals.h"
>>>>> #include "qemu/log.h"
>>>>> -static inline void set_feature(uint64_t *features, int feature)
>>>>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>>>>
>>>> Why, what's wrong with the existing name?
>>
>> Peter suggested the rename here:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
>
> In that message I suggest that if you move the set_feature()
> function to cpu.h (which is included in lots of places) then
> that is too generic a name to use for it. The function of
> the same name here in kvm32.c is fine, because it's
> 'static inline' and only visible in this file, so the bar
> for naming is lower. (In fact, it's a demonstration of why
> you don't want a generic name like 'set_feature' in a widely
> included header file.)
And your suggestion is indeed obviously correct...
Apparently after 19 months rebasing this work I'm not seeing clearly.
Thanks again!
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature()
@ 2020-04-20 10:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-20 10:44 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On 4/19/20 9:58 PM, Peter Maydell wrote:
> On Sun, 19 Apr 2020 at 17:31, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> On 3/17/20 10:09 AM, Philippe Mathieu-Daudé wrote:
>>> On 3/16/20 9:16 PM, Richard Henderson wrote:
>>>> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>>>>> +++ b/target/arm/kvm32.c
>>>>> @@ -22,7 +22,7 @@
>>>>> #include "internals.h"
>>>>> #include "qemu/log.h"
>>>>> -static inline void set_feature(uint64_t *features, int feature)
>>>>> +static inline void kvm_set_feature(uint64_t *features, int feature)
>>>>
>>>> Why, what's wrong with the existing name?
>>
>> Peter suggested the rename here:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg641931.html
>
> In that message I suggest that if you move the set_feature()
> function to cpu.h (which is included in lots of places) then
> that is too generic a name to use for it. The function of
> the same name here in kvm32.c is fine, because it's
> 'static inline' and only visible in this file, so the bar
> for naming is lower. (In fact, it's a demonstration of why
> you don't want a generic name like 'set_feature' in a widely
> included header file.)
And your suggestion is indeed obviously correct...
Apparently after 19 months rebasing this work I'm not seeing clearly.
Thanks again!
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
2020-03-16 20:17 ` Richard Henderson
@ 2020-04-20 10:49 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-20 10:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:17 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> Under KVM the ARMv8.1-VHE instruction will trap.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> target/arm/helper.c | 22 ++++++++++++----------
>> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> What happened to the uses of these functions?
Sincerely I don't remember... I got this branch working again without
this patch, so I'll just drop it.
>
> r~
>
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index a5280c091b..ce6778283d 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> gt_ctl_write(env, ri, GTIMER_VIRT, value);
>> }
>>
>> -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> - uint64_t value)
>> -{
>> - ARMCPU *cpu = env_archcpu(env);
>> -
>> - trace_arm_gt_cntvoff_write(value);
>> - raw_write(env, ri, value);
>> - gt_recalc_timer(cpu, GTIMER_VIRT);
>> -}
>> -
>> static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
>> const ARMCPRegInfo *ri)
>> {
>> @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> gt_ctl_write(env, ri, timeridx, value);
>> }
>>
>> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
>> +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> + uint64_t value)
>> +{
>> + ARMCPU *cpu = env_archcpu(env);
>> +
>> + trace_arm_gt_cntvoff_write(value);
>> + raw_write(env, ri, value);
>> + gt_recalc_timer(cpu, GTIMER_VIRT);
>> +}
>> +
>> static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
>> {
>> gt_timer_reset(env, ri, GTIMER_HYP);
>> @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> {
>> gt_ctl_write(env, ri, GTIMER_HYP, value);
>> }
>> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>>
>> static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
>> {
>>
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG
@ 2020-04-20 10:49 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-20 10:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:17 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> Under KVM the ARMv8.1-VHE instruction will trap.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> target/arm/helper.c | 22 ++++++++++++----------
>> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> What happened to the uses of these functions?
Sincerely I don't remember... I got this branch working again without
this patch, so I'll just drop it.
>
> r~
>
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index a5280c091b..ce6778283d 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> gt_ctl_write(env, ri, GTIMER_VIRT, value);
>> }
>>
>> -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> - uint64_t value)
>> -{
>> - ARMCPU *cpu = env_archcpu(env);
>> -
>> - trace_arm_gt_cntvoff_write(value);
>> - raw_write(env, ri, value);
>> - gt_recalc_timer(cpu, GTIMER_VIRT);
>> -}
>> -
>> static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
>> const ARMCPRegInfo *ri)
>> {
>> @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> gt_ctl_write(env, ri, timeridx, value);
>> }
>>
>> +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
>> +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> + uint64_t value)
>> +{
>> + ARMCPU *cpu = env_archcpu(env);
>> +
>> + trace_arm_gt_cntvoff_write(value);
>> + raw_write(env, ri, value);
>> + gt_recalc_timer(cpu, GTIMER_VIRT);
>> +}
>> +
>> static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
>> {
>> gt_timer_reset(env, ri, GTIMER_HYP);
>> @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> {
>> gt_ctl_write(env, ri, GTIMER_HYP, value);
>> }
>> +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>>
>> static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
>> {
>>
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-04-23 8:36 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-23 8:36 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell
Cc: qemu-devel, Alex Bennée, kvm, Thomas Huth, qemu-arm,
Fam Zheng, Richard Henderson
On 3/16/20 5:06 PM, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
> - StrongARM (SA1100/1110)
> - OMAP1510 (TI925T)
>
I missed to explain, the point of this Kconfig granularity is on a KVM
only build, the TCG-only CPUs can't be default-selected, so most of
their devices are not pulled in.
Instead at the end the KVM-only binary only contains the devices
required to run the Cortex-A machines.
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 8b89d8c4c0..0652396296 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=y
> CONFIG_FSL_IMX31=y
> CONFIG_MUSICPAL=y
> CONFIG_MUSCA=y
> -CONFIG_CHEETAH=y
> -CONFIG_SX1=y
> CONFIG_NSERIES=y
> CONFIG_STELLARIS=y
> CONFIG_REALVIEW=y
[...]
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index e3d7e7694a..7fc0cff776 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -28,6 +28,7 @@ config ARM_VIRT
>
> config CHEETAH
> bool
> + select ARM_V4
> select OMAP
> select TSC210X
>
> @@ -242,6 +243,7 @@ config COLLIE
>
> config SX1
> bool
> + select ARM_V4
> select OMAP
>
> config VERSATILE
> diff --git a/target/arm/Kconfig b/target/arm/Kconfig
> index e68c71a6ff..0d496d318a 100644
> --- a/target/arm/Kconfig
> +++ b/target/arm/Kconfig
> @@ -1,2 +1,6 @@
> +config ARM_V4
> + depends on TCG
> + bool
> +
> config ARM_V7M
> bool
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2020-04-23 8:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-23 8:36 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm, Richard Henderson, qemu-devel,
qemu-arm, Alex Bennée
On 3/16/20 5:06 PM, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
> - StrongARM (SA1100/1110)
> - OMAP1510 (TI925T)
>
I missed to explain, the point of this Kconfig granularity is on a KVM
only build, the TCG-only CPUs can't be default-selected, so most of
their devices are not pulled in.
Instead at the end the KVM-only binary only contains the devices
required to run the Cortex-A machines.
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 8b89d8c4c0..0652396296 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=y
> CONFIG_FSL_IMX31=y
> CONFIG_MUSICPAL=y
> CONFIG_MUSCA=y
> -CONFIG_CHEETAH=y
> -CONFIG_SX1=y
> CONFIG_NSERIES=y
> CONFIG_STELLARIS=y
> CONFIG_REALVIEW=y
[...]
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index e3d7e7694a..7fc0cff776 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -28,6 +28,7 @@ config ARM_VIRT
>
> config CHEETAH
> bool
> + select ARM_V4
> select OMAP
> select TSC210X
>
> @@ -242,6 +243,7 @@ config COLLIE
>
> config SX1
> bool
> + select ARM_V4
> select OMAP
>
> config VERSATILE
> diff --git a/target/arm/Kconfig b/target/arm/Kconfig
> index e68c71a6ff..0d496d318a 100644
> --- a/target/arm/Kconfig
> +++ b/target/arm/Kconfig
> @@ -1,2 +1,6 @@
> +config ARM_V4
> + depends on TCG
> + bool
> +
> config ARM_V7M
> bool
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-03-16 20:06 ` Richard Henderson
@ 2020-09-29 18:26 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-29 18:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Alex Bennée, kvm, Thomas Huth, qemu-arm, Fam Zheng,
Paolo Bonzini, Peter Maydell
On 3/16/20 9:06 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> When building a KVM-only QEMU, the 'virt' machine is a good
>> default :)
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/arm/Kconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index d0903d8544..8e801cd15f 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -1,5 +1,6 @@
>> config ARM_VIRT
>> bool
>> + default y if KVM
>> imply PCI_DEVICES
>> imply TEST_DEVICES
>> imply VFIO_AMD_XGBE
>>
>
> Likewise SBSA_REF?
OK.
> Otherwise, what is this for?
> Did you remove ARM_VIRT from default-config/*?
This is to use custom config (and easily test by
blowing default-config/).
>
>
> r~
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-09-29 18:26 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-29 18:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, qemu-arm,
Paolo Bonzini, Alex Bennée
On 3/16/20 9:06 PM, Richard Henderson wrote:
> On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
>> When building a KVM-only QEMU, the 'virt' machine is a good
>> default :)
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/arm/Kconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index d0903d8544..8e801cd15f 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -1,5 +1,6 @@
>> config ARM_VIRT
>> bool
>> + default y if KVM
>> imply PCI_DEVICES
>> imply TEST_DEVICES
>> imply VFIO_AMD_XGBE
>>
>
> Likewise SBSA_REF?
OK.
> Otherwise, what is this for?
> Did you remove ARM_VIRT from default-config/*?
This is to use custom config (and easily test by
blowing default-config/).
>
>
> r~
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-03-16 16:06 ` Philippe Mathieu-Daudé
@ 2020-09-29 20:06 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-09-29 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini, Richard Henderson
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> When building a KVM-only QEMU, the 'virt' machine is a good
> default :)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index d0903d8544..8e801cd15f 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> imply VFIO_AMD_XGBE
What does this actually do ? Why should the choice of
accelerator affect what boards we pull in by default?
I can see why you'd want to disable boards that only
work with accelerators we don't enable, ie don't build
TCG-only boards unless CONFIG_TCG, but this is the other
way around...
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-09-29 20:06 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-09-29 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> When building a KVM-only QEMU, the 'virt' machine is a good
> default :)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index d0903d8544..8e801cd15f 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,5 +1,6 @@
> config ARM_VIRT
> bool
> + default y if KVM
> imply PCI_DEVICES
> imply TEST_DEVICES
> imply VFIO_AMD_XGBE
What does this actually do ? Why should the choice of
accelerator affect what boards we pull in by default?
I can see why you'd want to disable boards that only
work with accelerators we don't enable, ie don't build
TCG-only boards unless CONFIG_TCG, but this is the other
way around...
thanks
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-09-29 20:06 ` Peter Maydell
@ 2020-09-29 20:11 ` Peter Maydell
-1 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-09-29 20:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini, Richard Henderson
On Tue, 29 Sep 2020 at 21:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
> >
> > When building a KVM-only QEMU, the 'virt' machine is a good
> > default :)
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> > hw/arm/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> > index d0903d8544..8e801cd15f 100644
> > --- a/hw/arm/Kconfig
> > +++ b/hw/arm/Kconfig
> > @@ -1,5 +1,6 @@
> > config ARM_VIRT
> > bool
> > + default y if KVM
> > imply PCI_DEVICES
> > imply TEST_DEVICES
> > imply VFIO_AMD_XGBE
>
> What does this actually do ? Why should the choice of
> accelerator affect what boards we pull in by default?
Put another way, our current default is "build everything",
so "default y if ..." on a board is a no-op...
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-09-29 20:11 ` Peter Maydell
0 siblings, 0 replies; 122+ messages in thread
From: Peter Maydell @ 2020-09-29 20:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On Tue, 29 Sep 2020 at 21:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
> >
> > When building a KVM-only QEMU, the 'virt' machine is a good
> > default :)
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> > hw/arm/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> > index d0903d8544..8e801cd15f 100644
> > --- a/hw/arm/Kconfig
> > +++ b/hw/arm/Kconfig
> > @@ -1,5 +1,6 @@
> > config ARM_VIRT
> > bool
> > + default y if KVM
> > imply PCI_DEVICES
> > imply TEST_DEVICES
> > imply VFIO_AMD_XGBE
>
> What does this actually do ? Why should the choice of
> accelerator affect what boards we pull in by default?
Put another way, our current default is "build everything",
so "default y if ..." on a board is a no-op...
-- PMM
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-09-29 20:11 ` Peter Maydell
@ 2020-09-29 20:36 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-29 20:36 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Paolo Bonzini, Richard Henderson
On 9/29/20 10:11 PM, Peter Maydell wrote:
> On Tue, 29 Sep 2020 at 21:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>>
>>> When building a KVM-only QEMU, the 'virt' machine is a good
>>> default :)
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>> hw/arm/Kconfig | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>>> index d0903d8544..8e801cd15f 100644
>>> --- a/hw/arm/Kconfig
>>> +++ b/hw/arm/Kconfig
>>> @@ -1,5 +1,6 @@
>>> config ARM_VIRT
>>> bool
>>> + default y if KVM
>>> imply PCI_DEVICES
>>> imply TEST_DEVICES
>>> imply VFIO_AMD_XGBE
>>
>> What does this actually do ? Why should the choice of
>> accelerator affect what boards we pull in by default?
>
> Put another way, our current default is "build everything",
> so "default y if ..." on a board is a no-op...
Yes, the problem if I don't restrict to KVM, when
using the Xen accelerator odd things occur
(using configure --enable-xen --disable-tcg --disable-kvm):
Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
See
https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
We can't have the 'virt' machine automatically selected if
Xen is the only accelerator...
I'm looking for a simple way to avoid modifying the Xen code.
>
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-09-29 20:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-29 20:36 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Paolo Bonzini, Alex Bennée
On 9/29/20 10:11 PM, Peter Maydell wrote:
> On Tue, 29 Sep 2020 at 21:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>>
>>> When building a KVM-only QEMU, the 'virt' machine is a good
>>> default :)
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>> hw/arm/Kconfig | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>>> index d0903d8544..8e801cd15f 100644
>>> --- a/hw/arm/Kconfig
>>> +++ b/hw/arm/Kconfig
>>> @@ -1,5 +1,6 @@
>>> config ARM_VIRT
>>> bool
>>> + default y if KVM
>>> imply PCI_DEVICES
>>> imply TEST_DEVICES
>>> imply VFIO_AMD_XGBE
>>
>> What does this actually do ? Why should the choice of
>> accelerator affect what boards we pull in by default?
>
> Put another way, our current default is "build everything",
> so "default y if ..." on a board is a no-op...
Yes, the problem if I don't restrict to KVM, when
using the Xen accelerator odd things occur
(using configure --enable-xen --disable-tcg --disable-kvm):
Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
See
https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
We can't have the 'virt' machine automatically selected if
Xen is the only accelerator...
I'm looking for a simple way to avoid modifying the Xen code.
>
> -- PMM
>
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-09-29 20:36 ` Philippe Mathieu-Daudé
@ 2020-10-01 7:38 ` Paolo Bonzini
-1 siblings, 0 replies; 122+ messages in thread
From: Paolo Bonzini @ 2020-10-01 7:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Richard Henderson
On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
> Yes, the problem if I don't restrict to KVM, when
> using the Xen accelerator odd things occur
> (using configure --enable-xen --disable-tcg --disable-kvm):
>
> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> See
> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
default-configs/i386-softmmu.mak??
(By the way, there are duplicate Kconfig symbols between target/arm and
hw/cpu, they could/should be removed from target/arm).
Paolo
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-10-01 7:38 ` Paolo Bonzini
0 siblings, 0 replies; 122+ messages in thread
From: Paolo Bonzini @ 2020-10-01 7:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Alex Bennée
On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
> Yes, the problem if I don't restrict to KVM, when
> using the Xen accelerator odd things occur
> (using configure --enable-xen --disable-tcg --disable-kvm):
>
> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>
> See
> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
default-configs/i386-softmmu.mak??
(By the way, there are duplicate Kconfig symbols between target/arm and
hw/cpu, they could/should be removed from target/arm).
Paolo
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-10-01 7:38 ` Paolo Bonzini
@ 2020-10-01 15:05 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-01 15:05 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell
Cc: QEMU Developers, Alex Bennée, kvm-devel, Thomas Huth,
qemu-arm, Fam Zheng, Richard Henderson
On 10/1/20 9:38 AM, Paolo Bonzini wrote:
> On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
>> Yes, the problem if I don't restrict to KVM, when
>> using the Xen accelerator odd things occur
>> (using configure --enable-xen --disable-tcg --disable-kvm):
>>
>> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>
>> See
>> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>
> I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
> default-configs/i386-softmmu.mak??
No, this is when using:
config ARM_VIRT
bool
+ default y
I had the understanding devices in hw/$BASEARCH would be only
included for $ARCH, but I was wrong, any arch kconfig-include
the devices of the other archs.
I tried the following diff which doesn't build because various
devices in *non*-archdep folders use arch-specific Kconfig values:
-- >8 --
diff --git a/meson.build b/meson.build
index 9ab5d514d7..cfe19d0007 100644
--- a/meson.build
+++ b/meson.build
@@ -575,6 +575,7 @@ foreach target : target_dirs
if fs.is_file(target_kconfig)
minikconf_input += [target_kconfig]
endif
+ minikconf_input += 'hw' / config_target['TARGET_BASE_ARCH'] / 'Kconfig'
config_devices_mak = configure_file(
input: minikconf_input,
output: config_devices_mak,
diff --git a/hw/Kconfig b/hw/Kconfig
index 4de1797ffd..64c120175a 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -41,29 +41,29 @@ source vfio/Kconfig
source watchdog/Kconfig
# arch Kconfig
-source arm/Kconfig
-source alpha/Kconfig
-source avr/Kconfig
-source cris/Kconfig
-source hppa/Kconfig
-source i386/Kconfig
-source lm32/Kconfig
-source m68k/Kconfig
-source microblaze/Kconfig
-source mips/Kconfig
-source moxie/Kconfig
-source nios2/Kconfig
-source openrisc/Kconfig
-source ppc/Kconfig
-source riscv/Kconfig
-source rx/Kconfig
-source s390x/Kconfig
-source sh4/Kconfig
-source sparc/Kconfig
-source sparc64/Kconfig
-source tricore/Kconfig
-source unicore32/Kconfig
-source xtensa/Kconfig
# Symbols used by multiple targets
config TEST_DEVICES
---
>
> (By the way, there are duplicate Kconfig symbols between target/arm and
> hw/cpu, they could/should be removed from target/arm).
I'd rather define Kconfig entry where the model is, so in this case
keep them defined in hw/cpu/Kconfig and remove dup entries from
hw/arm/Kconfig (if Peter is OK with that).
>
> Paolo
>
^ permalink raw reply related [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-10-01 15:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-01 15:05 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Richard Henderson,
QEMU Developers, qemu-arm, Alex Bennée
On 10/1/20 9:38 AM, Paolo Bonzini wrote:
> On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
>> Yes, the problem if I don't restrict to KVM, when
>> using the Xen accelerator odd things occur
>> (using configure --enable-xen --disable-tcg --disable-kvm):
>>
>> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>
>> See
>> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>
> I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
> default-configs/i386-softmmu.mak??
No, this is when using:
config ARM_VIRT
bool
+ default y
I had the understanding devices in hw/$BASEARCH would be only
included for $ARCH, but I was wrong, any arch kconfig-include
the devices of the other archs.
I tried the following diff which doesn't build because various
devices in *non*-archdep folders use arch-specific Kconfig values:
-- >8 --
diff --git a/meson.build b/meson.build
index 9ab5d514d7..cfe19d0007 100644
--- a/meson.build
+++ b/meson.build
@@ -575,6 +575,7 @@ foreach target : target_dirs
if fs.is_file(target_kconfig)
minikconf_input += [target_kconfig]
endif
+ minikconf_input += 'hw' / config_target['TARGET_BASE_ARCH'] / 'Kconfig'
config_devices_mak = configure_file(
input: minikconf_input,
output: config_devices_mak,
diff --git a/hw/Kconfig b/hw/Kconfig
index 4de1797ffd..64c120175a 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -41,29 +41,29 @@ source vfio/Kconfig
source watchdog/Kconfig
# arch Kconfig
-source arm/Kconfig
-source alpha/Kconfig
-source avr/Kconfig
-source cris/Kconfig
-source hppa/Kconfig
-source i386/Kconfig
-source lm32/Kconfig
-source m68k/Kconfig
-source microblaze/Kconfig
-source mips/Kconfig
-source moxie/Kconfig
-source nios2/Kconfig
-source openrisc/Kconfig
-source ppc/Kconfig
-source riscv/Kconfig
-source rx/Kconfig
-source s390x/Kconfig
-source sh4/Kconfig
-source sparc/Kconfig
-source sparc64/Kconfig
-source tricore/Kconfig
-source unicore32/Kconfig
-source xtensa/Kconfig
# Symbols used by multiple targets
config TEST_DEVICES
---
>
> (By the way, there are duplicate Kconfig symbols between target/arm and
> hw/cpu, they could/should be removed from target/arm).
I'd rather define Kconfig entry where the model is, so in this case
keep them defined in hw/cpu/Kconfig and remove dup entries from
hw/arm/Kconfig (if Peter is OK with that).
>
> Paolo
>
^ permalink raw reply related [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-10-01 15:05 ` Philippe Mathieu-Daudé
@ 2020-10-05 9:22 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-05 9:22 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Peter Maydell, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Richard Henderson
On 10/1/20 5:05 PM, Philippe Mathieu-Daudé wrote:
> On 10/1/20 9:38 AM, Paolo Bonzini wrote:
>> On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
>>> Yes, the problem if I don't restrict to KVM, when
>>> using the Xen accelerator odd things occur
>>> (using configure --enable-xen --disable-tcg --disable-kvm):
>>>
>>> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
>>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>>
>>> See
>>> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>>
>> I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
>> default-configs/i386-softmmu.mak??
>
> No, this is when using:
>
> config ARM_VIRT
> bool
> + default y
>
> I had the understanding devices in hw/$BASEARCH would be only
> included for $ARCH, but I was wrong, any arch kconfig-include
> the devices of the other archs.
>
> I tried the following diff which doesn't build because various
> devices in *non*-archdep folders use arch-specific Kconfig values:
>
> -- >8 --
> diff --git a/meson.build b/meson.build
> index 9ab5d514d7..cfe19d0007 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -575,6 +575,7 @@ foreach target : target_dirs
> if fs.is_file(target_kconfig)
> minikconf_input += [target_kconfig]
> endif
> + minikconf_input += 'hw' / config_target['TARGET_BASE_ARCH'] / 'Kconfig'
> config_devices_mak = configure_file(
> input: minikconf_input,
> output: config_devices_mak,
> diff --git a/hw/Kconfig b/hw/Kconfig
> index 4de1797ffd..64c120175a 100644
> --- a/hw/Kconfig
> +++ b/hw/Kconfig
> @@ -41,29 +41,29 @@ source vfio/Kconfig
> source watchdog/Kconfig
>
> # arch Kconfig
> -source arm/Kconfig
> -source alpha/Kconfig
> -source avr/Kconfig
> -source cris/Kconfig
> -source hppa/Kconfig
> -source i386/Kconfig
> -source lm32/Kconfig
> -source m68k/Kconfig
> -source microblaze/Kconfig
> -source mips/Kconfig
> -source moxie/Kconfig
> -source nios2/Kconfig
> -source openrisc/Kconfig
> -source ppc/Kconfig
> -source riscv/Kconfig
> -source rx/Kconfig
> -source s390x/Kconfig
> -source sh4/Kconfig
> -source sparc/Kconfig
> -source sparc64/Kconfig
> -source tricore/Kconfig
> -source unicore32/Kconfig
> -source xtensa/Kconfig
>
> # Symbols used by multiple targets
> config TEST_DEVICES
> ---
List of arch-indep Kconfig using arch-defined selectors:
hw/acpi/Kconfig:42: depends on PC
hw/intc/Kconfig:31: depends on ARM_GIC && KVM
hw/intc/Kconfig:36: depends on OPENPIC && KVM
hw/intc/Kconfig:40: depends on POWERNV || PSERIES
hw/intc/Kconfig:49: depends on XICS && KVM
hw/intc/Kconfig:60: depends on S390_FLIC && KVM
hw/mem/Kconfig:11: depends on (PC || PSERIES || ARM_VIRT)
hw/pci-bridge/Kconfig:8: default y if Q35
hw/timer/Kconfig:14: default y if PC
hw/tpm/Kconfig:18: depends on TPM && PC
hw/tpm/Kconfig:24: depends on TPM && PSERIES
hw/vfio/Kconfig:16: depends on LINUX && S390_CCW_VIRTIO
hw/vfio/Kconfig:38: depends on LINUX && S390_CCW_VIRTIO
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-10-05 9:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 122+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-05 9:22 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm-devel,
Richard Henderson, QEMU Developers, qemu-arm, Alex Bennée
On 10/1/20 5:05 PM, Philippe Mathieu-Daudé wrote:
> On 10/1/20 9:38 AM, Paolo Bonzini wrote:
>> On 29/09/20 22:36, Philippe Mathieu-Daudé wrote:
>>> Yes, the problem if I don't restrict to KVM, when
>>> using the Xen accelerator odd things occur
>>> (using configure --enable-xen --disable-tcg --disable-kvm):
>>>
>>> Compiling C object libqemu-i386-softmmu.fa.p/hw_cpu_a15mpcore.c.o
>>> hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directory
>>>
>>> See
>>> https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions#Use_of_qemu-system-i386_on_ARM
>>
>> I don't understand. Is Xen adding CONFIG_ARM_VIRT=y to
>> default-configs/i386-softmmu.mak??
>
> No, this is when using:
>
> config ARM_VIRT
> bool
> + default y
>
> I had the understanding devices in hw/$BASEARCH would be only
> included for $ARCH, but I was wrong, any arch kconfig-include
> the devices of the other archs.
>
> I tried the following diff which doesn't build because various
> devices in *non*-archdep folders use arch-specific Kconfig values:
>
> -- >8 --
> diff --git a/meson.build b/meson.build
> index 9ab5d514d7..cfe19d0007 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -575,6 +575,7 @@ foreach target : target_dirs
> if fs.is_file(target_kconfig)
> minikconf_input += [target_kconfig]
> endif
> + minikconf_input += 'hw' / config_target['TARGET_BASE_ARCH'] / 'Kconfig'
> config_devices_mak = configure_file(
> input: minikconf_input,
> output: config_devices_mak,
> diff --git a/hw/Kconfig b/hw/Kconfig
> index 4de1797ffd..64c120175a 100644
> --- a/hw/Kconfig
> +++ b/hw/Kconfig
> @@ -41,29 +41,29 @@ source vfio/Kconfig
> source watchdog/Kconfig
>
> # arch Kconfig
> -source arm/Kconfig
> -source alpha/Kconfig
> -source avr/Kconfig
> -source cris/Kconfig
> -source hppa/Kconfig
> -source i386/Kconfig
> -source lm32/Kconfig
> -source m68k/Kconfig
> -source microblaze/Kconfig
> -source mips/Kconfig
> -source moxie/Kconfig
> -source nios2/Kconfig
> -source openrisc/Kconfig
> -source ppc/Kconfig
> -source riscv/Kconfig
> -source rx/Kconfig
> -source s390x/Kconfig
> -source sh4/Kconfig
> -source sparc/Kconfig
> -source sparc64/Kconfig
> -source tricore/Kconfig
> -source unicore32/Kconfig
> -source xtensa/Kconfig
>
> # Symbols used by multiple targets
> config TEST_DEVICES
> ---
List of arch-indep Kconfig using arch-defined selectors:
hw/acpi/Kconfig:42: depends on PC
hw/intc/Kconfig:31: depends on ARM_GIC && KVM
hw/intc/Kconfig:36: depends on OPENPIC && KVM
hw/intc/Kconfig:40: depends on POWERNV || PSERIES
hw/intc/Kconfig:49: depends on XICS && KVM
hw/intc/Kconfig:60: depends on S390_FLIC && KVM
hw/mem/Kconfig:11: depends on (PC || PSERIES || ARM_VIRT)
hw/pci-bridge/Kconfig:8: default y if Q35
hw/timer/Kconfig:14: default y if PC
hw/tpm/Kconfig:18: depends on TPM && PC
hw/tpm/Kconfig:24: depends on TPM && PSERIES
hw/vfio/Kconfig:16: depends on LINUX && S390_CCW_VIRTIO
hw/vfio/Kconfig:38: depends on LINUX && S390_CCW_VIRTIO
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
2020-10-05 9:22 ` Philippe Mathieu-Daudé
@ 2020-10-05 10:53 ` Paolo Bonzini
-1 siblings, 0 replies; 122+ messages in thread
From: Paolo Bonzini @ 2020-10-05 10:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, QEMU Developers, Alex Bennée, kvm-devel,
Thomas Huth, qemu-arm, Fam Zheng, Richard Henderson
On 05/10/20 11:22, Philippe Mathieu-Daudé wrote:
> List of arch-indep Kconfig using arch-defined selectors:
>
> hw/acpi/Kconfig:42: depends on PC
> hw/intc/Kconfig:31: depends on ARM_GIC && KVM
> hw/intc/Kconfig:36: depends on OPENPIC && KVM
> hw/intc/Kconfig:40: depends on POWERNV || PSERIES
> hw/intc/Kconfig:49: depends on XICS && KVM
> hw/intc/Kconfig:60: depends on S390_FLIC && KVM
> hw/mem/Kconfig:11: depends on (PC || PSERIES || ARM_VIRT)
> hw/pci-bridge/Kconfig:8: default y if Q35
> hw/timer/Kconfig:14: default y if PC
> hw/tpm/Kconfig:18: depends on TPM && PC
> hw/tpm/Kconfig:24: depends on TPM && PSERIES
> hw/vfio/Kconfig:16: depends on LINUX && S390_CCW_VIRTIO
> hw/vfio/Kconfig:38: depends on LINUX && S390_CCW_VIRTIO
>
I don't think that's a problem, and also I'm not sure this patch is a
good idea.
See docs/devel/kconfig.rst: "Boards default to false; they are enabled
by the ``default-configs/*.mak`` for the target they apply to".
Paolo
^ permalink raw reply [flat|nested] 122+ messages in thread
* Re: [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM
@ 2020-10-05 10:53 ` Paolo Bonzini
0 siblings, 0 replies; 122+ messages in thread
From: Paolo Bonzini @ 2020-10-05 10:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm-devel,
Richard Henderson, QEMU Developers, qemu-arm, Alex Bennée
On 05/10/20 11:22, Philippe Mathieu-Daudé wrote:
> List of arch-indep Kconfig using arch-defined selectors:
>
> hw/acpi/Kconfig:42: depends on PC
> hw/intc/Kconfig:31: depends on ARM_GIC && KVM
> hw/intc/Kconfig:36: depends on OPENPIC && KVM
> hw/intc/Kconfig:40: depends on POWERNV || PSERIES
> hw/intc/Kconfig:49: depends on XICS && KVM
> hw/intc/Kconfig:60: depends on S390_FLIC && KVM
> hw/mem/Kconfig:11: depends on (PC || PSERIES || ARM_VIRT)
> hw/pci-bridge/Kconfig:8: default y if Q35
> hw/timer/Kconfig:14: default y if PC
> hw/tpm/Kconfig:18: depends on TPM && PC
> hw/tpm/Kconfig:24: depends on TPM && PSERIES
> hw/vfio/Kconfig:16: depends on LINUX && S390_CCW_VIRTIO
> hw/vfio/Kconfig:38: depends on LINUX && S390_CCW_VIRTIO
>
I don't think that's a problem, and also I'm not sure this patch is a
good idea.
See docs/devel/kconfig.rst: "Boards default to false; they are enabled
by the ``default-configs/*.mak`` for the target they apply to".
Paolo
^ permalink raw reply [flat|nested] 122+ messages in thread
end of thread, other threads:[~2020-10-05 10:56 UTC | newest]
Thread overview: 122+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-16 16:06 [PATCH v3 00/19] Support disabling TCG on ARM (part 2) Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 01/19] target/arm: Rename KVM set_feature() as kvm_set_feature() Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:16 ` Richard Henderson
2020-03-16 20:16 ` Richard Henderson
2020-03-17 9:09 ` Philippe Mathieu-Daudé
2020-03-17 9:09 ` Philippe Mathieu-Daudé
2020-04-19 16:31 ` Philippe Mathieu-Daudé
2020-04-19 16:31 ` Philippe Mathieu-Daudé
2020-04-19 19:58 ` Peter Maydell
2020-04-19 19:58 ` Peter Maydell
2020-04-20 10:44 ` Philippe Mathieu-Daudé
2020-04-20 10:44 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 02/19] target/arm: Make set_feature() available for other files Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:36 ` Richard Henderson
2020-03-16 19:36 ` Richard Henderson
2020-03-16 20:11 ` Peter Maydell
2020-03-16 20:11 ` Peter Maydell
2020-04-17 13:49 ` Philippe Mathieu-Daudé
2020-04-17 13:49 ` Philippe Mathieu-Daudé
2020-04-17 13:54 ` Peter Maydell
2020-04-17 13:54 ` Peter Maydell
2020-04-17 14:19 ` Philippe Mathieu-Daudé
2020-04-17 14:19 ` Philippe Mathieu-Daudé
2020-04-17 14:24 ` Peter Maydell
2020-04-17 14:24 ` Peter Maydell
2020-03-16 16:06 ` [PATCH v3 04/19] target/arm: Restric the Address Translate operations " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:37 ` Richard Henderson
2020-03-16 19:37 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:17 ` Richard Henderson
2020-03-16 20:17 ` Richard Henderson
2020-04-20 10:49 ` Philippe Mathieu-Daudé
2020-04-20 10:49 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 06/19] target/arm: Move Makefile variable restricted to CONFIG_TCG Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 07/19] target/arm: Make cpu_register() available for other files Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:10 ` Richard Henderson
2020-03-16 20:10 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:46 ` Richard Henderson
2020-03-16 19:46 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/ Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:09 ` Richard Henderson
2020-03-16 20:09 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:50 ` Richard Henderson
2020-03-16 19:50 ` Richard Henderson
2020-03-16 19:51 ` Richard Henderson
2020-03-16 19:51 ` Richard Henderson
2020-04-23 8:36 ` Philippe Mathieu-Daudé
2020-04-23 8:36 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 11/19] target/arm: Restrict ARMv5 " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:52 ` Richard Henderson
2020-03-16 19:52 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 12/19] target/arm: Restrict ARMv6 " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:54 ` Richard Henderson
2020-03-16 19:54 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:55 ` Richard Henderson
2020-03-16 19:55 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:57 ` Richard Henderson
2020-03-16 19:57 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 19:59 ` Richard Henderson
2020-03-16 19:59 ` Richard Henderson
2020-03-16 16:06 ` [PATCH v3 16/19] target/arm: Do not build TCG objects when TCG is off Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 17/19] hw/arm: Automatically select the 'virt' machine on KVM Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:06 ` Richard Henderson
2020-03-16 20:06 ` Richard Henderson
2020-09-29 18:26 ` Philippe Mathieu-Daudé
2020-09-29 18:26 ` Philippe Mathieu-Daudé
2020-09-29 20:06 ` Peter Maydell
2020-09-29 20:06 ` Peter Maydell
2020-09-29 20:11 ` Peter Maydell
2020-09-29 20:11 ` Peter Maydell
2020-09-29 20:36 ` Philippe Mathieu-Daudé
2020-09-29 20:36 ` Philippe Mathieu-Daudé
2020-10-01 7:38 ` Paolo Bonzini
2020-10-01 7:38 ` Paolo Bonzini
2020-10-01 15:05 ` Philippe Mathieu-Daudé
2020-10-01 15:05 ` Philippe Mathieu-Daudé
2020-10-05 9:22 ` Philippe Mathieu-Daudé
2020-10-05 9:22 ` Philippe Mathieu-Daudé
2020-10-05 10:53 ` Paolo Bonzini
2020-10-05 10:53 ` Paolo Bonzini
2020-03-16 16:06 ` [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen Philippe Mathieu-Daudé
2020-03-16 16:06 ` [Xen-devel] " Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 17:05 ` Stefano Stabellini
2020-03-16 17:05 ` [Xen-devel] " Stefano Stabellini
2020-03-16 17:05 ` Stefano Stabellini
2020-03-16 17:11 ` Peter Maydell
2020-03-16 17:11 ` [Xen-devel] " Peter Maydell
2020-03-16 17:11 ` Peter Maydell
2020-03-16 19:00 ` Philippe Mathieu-Daudé
2020-03-16 19:00 ` [Xen-devel] " Philippe Mathieu-Daudé
2020-03-16 19:00 ` Philippe Mathieu-Daudé
2020-03-16 16:06 ` [PATCH v3 19/19] .travis.yml: Add a KVM-only Aarch64 job Philippe Mathieu-Daudé
2020-03-16 16:06 ` Philippe Mathieu-Daudé
2020-03-16 20:03 ` [PATCH v3 00/19] Support disabling TCG on ARM (part 2) no-reply
2020-03-16 20:03 ` no-reply
2020-03-16 23:10 ` no-reply
2020-03-16 23:10 ` no-reply
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