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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v2 3/4] hw/riscv: Add a riscv_is_32_bit() function
Date: Tue, 13 Oct 2020 17:17:30 -0700	[thread overview]
Message-ID: <4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1602634524.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h | 2 ++
 hw/riscv/boot.c         | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0acbd8aa6e..2975ed1a31 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -23,6 +23,8 @@
 #include "exec/cpu-defs.h"
 #include "hw/loader.h"
 
+bool riscv_is_32_bit(MachineState *machine);
+
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index fa699308a0..5dea644f47 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -40,6 +40,15 @@
 #define fw_dynamic_info_data(__val)     cpu_to_le64(__val)
 #endif
 
+bool riscv_is_32_bit(MachineState *machine)
+{
+    if (!strncmp(machine->cpu_type, "rv32", 4)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
-- 
2.28.0



WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com,
	alistair23@gmail.com
Subject: [PATCH v2 3/4] hw/riscv: Add a riscv_is_32_bit() function
Date: Tue, 13 Oct 2020 17:17:30 -0700	[thread overview]
Message-ID: <4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1602634524.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h | 2 ++
 hw/riscv/boot.c         | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0acbd8aa6e..2975ed1a31 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -23,6 +23,8 @@
 #include "exec/cpu-defs.h"
 #include "hw/loader.h"
 
+bool riscv_is_32_bit(MachineState *machine);
+
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index fa699308a0..5dea644f47 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -40,6 +40,15 @@
 #define fw_dynamic_info_data(__val)     cpu_to_le64(__val)
 #endif
 
+bool riscv_is_32_bit(MachineState *machine)
+{
+    if (!strncmp(machine->cpu_type, "rv32", 4)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
-- 
2.28.0



  parent reply	other threads:[~2020-10-14  0:33 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-14  0:17 [PATCH v2 0/4] Allow loading a no MMU kernel Alistair Francis
2020-10-14  0:17 ` Alistair Francis
2020-10-14  0:17 ` [PATCH v2 1/4] hw/riscv: sifive_u: Allow specifying the CPU Alistair Francis
2020-10-14  0:17   ` Alistair Francis
2020-10-19 23:17   ` Palmer Dabbelt
2020-10-19 23:17     ` Palmer Dabbelt
2020-10-20  3:17   ` Bin Meng
2020-10-20  3:17     ` Bin Meng
2020-10-14  0:17 ` [PATCH v2 2/4] hw/riscv: Return the end address of the loaded firmware Alistair Francis
2020-10-14  0:17   ` Alistair Francis
2020-10-19 23:17   ` Palmer Dabbelt
2020-10-19 23:17     ` Palmer Dabbelt
2020-10-20  3:17   ` Bin Meng
2020-10-20  3:17     ` Bin Meng
2020-10-14  0:17 ` Alistair Francis [this message]
2020-10-14  0:17   ` [PATCH v2 3/4] hw/riscv: Add a riscv_is_32_bit() function Alistair Francis
2020-10-19 23:17   ` Palmer Dabbelt
2020-10-19 23:17     ` Palmer Dabbelt
2020-10-20  3:17   ` Bin Meng
2020-10-20  3:17     ` Bin Meng
2020-10-14  0:17 ` [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware Alistair Francis
2020-10-14  0:17   ` Alistair Francis
2020-10-19 23:17   ` Palmer Dabbelt
2020-10-19 23:17     ` Palmer Dabbelt
2020-10-20 15:46     ` Alistair Francis
2020-10-20 15:46       ` Alistair Francis
2020-11-06  2:48       ` Palmer Dabbelt
2020-11-06  2:48         ` Palmer Dabbelt
2020-11-06  4:15         ` Anup Patel
2020-11-06  4:15           ` Anup Patel
2020-11-09 23:19           ` Alistair Francis
2020-11-09 23:19             ` Alistair Francis
2020-10-20  3:17   ` Bin Meng
2020-10-20  3:17     ` Bin Meng
2020-10-20 15:44 ` [PATCH v2 0/4] Allow loading a no MMU kernel Alistair Francis
2020-10-20 15:44   ` Alistair Francis

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