From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v2 0/4] Allow loading a no MMU kernel Date: Tue, 13 Oct 2020 17:17:22 -0700 [thread overview] Message-ID: <cover.1602634524.git.alistair.francis@wdc.com> (raw) This series allows loading a noMMU kernel using the -kernel option. Currently if using -kernel QEMU assumes you also have firmware and loads the kernel at a hardcoded offset. This series changes that so we only load the kernel at an offset if a firmware (-bios) was loaded. This series also adds a function to check if the CPU is 32-bit. This is a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build by using run time checks instead of compile time checks. We also allow the user to sepcify a CPU for the sifive_u machine. Alistair Francis (4): hw/riscv: sifive_u: Allow specifying the CPU hw/riscv: Return the end address of the loaded firmware hw/riscv: Add a riscv_is_32_bit() function hw/riscv: Load the kernel after the firmware include/hw/riscv/boot.h | 13 ++++++--- include/hw/riscv/sifive_u.h | 1 + hw/riscv/boot.c | 56 ++++++++++++++++++++++++++----------- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 3 +- hw/riscv/sifive_u.c | 28 ++++++++++++++----- hw/riscv/spike.c | 11 ++++++-- hw/riscv/virt.c | 11 ++++++-- 8 files changed, 91 insertions(+), 35 deletions(-) -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v2 0/4] Allow loading a no MMU kernel Date: Tue, 13 Oct 2020 17:17:22 -0700 [thread overview] Message-ID: <cover.1602634524.git.alistair.francis@wdc.com> (raw) This series allows loading a noMMU kernel using the -kernel option. Currently if using -kernel QEMU assumes you also have firmware and loads the kernel at a hardcoded offset. This series changes that so we only load the kernel at an offset if a firmware (-bios) was loaded. This series also adds a function to check if the CPU is 32-bit. This is a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build by using run time checks instead of compile time checks. We also allow the user to sepcify a CPU for the sifive_u machine. Alistair Francis (4): hw/riscv: sifive_u: Allow specifying the CPU hw/riscv: Return the end address of the loaded firmware hw/riscv: Add a riscv_is_32_bit() function hw/riscv: Load the kernel after the firmware include/hw/riscv/boot.h | 13 ++++++--- include/hw/riscv/sifive_u.h | 1 + hw/riscv/boot.c | 56 ++++++++++++++++++++++++++----------- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 3 +- hw/riscv/sifive_u.c | 28 ++++++++++++++----- hw/riscv/spike.c | 11 ++++++-- hw/riscv/virt.c | 11 ++++++-- 8 files changed, 91 insertions(+), 35 deletions(-) -- 2.28.0
next reply other threads:[~2020-10-14 0:30 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-14 0:17 Alistair Francis [this message] 2020-10-14 0:17 ` [PATCH v2 0/4] Allow loading a no MMU kernel Alistair Francis 2020-10-14 0:17 ` [PATCH v2 1/4] hw/riscv: sifive_u: Allow specifying the CPU Alistair Francis 2020-10-14 0:17 ` Alistair Francis 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-20 3:17 ` Bin Meng 2020-10-20 3:17 ` Bin Meng 2020-10-14 0:17 ` [PATCH v2 2/4] hw/riscv: Return the end address of the loaded firmware Alistair Francis 2020-10-14 0:17 ` Alistair Francis 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-20 3:17 ` Bin Meng 2020-10-20 3:17 ` Bin Meng 2020-10-14 0:17 ` [PATCH v2 3/4] hw/riscv: Add a riscv_is_32_bit() function Alistair Francis 2020-10-14 0:17 ` Alistair Francis 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-20 3:17 ` Bin Meng 2020-10-20 3:17 ` Bin Meng 2020-10-14 0:17 ` [PATCH v2 4/4] hw/riscv: Load the kernel after the firmware Alistair Francis 2020-10-14 0:17 ` Alistair Francis 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-19 23:17 ` Palmer Dabbelt 2020-10-20 15:46 ` Alistair Francis 2020-10-20 15:46 ` Alistair Francis 2020-11-06 2:48 ` Palmer Dabbelt 2020-11-06 2:48 ` Palmer Dabbelt 2020-11-06 4:15 ` Anup Patel 2020-11-06 4:15 ` Anup Patel 2020-11-09 23:19 ` Alistair Francis 2020-11-09 23:19 ` Alistair Francis 2020-10-20 3:17 ` Bin Meng 2020-10-20 3:17 ` Bin Meng 2020-10-20 15:44 ` [PATCH v2 0/4] Allow loading a no MMU kernel Alistair Francis 2020-10-20 15:44 ` Alistair Francis
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=cover.1602634524.git.alistair.francis@wdc.com \ --to=alistair.francis@wdc.com \ --cc=alistair23@gmail.com \ --cc=bmeng.cn@gmail.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.