* [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
@ 2020-07-25 14:50 Marek Vasut
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Marek Vasut @ 2020-07-25 14:50 UTC (permalink / raw)
To: u-boot
The PHY and the VIO regulator is populated on the SoM, move it
into the SoM DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 -------------------------
arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++
2 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
index dd98c7abee..52a77c4123 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
@@ -11,78 +11,9 @@
aliases {
serial0 = &uart4;
- ethernet0 = ðernet0;
};
chosen {
stdout-path = "serial0:115200n8";
};
-
- ethernet_vio: vioregulator {
- compatible = "regulator-fixed";
- regulator-name = "vio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rmii_pins_a>;
- pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rmii";
- max-speed = <100>;
- phy-handle = <&phy0>;
- st,eth_ref_clk_sel;
- phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy0: ethernet-phy at 1 {
- reg = <1>;
- };
- };
-};
-
-&pinctrl {
- ethernet0_rmii_pins_a: rmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <2>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
- bias-disable;
- };
- };
-
- ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
- };
- };
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index b3f4cb4515..643aec94ce 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -14,12 +14,23 @@
/ {
aliases {
eeprom0 = &eeprom0;
+ ethernet0 = ðernet0;
};
memory at c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
+
+ ethernet_vio: vioregulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&cec {
@@ -39,6 +50,28 @@
status = "okay";
};
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rmii_pins_a>;
+ pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0>;
+ st,eth_ref_clk_sel;
+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@@ -228,6 +261,42 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
+&pinctrl {
+ ethernet0_rmii_pins_a: rmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
+ };
+ };
+};
+
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board
2020-07-25 14:50 [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Marek Vasut
@ 2020-07-25 14:50 ` Marek Vasut
2020-07-28 9:09 ` Patrice CHOTARD
2020-07-28 11:14 ` Patrick DELAUNAY
2020-07-28 9:00 ` [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Patrice CHOTARD
2020-07-28 11:11 ` Patrick DELAUNAY
2 siblings, 2 replies; 8+ messages in thread
From: Marek Vasut @ 2020-07-25 14:50 UTC (permalink / raw)
To: u-boot
Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
arch/arm/dts/Makefile | 1 +
.../dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi | 6 +
arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 158 ++++++++++++++++++
3 files changed, 165 insertions(+)
create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5726156a2d..58f3cd4207 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -936,6 +936,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
+ stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcor-avenger96.dtb
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
new file mode 100644
index 0000000000..f83cfe90b8
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15xx-dhcom-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
new file mode 100644
index 0000000000..5a237a3b7b
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15xx-dhcom.dtsi"
+
+/ {
+ model = "DH Electronics STM32MP15xx DHCOM DRC02";
+ compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
+
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart8;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&gpiob {
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the STM32 UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rs485-rx-en";
+ };
+};
+
+&gpiod {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "Out1",
+ "Out2", "", "", "";
+};
+
+&gpioi {
+ gpio-line-names = "In1", "", "", "",
+ "", "", "", "",
+ "In2", "", "", "",
+ "", "", "", "";
+
+ /*
+ * NOTE: The USB Hub on the DRC02 needs a reset signal to be
+ * pulled high in order to be detected by the USB Controller.
+ * This signal should be handled by USB power sequencing in
+ * order to reset the Hub when USB bus is powered down, but
+ * so far there is no such functionality.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ eeprom at 50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c5 { /* TP7/TP8 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&sdmmc3 {
+ /*
+ * On DRC02, the SoM does not have SDIO WiFi. The pins
+ * are used for on-board microSD slot instead.
+ */
+ /delete-property/broken-cd;
+ cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ cs-gpios = <&gpioz 3 0>;
+ /* Use PIO for the display */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled"; /* Enable once there is display driver */
+ /*
+ * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
+ * also connected to the display board connector.
+ */
+};
+
+&usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart3_pins_a>;
+ status = "okay";
+};
+
+/*
+ * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
+ * however the STM32MP1 pinmux cannot map them to UART4 .
+ */
+
+&uart8 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8_pins_a>;
+ rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
--
2.27.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
@ 2020-07-28 9:09 ` Patrice CHOTARD
2020-07-28 11:14 ` Patrick DELAUNAY
1 sibling, 0 replies; 8+ messages in thread
From: Patrice CHOTARD @ 2020-07-28 9:09 UTC (permalink / raw)
To: u-boot
Hi Marek
On 7/25/20 4:50 PM, Marek Vasut wrote:
> Add DT for DH DRC02 unit, which is a universal controller device.
> The system has two ethernet ports, two CANs, RS485 and RS232, USB,
> capacitive buttons and an OLED display.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
> arch/arm/dts/Makefile | 1 +
> .../dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi | 6 +
> arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 158 ++++++++++++++++++
> 3 files changed, 165 insertions(+)
> create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
> create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 5726156a2d..58f3cd4207 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -936,6 +936,7 @@ dtb-$(CONFIG_STM32MP15x) += \
> stm32mp157c-dk2.dtb \
> stm32mp157c-ed1.dtb \
> stm32mp157c-ev1.dtb \
> + stm32mp15xx-dhcom-drc02.dtb \
> stm32mp15xx-dhcom-pdk2.dtb \
> stm32mp15xx-dhcor-avenger96.dtb
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
> new file mode 100644
> index 0000000000..f83cfe90b8
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2020 Marek Vasut <marex@denx.de>
> + */
> +
> +#include "stm32mp15xx-dhcom-u-boot.dtsi"
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> new file mode 100644
> index 0000000000..5a237a3b7b
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (C) 2020 Marek Vasut <marex@denx.de>
> + */
> +
> +#include "stm32mp15xx-dhcom.dtsi"
> +
> +/ {
> + model = "DH Electronics STM32MP15xx DHCOM DRC02";
> + compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
> +
> + aliases {
> + serial0 = &uart4;
> + serial1 = &usart3;
> + serial2 = &uart8;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&adc {
> + status = "disabled";
> +};
> +
> +&dac {
> + status = "disabled";
> +};
> +
> +&gpiob {
> + /*
> + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
> + * GPIO line, however the STM32 UART driver assumes RX happens
> + * during TX anyway and that it only controls drive enable DE
> + * line. Hence, the RX is always enabled here.
> + */
> + usb-hub {
> + gpio-hog;
> + gpios = <8 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "rs485-rx-en";
> + };
> +};
> +
> +&gpiod {
> + gpio-line-names = "", "", "", "",
> + "", "", "", "",
> + "", "", "", "Out1",
> + "Out2", "", "", "";
> +};
> +
> +&gpioi {
> + gpio-line-names = "In1", "", "", "",
> + "", "", "", "",
> + "In2", "", "", "",
> + "", "", "", "";
> +
> + /*
> + * NOTE: The USB Hub on the DRC02 needs a reset signal to be
> + * pulled high in order to be detected by the USB Controller.
> + * This signal should be handled by USB power sequencing in
> + * order to reset the Hub when USB bus is powered down, but
> + * so far there is no such functionality.
> + */
> + usb-hub {
> + gpio-hog;
> + gpios = <2 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "usb-hub-reset";
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins_a>;
> + i2c-scl-rising-time-ns = <185>;
> + i2c-scl-falling-time-ns = <20>;
> + status = "okay";
> + /* spare dmas for other usage */
> + /delete-property/dmas;
> + /delete-property/dma-names;
> + status = "okay";
> +
> + eeprom at 50 {
> + compatible = "atmel,24c04";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
> +
> +&i2c5 { /* TP7/TP8 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5_pins_a>;
> + i2c-scl-rising-time-ns = <185>;
> + i2c-scl-falling-time-ns = <20>;
> + status = "okay";
> + /* spare dmas for other usage */
> + /delete-property/dmas;
> + /delete-property/dma-names;
> +};
> +
> +&sdmmc3 {
> + /*
> + * On DRC02, the SoM does not have SDIO WiFi. The pins
> + * are used for on-board microSD slot instead.
> + */
> + /delete-property/broken-cd;
> + cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
> + disable-wp;
> +};
> +
> +&spi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_pins_a>;
> + cs-gpios = <&gpioz 3 0>;
> + /* Use PIO for the display */
> + /delete-property/dmas;
> + /delete-property/dma-names;
> + status = "disabled"; /* Enable once there is display driver */
> + /*
> + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
> + * also connected to the display board connector.
> + */
> +};
> +
> +&usart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usart3_pins_a>;
> + status = "okay";
> +};
> +
> +/*
> + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
> + * however the STM32MP1 pinmux cannot map them to UART4 .
> + */
> +
> +&uart8 { /* RS485 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart8_pins_a>;
> + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&usbh_ehci {
> + phys = <&usbphyc_port0>;
> + status = "okay";
> +};
> +
> +&usbphyc {
> + status = "okay";
> +};
> +
> +&usbphyc_port0 {
> + phy-supply = <&vdd_usb>;
> + vdda1v1-supply = <®11>;
> + vdda1v8-supply = <®18>;
> +};
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
Patrice
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
2020-07-28 9:09 ` Patrice CHOTARD
@ 2020-07-28 11:14 ` Patrick DELAUNAY
1 sibling, 0 replies; 8+ messages in thread
From: Patrick DELAUNAY @ 2020-07-28 11:14 UTC (permalink / raw)
To: u-boot
Hi Marek,
> From: Marek Vasut <marex@denx.de>
> Sent: samedi 25 juillet 2020 16:51
>
> Add DT for DH DRC02 unit, which is a universal controller device.
> The system has two ethernet ports, two CANs, RS485 and RS232, USB,
> capacitive buttons and an OLED display.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
> arch/arm/dts/Makefile | 1 +
> .../dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi | 6 +
> arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 158 ++++++++++++++++++
> 3 files changed, 165 insertions(+)
> create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi
> create mode 100644 arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Thanks
Patrick
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
2020-07-25 14:50 [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Marek Vasut
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
@ 2020-07-28 9:00 ` Patrice CHOTARD
2020-07-28 16:18 ` Patrice CHOTARD
2020-07-28 11:11 ` Patrick DELAUNAY
2 siblings, 1 reply; 8+ messages in thread
From: Patrice CHOTARD @ 2020-07-28 9:00 UTC (permalink / raw)
To: u-boot
Hi Marek
On 7/25/20 4:50 PM, Marek Vasut wrote:
> The PHY and the VIO regulator is populated on the SoM, move it
> into the SoM DT.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 -------------------------
> arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++
> 2 files changed, 69 insertions(+), 69 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> index dd98c7abee..52a77c4123 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
> @@ -11,78 +11,9 @@
>
> aliases {
> serial0 = &uart4;
> - ethernet0 = ðernet0;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> -
> - ethernet_vio: vioregulator {
> - compatible = "regulator-fixed";
> - regulator-name = "vio";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
> - regulator-always-on;
> - regulator-boot-on;
> - };
> -};
> -
> -ðernet0 {
> - status = "okay";
> - pinctrl-0 = <ðernet0_rmii_pins_a>;
> - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
> - pinctrl-names = "default", "sleep";
> - phy-mode = "rmii";
> - max-speed = <100>;
> - phy-handle = <&phy0>;
> - st,eth_ref_clk_sel;
> - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
> -
> - mdio0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "snps,dwmac-mdio";
> -
> - phy0: ethernet-phy at 1 {
> - reg = <1>;
> - };
> - };
> -};
> -
> -&pinctrl {
> - ethernet0_rmii_pins_a: rmii-0 {
> - pins1 {
> - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
> - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
> - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
> - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
> - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
> - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
> - bias-disable;
> - drive-push-pull;
> - slew-rate = <2>;
> - };
> - pins2 {
> - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
> - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
> - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
> - bias-disable;
> - };
> - };
> -
> - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
> - pins1 {
> - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
> - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
> - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
> - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
> - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
> - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
> - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
> - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
> - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
> - };
> - };
> };
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> index b3f4cb4515..643aec94ce 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> @@ -14,12 +14,23 @@
> / {
> aliases {
> eeprom0 = &eeprom0;
> + ethernet0 = ðernet0;
> };
>
> memory at c0000000 {
> device_type = "memory";
> reg = <0xC0000000 0x40000000>;
> };
> +
> + ethernet_vio: vioregulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vio";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> };
>
> &cec {
> @@ -39,6 +50,28 @@
> status = "okay";
> };
>
> +ðernet0 {
> + status = "okay";
> + pinctrl-0 = <ðernet0_rmii_pins_a>;
> + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
> + pinctrl-names = "default", "sleep";
> + phy-mode = "rmii";
> + max-speed = <100>;
> + phy-handle = <&phy0>;
> + st,eth_ref_clk_sel;
> + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
> +
> + mdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy0: ethernet-phy at 1 {
> + reg = <1>;
> + };
> + };
> +};
> +
> &i2c2 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c2_pins_a>;
> @@ -228,6 +261,42 @@
> vdd_3v3_usbfs-supply = <&vdd_usb>;
> };
>
> +&pinctrl {
> + ethernet0_rmii_pins_a: rmii-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
> + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
> + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
> + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
> + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
> + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> + pins2 {
> + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
> + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
> + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
> + bias-disable;
> + };
> + };
> +
> + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
> + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
> + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
> + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
> + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
> + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
> + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
> + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
> + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
> + };
> + };
> +};
> +
> &qspi {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Thanks
Patrice
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
2020-07-28 9:00 ` [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Patrice CHOTARD
@ 2020-07-28 16:18 ` Patrice CHOTARD
0 siblings, 0 replies; 8+ messages in thread
From: Patrice CHOTARD @ 2020-07-28 16:18 UTC (permalink / raw)
To: u-boot
On 7/28/20 11:00 AM, Patrice CHOTARD wrote:
> Hi Marek
>
> On 7/25/20 4:50 PM, Marek Vasut wrote:
>> The PHY and the VIO regulator is populated on the SoM, move it
>> into the SoM DT.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Patrice Chotard <patrice.chotard@st.com>
>> Cc: Patrick Delaunay <patrick.delaunay@st.com>
>> ---
>> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 -------------------------
>> arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++
>> 2 files changed, 69 insertions(+), 69 deletions(-)
>>
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
>> index dd98c7abee..52a77c4123 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
>> +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
>> @@ -11,78 +11,9 @@
>>
>> aliases {
>> serial0 = &uart4;
>> - ethernet0 = ðernet0;
>> };
>>
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> -
>> - ethernet_vio: vioregulator {
>> - compatible = "regulator-fixed";
>> - regulator-name = "vio";
>> - regulator-min-microvolt = <3300000>;
>> - regulator-max-microvolt = <3300000>;
>> - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
>> - regulator-always-on;
>> - regulator-boot-on;
>> - };
>> -};
>> -
>> -ðernet0 {
>> - status = "okay";
>> - pinctrl-0 = <ðernet0_rmii_pins_a>;
>> - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
>> - pinctrl-names = "default", "sleep";
>> - phy-mode = "rmii";
>> - max-speed = <100>;
>> - phy-handle = <&phy0>;
>> - st,eth_ref_clk_sel;
>> - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
>> -
>> - mdio0 {
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "snps,dwmac-mdio";
>> -
>> - phy0: ethernet-phy at 1 {
>> - reg = <1>;
>> - };
>> - };
>> -};
>> -
>> -&pinctrl {
>> - ethernet0_rmii_pins_a: rmii-0 {
>> - pins1 {
>> - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
>> - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
>> - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
>> - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
>> - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
>> - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
>> - bias-disable;
>> - drive-push-pull;
>> - slew-rate = <2>;
>> - };
>> - pins2 {
>> - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
>> - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
>> - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
>> - bias-disable;
>> - };
>> - };
>> -
>> - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
>> - pins1 {
>> - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
>> - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
>> - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
>> - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
>> - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
>> - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
>> - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
>> - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
>> - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
>> - };
>> - };
>> };
>> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
>> index b3f4cb4515..643aec94ce 100644
>> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
>> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
>> @@ -14,12 +14,23 @@
>> / {
>> aliases {
>> eeprom0 = &eeprom0;
>> + ethernet0 = ðernet0;
>> };
>>
>> memory at c0000000 {
>> device_type = "memory";
>> reg = <0xC0000000 0x40000000>;
>> };
>> +
>> + ethernet_vio: vioregulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vio";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> };
>>
>> &cec {
>> @@ -39,6 +50,28 @@
>> status = "okay";
>> };
>>
>> +ðernet0 {
>> + status = "okay";
>> + pinctrl-0 = <ðernet0_rmii_pins_a>;
>> + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
>> + pinctrl-names = "default", "sleep";
>> + phy-mode = "rmii";
>> + max-speed = <100>;
>> + phy-handle = <&phy0>;
>> + st,eth_ref_clk_sel;
>> + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
>> +
>> + mdio0 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "snps,dwmac-mdio";
>> +
>> + phy0: ethernet-phy at 1 {
>> + reg = <1>;
>> + };
>> + };
>> +};
>> +
>> &i2c2 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&i2c2_pins_a>;
>> @@ -228,6 +261,42 @@
>> vdd_3v3_usbfs-supply = <&vdd_usb>;
>> };
>>
>> +&pinctrl {
>> + ethernet0_rmii_pins_a: rmii-0 {
>> + pins1 {
>> + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
>> + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
>> + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
>> + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
>> + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
>> + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
>> + bias-disable;
>> + drive-push-pull;
>> + slew-rate = <2>;
>> + };
>> + pins2 {
>> + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
>> + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
>> + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
>> + bias-disable;
>> + };
>> + };
>> +
>> + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
>> + pins1 {
>> + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
>> + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
>> + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
>> + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
>> + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
>> + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
>> + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
>> + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
>> + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
>> + };
>> + };
>> +};
>> +
>> &qspi {
>> pinctrl-names = "default", "sleep";
>> pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
>
> Thanks
>
> Patrice
Applied to u-boot-stm/master
Thanks
Patrice
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
2020-07-25 14:50 [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Marek Vasut
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
2020-07-28 9:00 ` [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Patrice CHOTARD
@ 2020-07-28 11:11 ` Patrick DELAUNAY
2 siblings, 0 replies; 8+ messages in thread
From: Patrick DELAUNAY @ 2020-07-28 11:11 UTC (permalink / raw)
To: u-boot
Hi Marek,
> From: Marek Vasut <marex@denx.de>
> Sent: samedi 25 juillet 2020 16:51
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Patrice CHOTARD
> <patrice.chotard@st.com>; Patrick DELAUNAY <patrick.delaunay@st.com>
> Subject: [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
> Importance: High
>
> The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
> arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 69 -------------------------
> arch/arm/dts/stm32mp15xx-dhcom.dtsi | 69 +++++++++++++++++++++++++
> 2 files changed, 69 insertions(+), 69 deletions(-)
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Thanks
Patrick
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT
@ 2020-07-24 10:22 Marek Vasut
0 siblings, 0 replies; 8+ messages in thread
From: Marek Vasut @ 2020-07-24 10:22 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Alexandre Torgue, Patrice Chotard, Patrick Delaunay,
Maxime Coquelin, linux-stm32
The PHY and the VIO regulator is populated on the SoM, move it
into the SoM DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 33 -----------------
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 36 +++++++++++++++++++
2 files changed, 36 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
index 7c4bd615b311..9cf6d90fbf69 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -11,7 +11,6 @@ aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
- ethernet0 = ðernet0;
};
chosen {
@@ -33,16 +32,6 @@ display_bl: display-bl {
status = "okay";
};
- ethernet_vio: vioregulator {
- compatible = "regulator-fixed";
- regulator-name = "vio";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- };
-
gpio-keys-polled {
compatible = "gpio-keys-polled";
#size-cells = <0>;
@@ -141,28 +130,6 @@ &cec {
status = "okay";
};
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rmii_pins_a>;
- pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rmii";
- max-speed = <100>;
- phy-handle = <&phy0>;
- st,eth-ref-clk-sel;
- phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy0: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
&i2c2 { /* Header X22 */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
index ba905196fb54..d30a3c60da9b 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -9,6 +9,10 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
+ aliases {
+ ethernet0 = ðernet0;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
@@ -55,6 +59,16 @@ retram: retram@38000000 {
no-map;
};
};
+
+ ethernet_vio: vioregulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&adc {
@@ -94,6 +108,28 @@ &dts {
status = "okay";
};
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rmii_pins_a>;
+ pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0>;
+ st,eth-ref-clk-sel;
+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-07-28 16:18 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-25 14:50 [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Marek Vasut
2020-07-25 14:50 ` [PATCH 2/2] ARM: dts: stm32: Add DHSOM based DRC02 board Marek Vasut
2020-07-28 9:09 ` Patrice CHOTARD
2020-07-28 11:14 ` Patrick DELAUNAY
2020-07-28 9:00 ` [PATCH 1/2] ARM: dts: stm32: Move ethernet PHY into SoM DT Patrice CHOTARD
2020-07-28 16:18 ` Patrice CHOTARD
2020-07-28 11:11 ` Patrick DELAUNAY
-- strict thread matches above, loose matches on Subject: below --
2020-07-24 10:22 Marek Vasut
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.