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From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Jianlong Huang <jianlong.huang@starfivetech.com>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC
Date: Fri, 18 Nov 2022 15:17:26 +0800	[thread overview]
Message-ID: <4db38c2e-49b5-81fc-bfda-bef61860e411@starfivetech.com> (raw)
In-Reply-To: <20221118011108.70715-1-hal.feng@starfivetech.com>

On Fri, 18 Nov 2022 09:11:03 +0800, Hal Feng wrote:
> The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
> is split into 3 patch series. They respectively add basic clock&reset,
> pinctrl and device tree support for StarFive JH7110 SoC. These patch
> series are independent, but the Visionfive2 board can boot up successfully

Note that this patch series depends on the patch series [1].

[1] https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/

> only if all these patches series applied. This one adds basic pinctrl


WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Jianlong Huang <jianlong.huang@starfivetech.com>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC
Date: Fri, 18 Nov 2022 15:17:26 +0800	[thread overview]
Message-ID: <4db38c2e-49b5-81fc-bfda-bef61860e411@starfivetech.com> (raw)
In-Reply-To: <20221118011108.70715-1-hal.feng@starfivetech.com>

On Fri, 18 Nov 2022 09:11:03 +0800, Hal Feng wrote:
> The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1]
> is split into 3 patch series. They respectively add basic clock&reset,
> pinctrl and device tree support for StarFive JH7110 SoC. These patch
> series are independent, but the Visionfive2 board can boot up successfully

Note that this patch series depends on the patch series [1].

[1] https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/

> only if all these patches series applied. This one adds basic pinctrl


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  parent reply	other threads:[~2022-11-18  7:17 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18  1:11 [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC Hal Feng
2022-11-18  1:11 ` Hal Feng
2022-11-18  1:11 ` [PATCH v2 1/5] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Hal Feng
2022-11-18  1:11   ` Hal Feng
2022-11-21  8:38   ` Krzysztof Kozlowski
2022-11-21  8:38     ` Krzysztof Kozlowski
2022-11-21  8:39     ` Krzysztof Kozlowski
2022-11-21  8:39       ` Krzysztof Kozlowski
2022-11-28  0:48       ` Jianlong Huang
2022-11-28  0:48         ` Jianlong Huang
2022-11-28  8:32         ` Krzysztof Kozlowski
2022-11-28  8:32           ` Krzysztof Kozlowski
2022-11-29  1:47           ` Jianlong Huang
2022-11-29  1:47             ` Jianlong Huang
2022-11-29  7:49             ` Krzysztof Kozlowski
2022-11-29  7:49               ` Krzysztof Kozlowski
2022-11-29 14:46               ` Jianlong Huang
2022-11-29 14:46                 ` Jianlong Huang
2022-11-29 14:58                 ` Krzysztof Kozlowski
2022-11-29 14:58                   ` Krzysztof Kozlowski
2022-11-29 15:58                   ` Jianlong Huang
2022-11-29 15:58                     ` Jianlong Huang
2022-11-29 16:02                     ` Krzysztof Kozlowski
2022-11-29 16:02                       ` Krzysztof Kozlowski
2022-12-01  9:31                   ` Jianlong Huang
2022-12-01  9:31                     ` Jianlong Huang
2022-12-07 13:14   ` Emil Renner Berthing
2022-12-07 13:14     ` Emil Renner Berthing
2022-11-18  1:11 ` [PATCH v2 2/5] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl Hal Feng
2022-11-18  1:11   ` Hal Feng
2022-11-18  3:56   ` Rob Herring
2022-11-18  3:56     ` Rob Herring
2022-11-18  6:56     ` Hal Feng
2022-11-18  6:56       ` Hal Feng
2022-11-21  8:43   ` Krzysztof Kozlowski
2022-11-21  8:43     ` Krzysztof Kozlowski
2022-11-28  1:04     ` Jianlong Huang
2022-11-28  1:04       ` Jianlong Huang
2022-12-07 13:18       ` Emil Renner Berthing
2022-12-07 13:18         ` Emil Renner Berthing
2022-12-09  3:13   ` Icenowy Zheng
2022-12-09  3:13     ` Icenowy Zheng
2022-11-18  1:11 ` [PATCH v2 3/5] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl Hal Feng
2022-11-18  1:11   ` Hal Feng
2022-11-21  8:44   ` Krzysztof Kozlowski
2022-11-21  8:44     ` Krzysztof Kozlowski
2022-11-28  1:15     ` Jianlong Huang
2022-11-28  1:15       ` Jianlong Huang
2022-12-07 13:21       ` Emil Renner Berthing
2022-12-07 13:21         ` Emil Renner Berthing
2022-11-18  1:11 ` [PATCH v2 4/5] pinctrl: starfive: Add StarFive JH7110 sys controller driver Hal Feng
2022-11-18  1:11   ` Hal Feng
2022-12-07 13:47   ` Emil Renner Berthing
2022-12-07 13:47     ` Emil Renner Berthing
2022-11-18  1:11 ` [PATCH v2 5/5] pinctrl: starfive: Add StarFive JH7110 aon " Hal Feng
2022-11-18  1:11   ` Hal Feng
2022-11-18  7:17 ` Hal Feng [this message]
2022-11-18  7:17   ` [PATCH v2 0/5] Basic pinctrl support for StarFive JH7110 RISC-V SoC Hal Feng

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