[RFC 00/11] MIPS: ralink: adds support for ralink platform

[RFC 00/11] MIPS: ralink: adds support for ralink platform

[John Crispin]

This series adds support for the ralink SoC family. Currently RT305X type
SoC is supported. RT2880/3883 are in my local queue already but require
further testing.

John Crispin (11):
  MIPS: allow platforms to override cp0_compare_irq
  MIPS: ralink: adds include files
  MIPS: ralink: adds irq code
  MIPS: ralink: adds reset code
  MIPS: ralink: adds prom and cmdline code
  MIPS: ralink: adds clkdev code
  MIPS: ralink: adds OF code
  MIPS: ralink: adds early_printk support
  MIPS: ralink: adds support for RT305x SoC family
  MIPS: ralink: adds rt305x devicetree
  MIPS: ralink: adds Kbuild files

 arch/mips/Kbuild.platforms                      |    1 +
 arch/mips/Kconfig                               |   19 +-
 arch/mips/include/asm/mach-ralink/ralink_regs.h |   39 ++++
 arch/mips/include/asm/mach-ralink/rt305x.h      |  139 ++++++++++++++
 arch/mips/include/asm/mach-ralink/war.h         |   25 +++
 arch/mips/include/asm/time.h                    |    1 +
 arch/mips/kernel/traps.c                        |    7 +-
 arch/mips/ralink/Kconfig                        |   27 +++
 arch/mips/ralink/Makefile                       |   15 ++
 arch/mips/ralink/Platform                       |   11 ++
 arch/mips/ralink/clk.c                          |   72 +++++++
 arch/mips/ralink/common.h                       |   43 +++++
 arch/mips/ralink/dts/Makefile                   |    1 +
 arch/mips/ralink/dts/rt305x.dts                 |  156 +++++++++++++++
 arch/mips/ralink/early_printk.c                 |   43 +++++
 arch/mips/ralink/irq.c                          |  182 ++++++++++++++++++
 arch/mips/ralink/of.c                           |  105 +++++++++++
 arch/mips/ralink/prom.c                         |   69 +++++++
 arch/mips/ralink/reset.c                        |   44 +++++
 arch/mips/ralink/rt305x.c                       |  231 +++++++++++++++++++++++
 20 files changed, 1228 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h
 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
 create mode 100644 arch/mips/include/asm/mach-ralink/war.h
 create mode 100644 arch/mips/ralink/Kconfig
 create mode 100644 arch/mips/ralink/Makefile
 create mode 100644 arch/mips/ralink/Platform
 create mode 100644 arch/mips/ralink/clk.c
 create mode 100644 arch/mips/ralink/common.h
 create mode 100644 arch/mips/ralink/dts/Makefile
 create mode 100644 arch/mips/ralink/dts/rt305x.dts
 create mode 100644 arch/mips/ralink/early_printk.c
 create mode 100644 arch/mips/ralink/irq.c
 create mode 100644 arch/mips/ralink/of.c
 create mode 100644 arch/mips/ralink/prom.c
 create mode 100644 arch/mips/ralink/reset.c
 create mode 100644 arch/mips/ralink/rt305x.c

-- 
1.7.10.4

[RFC 01/11] MIPS: allow platforms to override cp0_compare_irq

[John Crispin]

Ralink SoC needs to be able to override cp0_compare_irq. We do this similar to
the way in which how cp0_compare_int can be overridden.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/time.h |    1 +
 arch/mips/kernel/traps.c     |    7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 761f2e9..c5ad468 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -51,6 +51,7 @@ extern int (*perf_irq)(void);
  * Initialize the calling CPU's compare interrupt as clockevent device
  */
 extern unsigned int __weak get_c0_compare_int(void);
+extern unsigned int __weak get_c0_compare_irq(void);
 extern int r4k_clockevent_init(void);
 
 static inline int mips_clockevent_init(void)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index cf7ac54..260d7f6 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -55,6 +55,7 @@
 #include <asm/types.h>
 #include <asm/stacktrace.h>
 #include <asm/uasm.h>
+#include <asm/time.h>
 
 extern void check_wait(void);
 extern asmlinkage void r4k_wait(void);
@@ -1616,7 +1617,11 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 	 */
 	if (cpu_has_mips_r2) {
 		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
-		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+		if (get_c0_compare_irq)
+			cp0_compare_irq = get_c0_compare_irq();
+		else
+			cp0_compare_irq =
+				(read_c0_intctl() >> INTCTLB_IPTI) & 7;
 		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
 		if (cp0_perfcount_irq == cp0_compare_irq)
 			cp0_perfcount_irq = -1;
-- 
1.7.10.4

[RFC 02/11] MIPS: ralink: adds include files

[John Crispin]

Before we start adding the platform code we add the common include files.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/ralink_regs.h |   39 ++++++++++++++++++++
 arch/mips/include/asm/mach-ralink/war.h         |   25 +++++++++++++
 arch/mips/ralink/common.h                       |   43 +++++++++++++++++++++++
 3 files changed, 107 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h
 create mode 100644 arch/mips/include/asm/mach-ralink/war.h
 create mode 100644 arch/mips/ralink/common.h

diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
new file mode 100644
index 0000000..5a508f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -0,0 +1,39 @@
+/*
+ *  Ralink SoC register definitions
+ *
+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _RALINK_REGS_H_
+#define _RALINK_REGS_H_
+
+extern __iomem void *rt_sysc_membase;
+extern __iomem void *rt_memc_membase;
+
+static inline void rt_sysc_w32(u32 val, unsigned reg)
+{
+	__raw_writel(val, rt_sysc_membase + reg);
+}
+
+static inline u32 rt_sysc_r32(unsigned reg)
+{
+	return __raw_readl(rt_sysc_membase + reg);
+}
+
+static inline void rt_memc_w32(u32 val, unsigned reg)
+{
+	__raw_writel(val, rt_memc_membase + reg);
+}
+
+static inline u32 rt_memc_r32(unsigned reg)
+{
+	return __raw_readl(rt_memc_membase + reg);
+}
+
+#endif /* _RALINK_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
new file mode 100644
index 0000000..a7b712c
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_RALINK_WAR_H
+#define __ASM_MACH_RALINK_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MACH_RALINK_WAR_H */
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
new file mode 100644
index 0000000..8c751f5
--- /dev/null
+++ b/arch/mips/ralink/common.h
@@ -0,0 +1,43 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _RALINK_COMMON_H__
+#define _RALINK_COMMON_H__
+
+#define RAMIPS_SYS_TYPE_LEN	0x100
+
+struct ralink_pinmux_grp {
+	const char *name;
+	u32 mask;
+	int gpio_first;
+	int gpio_last;
+};
+
+struct ralink_pinmux {
+	struct ralink_pinmux_grp *mode;
+	struct ralink_pinmux_grp *uart;
+	int uart_shift;
+	void (*wdt_reset)(void);
+};
+extern struct ralink_pinmux gpio_pinmux;
+
+struct ralink_soc_info {
+	unsigned char *name;
+	unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
+	unsigned char *compatible;
+};
+extern struct ralink_soc_info soc_info;
+
+extern void ralink_of_remap(void);
+
+extern void ralink_clk_init(void);
+extern void ralink_clk_add(const char *dev, unsigned long rate);
+
+extern void prom_soc_init(struct ralink_soc_info *soc_info);
+
+#endif /* _RALINK_COMMON_H__ */
-- 
1.7.10.4

[RFC 03/11] MIPS: ralink: adds irq code

[John Crispin]

All of the Ralink Wifi SoC currently supported by this series share the same
interrupt controller (INTC).

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/irq.c |  182 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 182 insertions(+)
 create mode 100644 arch/mips/ralink/irq.c

diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
new file mode 100644
index 0000000..f858d5d
--- /dev/null
+++ b/arch/mips/ralink/irq.c
@@ -0,0 +1,182 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+#include "common.h"
+
+/* INTC register offsets */
+#define INTC_REG_STATUS0	0x00
+#define INTC_REG_STATUS1	0x04
+#define INTC_REG_TYPE		0x20
+#define INTC_REG_RAW_STATUS	0x30
+#define INTC_REG_ENABLE		0x34
+#define INTC_REG_DISABLE	0x38
+
+#define INTC_INT_GLOBAL		BIT(31)
+#define INTC_IRQ_COUNT		32
+
+#define RALINK_CPU_IRQ_BASE	0
+
+#define RALINK_CPU_IRQ_INTC	(RALINK_CPU_IRQ_BASE + 2)
+#define RALINK_CPU_IRQ_FE	(RALINK_CPU_IRQ_BASE + 5)
+#define RALINK_CPU_IRQ_WIFI	(RALINK_CPU_IRQ_BASE + 6)
+#define RALINK_CPU_IRQ_COUNTER	(RALINK_CPU_IRQ_BASE + 7)
+
+/* we have a cascade of 8 irqs */
+#define MIPS_CPU_IRQ_CASCADE	8
+
+/* we have 32 SoC irqs */
+#define RALINK_INTC_IRQ_COUNT	32
+
+#define RALINK_INTC_IRQ_PERFC   (MIPS_CPU_IRQ_CASCADE + 9)
+
+static void __iomem *rt_intc_membase;
+
+static inline void rt_intc_w32(u32 val, unsigned reg)
+{
+	__raw_writel(val, rt_intc_membase + reg);
+}
+
+static inline u32 rt_intc_r32(unsigned reg)
+{
+	return __raw_readl(rt_intc_membase + reg);
+}
+
+static void ralink_intc_irq_unmask(struct irq_data *d)
+{
+	unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE;
+
+	rt_intc_w32((1 << irq), INTC_REG_ENABLE);
+}
+
+static void ralink_intc_irq_mask(struct irq_data *d)
+{
+	unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE;
+
+	rt_intc_w32((1 << irq), INTC_REG_DISABLE);
+}
+
+static struct irq_chip ralink_intc_irq_chip = {
+	.name		= "INTC",
+	.irq_unmask	= ralink_intc_irq_unmask,
+	.irq_mask	= ralink_intc_irq_mask,
+	.irq_mask_ack	= ralink_intc_irq_mask,
+};
+
+static struct irqaction ralink_intc_irqaction = {
+	.handler	= no_action,
+	.name		= "cascade [INTC]",
+};
+
+unsigned int __cpuinit get_c0_compare_irq(void)
+{
+	return CP0_LEGACY_COMPARE_IRQ;
+}
+
+void ralink_intc_dispatch(void)
+{
+	u32 pending = rt_intc_r32(INTC_REG_STATUS0);
+
+	do_IRQ((int)(__ffs(pending) + MIPS_CPU_IRQ_CASCADE));
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned long pending;
+
+	pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+	if (pending & STATUSF_IP7)
+		do_IRQ(RALINK_CPU_IRQ_COUNTER);
+
+	else if (pending & STATUSF_IP5)
+		do_IRQ(RALINK_CPU_IRQ_FE);
+
+	else if (pending & STATUSF_IP6)
+		do_IRQ(RALINK_CPU_IRQ_WIFI);
+
+	else if (pending & STATUSF_IP2)
+		ralink_intc_dispatch();
+
+	else
+		spurious_interrupt();
+}
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+	if (hw < MIPS_CPU_IRQ_CASCADE)
+		return 0;
+
+	irq_set_chip_and_handler(hw, &ralink_intc_irq_chip, handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+	.xlate = irq_domain_xlate_onetwocell,
+	.map = intc_map,
+};
+
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+
+	mips_cpu_irq_init();
+
+	if (of_address_to_resource(node, 0, &res))
+		panic("Failed to get intc memory range");
+
+	if (request_mem_region(res.start, resource_size(&res),
+				res.name) < 0)
+		pr_err("Failed to request intc memory");
+
+	rt_intc_membase = ioremap_nocache(res.start,
+					resource_size(&res));
+	if (!rt_intc_membase)
+		panic("Failed to remap intc memory");
+
+	/* disable all interrupts */
+	rt_intc_w32(~0, INTC_REG_DISABLE);
+
+	/* route all INTC interrupts to MIPS HW0 interrupt */
+	rt_intc_w32(0, INTC_REG_TYPE);
+
+	setup_irq(RALINK_CPU_IRQ_INTC, &ralink_intc_irqaction);
+
+	irq_domain_add_linear(node,
+		MIPS_CPU_IRQ_CASCADE + RALINK_INTC_IRQ_COUNT,
+		&irq_domain_ops, 0);
+
+	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
+
+	cp0_perfcount_irq = RALINK_INTC_IRQ_PERFC;
+
+	return 0;
+}
+
+static struct of_device_id __initdata of_irq_ids[] = {
+	{ .compatible = "ralink,intc", .data = intc_of_init },
+	{},
+};
+
+void __init arch_init_irq(void)
+{
+	of_irq_init(of_irq_ids);
+}
+
-- 
1.7.10.4

[RFC 04/11] MIPS: ralink: adds reset code

[John Crispin]

Resetting these SoCs requires no real magic. The code is straight forward.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/reset.c |   44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 arch/mips/ralink/reset.c

diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
new file mode 100644
index 0000000..22120e5
--- /dev/null
+++ b/arch/mips/ralink/reset.c
@@ -0,0 +1,44 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/pm.h>
+#include <linux/io.h>
+
+#include <asm/reboot.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+/* Reset Control */
+#define SYSC_REG_RESET_CTRL     0x034
+#define RSTCTL_RESET_SYSTEM     BIT(0)
+
+static void ralink_restart(char *command)
+{
+	local_irq_disable();
+	rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
+	unreachable();
+}
+
+static void ralink_halt(void)
+{
+	local_irq_disable();
+	unreachable();
+}
+
+static int __init mips_reboot_setup(void)
+{
+	_machine_restart = ralink_restart;
+	_machine_halt = ralink_halt;
+	pm_power_off = ralink_halt;
+
+	return 0;
+}
+
+arch_initcall(mips_reboot_setup);
-- 
1.7.10.4

[RFC 05/11] MIPS: ralink: adds prom and cmdline code

[John Crispin]

Add minimal code to handle commandlines.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/prom.c |   69 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 arch/mips/ralink/prom.c

diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
new file mode 100644
index 0000000..49238d3
--- /dev/null
+++ b/arch/mips/ralink/prom.c
@@ -0,0 +1,69 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include "common.h"
+
+struct ralink_soc_info soc_info;
+
+const char *get_system_type(void)
+{
+	return soc_info.sys_type;
+}
+
+static __init void prom_init_cmdline(int argc, char **argv)
+{
+	int i;
+
+	pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n",
+	       (unsigned int)fw_arg0, (unsigned int)fw_arg1,
+	       (unsigned int)fw_arg2, (unsigned int)fw_arg3);
+
+	argc = fw_arg0;
+	argv = (char **) KSEG1ADDR(fw_arg1);
+
+	if (!argv) {
+		pr_debug("argv=%p is invalid, skipping\n",
+		       argv);
+		return;
+	}
+
+	for (i = 0; i < argc; i++) {
+		char *p = (char *) KSEG1ADDR(argv[i]);
+
+		if (CPHYSADDR(p) && *p) {
+			pr_debug("argv[%d]: %s\n", i, p);
+			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+		}
+	}
+}
+
+void __init prom_init(void)
+{
+	int argc;
+	char **argv;
+
+	prom_soc_init(&soc_info);
+
+	pr_info("CPU Type: %s\n", get_system_type());
+
+	prom_init_cmdline(argc, argv);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
-- 
1.7.10.4

[RFC 06/11] MIPS: ralink: adds clkdev code

[John Crispin]

These SoCs have a limited number of fixed rate clocks. Add support for the
clk and clkdev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/clk.c |   72 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 arch/mips/ralink/clk.c

diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
new file mode 100644
index 0000000..8dfa22f
--- /dev/null
+++ b/arch/mips/ralink/clk.c
@@ -0,0 +1,72 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+
+#include "common.h"
+
+struct clk {
+	struct clk_lookup cl;
+	unsigned long rate;
+};
+
+void ralink_clk_add(const char *dev, unsigned long rate)
+{
+	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+	if (!clk)
+		panic("failed to add clock\n");
+
+	clk->cl.dev_id = dev;
+	clk->cl.clk = clk;
+
+	clk->rate = rate;
+
+	clkdev_add(&clk->cl);
+}
+
+/*
+ * Linux clock API
+ */
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+void __init plat_time_init(void)
+{
+	struct clk *clk;
+
+	ralink_of_remap();
+
+	ralink_clk_init();
+	clk = clk_get_sys("cpu", NULL);
+	if (IS_ERR(clk))
+		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
+	mips_hpt_frequency = clk_get_rate(clk) / 2;
+	clk_put(clk);
+}
-- 
1.7.10.4

[RFC 07/11] MIPS: ralink: adds OF code

[John Crispin]

Until there is a generic MIPS way of handing the DTB over from bootloader to
kernel we rely on a built in devicetrees. The OF code also remaps those register
ranges that we use global in our drivers.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/of.c |  105 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 arch/mips/ralink/of.c

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
new file mode 100644
index 0000000..02814b3
--- /dev/null
+++ b/arch/mips/ralink/of.c
@@ -0,0 +1,105 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/of_fdt.h>
+#include <linux/kernel.h>
+#include <linux/bootmem.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include <asm/reboot.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include "common.h"
+
+__iomem void *rt_sysc_membase;
+__iomem void *rt_memc_membase;
+
+extern struct boot_param_header __dtb_start;
+
+void __init ralink_of_remap(void)
+{
+	struct resource res_sysc, res_memc;
+	struct device_node *np_sysc =
+			of_find_compatible_node(NULL, NULL, "ralink,sysc");
+	struct device_node *np_memc =
+			of_find_compatible_node(NULL, NULL, "ralink,memc");
+
+	if (!np_sysc || !np_memc)
+		panic("Failed to load core nodes from devicetree");
+
+	if (of_address_to_resource(np_sysc, 0, &res_sysc) ||
+			of_address_to_resource(np_memc, 0, &res_memc))
+		panic("Failed to get core resources");
+
+	if ((request_mem_region(res_sysc.start, resource_size(&res_sysc),
+				res_sysc.name) < 0) ||
+		(request_mem_region(res_memc.start, resource_size(&res_memc),
+				res_memc.name) < 0))
+		pr_err("Failed to request core resources");
+
+	rt_sysc_membase = ioremap_nocache(res_sysc.start,
+						resource_size(&res_sysc));
+	rt_memc_membase = ioremap_nocache(res_memc.start,
+						resource_size(&res_memc));
+
+	if (!rt_sysc_membase || !rt_memc_membase)
+		panic("Failed to remap core resources");
+}
+
+void __init device_tree_init(void)
+{
+	unsigned long base, size;
+
+	if (!initial_boot_params)
+		return;
+
+	base = virt_to_phys((void *)initial_boot_params);
+	size = be32_to_cpu(initial_boot_params->totalsize);
+
+	/* Before we do anything, lets reserve the dt blob */
+	reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+
+	unflatten_device_tree();
+}
+
+void __init plat_mem_setup(void)
+{
+	set_io_port_base(KSEG1);
+
+	/*
+	 * Load the builtin devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(&__dtb_start);
+}
+
+static int __init plat_of_setup(void)
+{
+	static struct of_device_id of_ids[3];
+	int len = sizeof(of_ids[0].compatible);
+
+	if (!of_have_populated_dt())
+		panic("device tree not present");
+
+	strncpy(of_ids[0].compatible, soc_info.compatible, len);
+	strncpy(of_ids[1].compatible, "palmbus", len);
+
+	if (of_platform_populate(NULL, of_ids, NULL, NULL))
+		panic("failed to populate DT\n");
+
+	return 0;
+}
+
+arch_initcall(plat_of_setup);
-- 
1.7.10.4

[RFC 08/11] MIPS: ralink: adds early_printk support

[John Crispin]

Add the code needed to make early printk work.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/early_printk.c |   43 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 arch/mips/ralink/early_printk.c

diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
new file mode 100644
index 0000000..c610084
--- /dev/null
+++ b/arch/mips/ralink/early_printk.c
@@ -0,0 +1,43 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+#include <asm/addrspace.h>
+
+/* UART registers */
+#define EARLY_UART_BASE         0x10000c00
+
+#define UART_REG_RX             0
+#define UART_REG_TX             1
+#define UART_REG_IER            2
+#define UART_REG_IIR            3
+#define UART_REG_FCR            4
+#define UART_REG_LCR            5
+#define UART_REG_MCR            6
+#define UART_REG_LSR            7
+
+static inline void uart_w32(u32 val, unsigned reg)
+{
+	__raw_writel((val),
+		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));
+}
+
+static inline u32 uart_r32(unsigned reg)
+{
+	return __raw_readl(
+		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));
+}
+
+void prom_putchar(unsigned char ch)
+{
+	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);
+	uart_w32(UART_REG_TX, ch);
+	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);
+}
-- 
1.7.10.4

[RFC 09/11] MIPS: ralink: adds support for RT305x SoC family

[John Crispin]

Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/rt305x.h |  139 +++++++++++++++++
 arch/mips/ralink/rt305x.c                  |  231 ++++++++++++++++++++++++++++
 2 files changed, 370 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
 create mode 100644 arch/mips/ralink/rt305x.c

diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
new file mode 100644
index 0000000..7d344f2
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -0,0 +1,139 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _RT305X_REGS_H_
+#define _RT305X_REGS_H_
+
+enum rt305x_soc_type {
+	RT305X_SOC_UNKNOWN = 0,
+	RT305X_SOC_RT3050,
+	RT305X_SOC_RT3052,
+	RT305X_SOC_RT3350,
+	RT305X_SOC_RT3352,
+	RT305X_SOC_RT5350,
+};
+
+extern enum rt305x_soc_type rt305x_soc;
+
+static inline int soc_is_rt3050(void)
+{
+	return rt305x_soc == RT305X_SOC_RT3050;
+}
+
+static inline int soc_is_rt3052(void)
+{
+	return rt305x_soc == RT305X_SOC_RT3052;
+}
+
+static inline int soc_is_rt305x(void)
+{
+	return soc_is_rt3050() || soc_is_rt3052();
+}
+
+static inline int soc_is_rt3350(void)
+{
+	return rt305x_soc == RT305X_SOC_RT3350;
+}
+
+static inline int soc_is_rt3352(void)
+{
+	return rt305x_soc == RT305X_SOC_RT3352;
+}
+
+static inline int soc_is_rt5350(void)
+{
+	return rt305x_soc == RT305X_SOC_RT5350;
+}
+
+#define RT305X_SYSC_BASE		0x10000000
+
+#define SYSC_REG_CHIP_NAME0		0x00
+#define SYSC_REG_CHIP_NAME1		0x04
+#define SYSC_REG_CHIP_ID		0x0c
+#define SYSC_REG_SYSTEM_CONFIG		0x10
+
+#define RT3052_CHIP_NAME0		0x30335452
+#define RT3052_CHIP_NAME1		0x20203235
+
+#define RT3350_CHIP_NAME0		0x33335452
+#define RT3350_CHIP_NAME1		0x20203035
+
+#define RT3352_CHIP_NAME0		0x33335452
+#define RT3352_CHIP_NAME1		0x20203235
+
+#define RT5350_CHIP_NAME0		0x33355452
+#define RT5350_CHIP_NAME1		0x20203035
+
+#define CHIP_ID_ID_MASK			0xff
+#define CHIP_ID_ID_SHIFT		8
+#define CHIP_ID_REV_MASK		0xff
+
+#define RT305X_SYSCFG_CPUCLK_SHIFT		18
+#define RT305X_SYSCFG_CPUCLK_MASK		0x1
+#define RT305X_SYSCFG_CPUCLK_LOW		0x0
+#define RT305X_SYSCFG_CPUCLK_HIGH		0x1
+
+#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT	2
+#define RT305X_SYSCFG_CPUCLK_MASK		0x1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT		0x1
+
+#define RT3352_SYSCFG0_CPUCLK_SHIFT	8
+#define RT3352_SYSCFG0_CPUCLK_MASK	0x1
+#define RT3352_SYSCFG0_CPUCLK_LOW	0x0
+#define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
+
+#define RT5350_SYSCFG0_CPUCLK_SHIFT	8
+#define RT5350_SYSCFG0_CPUCLK_MASK	0x3
+#define RT5350_SYSCFG0_CPUCLK_360	0x0
+#define RT5350_SYSCFG0_CPUCLK_320	0x2
+#define RT5350_SYSCFG0_CPUCLK_300	0x3
+
+/* multi function gpio pins */
+#define RT305X_GPIO_I2C_SD		1
+#define RT305X_GPIO_I2C_SCLK		2
+#define RT305X_GPIO_SPI_EN		3
+#define RT305X_GPIO_SPI_CLK		4
+/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
+#define RT305X_GPIO_7			7
+#define RT305X_GPIO_10			10
+#define RT305X_GPIO_14			14
+#define RT305X_GPIO_UART1_TXD		15
+#define RT305X_GPIO_UART1_RXD		16
+#define RT305X_GPIO_JTAG_TDO		17
+#define RT305X_GPIO_JTAG_TDI		18
+#define RT305X_GPIO_MDIO_MDC		22
+#define RT305X_GPIO_MDIO_MDIO		23
+#define RT305X_GPIO_SDRAM_MD16		24
+#define RT305X_GPIO_SDRAM_MD31		39
+#define RT305X_GPIO_GE0_TXD0		40
+#define RT305X_GPIO_GE0_RXCLK		51
+
+#define RT305X_GPIO_MODE_I2C		BIT(0)
+#define RT305X_GPIO_MODE_SPI		BIT(1)
+#define RT305X_GPIO_MODE_UART0_SHIFT	2
+#define RT305X_GPIO_MODE_UART0_MASK	0x7
+#define RT305X_GPIO_MODE_UART0(x)	((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+#define RT305X_GPIO_MODE_UARTF		0x0
+#define RT305X_GPIO_MODE_PCM_UARTF	0x1
+#define RT305X_GPIO_MODE_PCM_I2S	0x2
+#define RT305X_GPIO_MODE_I2S_UARTF	0x3
+#define RT305X_GPIO_MODE_PCM_GPIO	0x4
+#define RT305X_GPIO_MODE_GPIO_UARTF	0x5
+#define RT305X_GPIO_MODE_GPIO_I2S	0x6
+#define RT305X_GPIO_MODE_GPIO		0x7
+#define RT305X_GPIO_MODE_UART1		BIT(5)
+#define RT305X_GPIO_MODE_JTAG		BIT(6)
+#define RT305X_GPIO_MODE_MDIO		BIT(7)
+#define RT305X_GPIO_MODE_SDRAM		BIT(8)
+#define RT305X_GPIO_MODE_RGMII		BIT(9)
+
+#endif
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
new file mode 100644
index 0000000..23ea087
--- /dev/null
+++ b/arch/mips/ralink/rt305x.c
@@ -0,0 +1,231 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mipsregs.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/rt305x.h>
+
+#include "common.h"
+
+enum rt305x_soc_type rt305x_soc;
+
+struct ralink_pinmux_grp mode_mux[] = {
+	{
+		.name = "i2c",
+		.mask = RT305X_GPIO_MODE_I2C,
+		.gpio_first = RT305X_GPIO_I2C_SD,
+		.gpio_last = RT305X_GPIO_I2C_SCLK,
+	}, {
+		.name = "spi",
+		.mask = RT305X_GPIO_MODE_SPI,
+		.gpio_first = RT305X_GPIO_SPI_EN,
+		.gpio_last = RT305X_GPIO_SPI_CLK,
+	}, {
+		.name = "uartlite",
+		.mask = RT305X_GPIO_MODE_UART1,
+		.gpio_first = RT305X_GPIO_UART1_TXD,
+		.gpio_last = RT305X_GPIO_UART1_RXD,
+	}, {
+		.name = "jtag",
+		.mask = RT305X_GPIO_MODE_JTAG,
+		.gpio_first = RT305X_GPIO_JTAG_TDO,
+		.gpio_last = RT305X_GPIO_JTAG_TDI,
+	}, {
+		.name = "mdio",
+		.mask = RT305X_GPIO_MODE_MDIO,
+		.gpio_first = RT305X_GPIO_MDIO_MDC,
+		.gpio_last = RT305X_GPIO_MDIO_MDIO,
+	}, {
+		.name = "sdram",
+		.mask = RT305X_GPIO_MODE_SDRAM,
+		.gpio_first = RT305X_GPIO_SDRAM_MD16,
+		.gpio_last = RT305X_GPIO_SDRAM_MD31,
+	}, {
+		.name = "rgmii",
+		.mask = RT305X_GPIO_MODE_RGMII,
+		.gpio_first = RT305X_GPIO_GE0_TXD0,
+		.gpio_last = RT305X_GPIO_GE0_RXCLK,
+	}, {0}
+};
+
+struct ralink_pinmux_grp uart_mux[] = {
+	{
+		.name = "uartf",
+		.mask = RT305X_GPIO_MODE_UARTF,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "pcm uartf",
+		.mask = RT305X_GPIO_MODE_PCM_UARTF,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "pcm i2s",
+		.mask = RT305X_GPIO_MODE_PCM_I2S,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "i2s uartf",
+		.mask = RT305X_GPIO_MODE_I2S_UARTF,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "pcm gio",
+		.mask = RT305X_GPIO_MODE_PCM_GPIO,
+		.gpio_first = RT305X_GPIO_10,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "gpio uartf",
+		.mask = RT305X_GPIO_MODE_GPIO_UARTF,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "gpio i2s",
+		.mask = RT305X_GPIO_MODE_GPIO_I2S,
+		.gpio_first = RT305X_GPIO_7,
+		.gpio_last = RT305X_GPIO_14,
+	}, {
+		.name = "gpio",
+		.mask = RT305X_GPIO_MODE_GPIO,
+	}, {0}
+};
+
+void rt305x_wdt_reset(void)
+{
+	u32 t;
+
+	/* enable WDT reset output on pin SRAM_CS_N */
+	t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+	t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
+		RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
+	rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
+}
+
+struct ralink_pinmux gpio_pinmux = {
+	.mode = mode_mux,
+	.uart = uart_mux,
+	.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
+	.wdt_reset = rt305x_wdt_reset,
+};
+
+void __init ralink_clk_init(void)
+{
+	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
+	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+
+	if (soc_is_rt305x() || soc_is_rt3350()) {
+		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
+		     RT305X_SYSCFG_CPUCLK_MASK;
+		switch (t) {
+		case RT305X_SYSCFG_CPUCLK_LOW:
+			cpu_rate = 320000000;
+			break;
+		case RT305X_SYSCFG_CPUCLK_HIGH:
+			cpu_rate = 384000000;
+			break;
+		}
+		sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
+	} else if (soc_is_rt3352()) {
+		t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
+		     RT3352_SYSCFG0_CPUCLK_MASK;
+		switch (t) {
+		case RT3352_SYSCFG0_CPUCLK_LOW:
+			cpu_rate = 384000000;
+			break;
+		case RT3352_SYSCFG0_CPUCLK_HIGH:
+			cpu_rate = 400000000;
+			break;
+		}
+		sys_rate = wdt_rate = cpu_rate / 3;
+		uart_rate = 40000000;
+	} else if (soc_is_rt5350()) {
+		t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
+		     RT5350_SYSCFG0_CPUCLK_MASK;
+		switch (t) {
+		case RT5350_SYSCFG0_CPUCLK_360:
+			cpu_rate = 360000000;
+			sys_rate = cpu_rate / 3;
+			break;
+		case RT5350_SYSCFG0_CPUCLK_320:
+			cpu_rate = 320000000;
+			sys_rate = cpu_rate / 4;
+			break;
+		case RT5350_SYSCFG0_CPUCLK_300:
+			cpu_rate = 300000000;
+			sys_rate = cpu_rate / 3;
+			break;
+		default:
+			BUG();
+		}
+		uart_rate = 40000000;
+		wdt_rate = sys_rate;
+	} else {
+		BUG();
+	}
+
+	ralink_clk_add("cpu", cpu_rate);
+	ralink_clk_add("10000b00.spi", sys_rate);
+	ralink_clk_add("10000100.timer", wdt_rate);
+	ralink_clk_add("10000500.uart", uart_rate);
+	ralink_clk_add("10000c00.uartlite", uart_rate);
+}
+
+void prom_soc_init(struct ralink_soc_info *soc_info)
+{
+	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+	u32 n0;
+	u32 n1;
+	u32 id;
+
+	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+
+	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
+		unsigned long icache_sets;
+
+		icache_sets = (read_c0_config1() >> 22) & 7;
+		if (icache_sets == 1) {
+			rt305x_soc = RT305X_SOC_RT3050;
+			soc_info->name = "RT3050";
+			soc_info->compatible = "ralink,rt3050";
+		} else {
+			rt305x_soc = RT305X_SOC_RT3052;
+			soc_info->name = "RT3052";
+			soc_info->compatible = "ralink,rt3052";
+		}
+	} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
+		rt305x_soc = RT305X_SOC_RT3350;
+		soc_info->name = "RT3350";
+		soc_info->compatible = "ralink,rt3250";
+	} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
+		rt305x_soc = RT305X_SOC_RT3352;
+		soc_info->name = "RT3352";
+		soc_info->compatible = "ralink,rt3352";
+	} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
+		rt305x_soc = RT305X_SOC_RT5350;
+		soc_info->name = "RT5350";
+		soc_info->compatible = "ralink,rt5350";
+	} else {
+		panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
+	}
+
+	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
+
+	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+		"Ralink %s id:%u rev:%u",
+		soc_info->name,
+		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
+		(id & CHIP_ID_REV_MASK));
+}
-- 
1.7.10.4

[RFC 10/11] MIPS: ralink: adds rt305x devicetree

[John Crispin]

This adds the devicetree file that describes the rt305x evaluation kit.

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/ralink/dts/rt305x.dts |  156 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 156 insertions(+)
 create mode 100644 arch/mips/ralink/dts/rt305x.dts

diff --git a/arch/mips/ralink/dts/rt305x.dts b/arch/mips/ralink/dts/rt305x.dts
new file mode 100644
index 0000000..6554cfd
--- /dev/null
+++ b/arch/mips/ralink/dts/rt305x.dts
@@ -0,0 +1,156 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "ralink,rt305x";
+
+	cpus {
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+		};
+	};
+
+	memory@0 {
+		reg = <0x0 0x4000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600 init=/init";
+	};
+
+	palmbus@10000000 {
+		compatible = "palmbus";
+		reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sysc@0 {
+			compatible = "ralink,sysc";
+			reg = <0x0 0x100>;
+
+			ralink,pinmmux = "uartlite", "spi";
+			ralink,uartmux = "gpio";
+			ralink,wdtmux = <0>;
+		};
+
+		timer@100 {
+			compatible = "ralink,wdt";
+			reg = <0x100 0x100>;
+		};
+
+		intc: intc@200 {
+			compatible = "ralink,intc";
+			reg = <0x200 0x100>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		memc@300 {
+			compatible = "ralink,memc";
+			reg = <0x300 0x100>;
+		};
+
+		gpio0: gpio@600 {
+			compatible = "ralink,gpio";
+			reg = <0x600 0x34>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,ngpio = <24>;
+			ralink,regs = [ 00 04 08 0c
+					20 24 28 2c
+					30 34 ];
+		};
+
+		gpio1: gpio@638 {
+			compatible = "ralink,gpio";
+			reg = <0x638 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,ngpio = <16>;
+			ralink,regs = [ 00 04 08 0c
+					10 14 18 1c
+					20 24 ];
+		};
+
+		gpio2: gpio@660 {
+			compatible = "ralink,gpio";
+			reg = <0x660 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,ngpio = <12>;
+			ralink,regs = [ 00 04 08 0c
+					10 14 18 1c
+					20 24 ];
+		};
+
+		spi@b00 {
+			compatible = "ralink,spi";
+			reg = <0xb00 0x100>;
+		};
+
+		uartlite@c00 {
+			compatible = "ns16550a";
+			reg = <0xc00 0x100>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <20>;
+
+			reg-shift = <2>;
+		};
+
+		fe@100000 {
+			compatible = "ralink,fe";
+			reg = <0x100000 0x10000>;
+		};
+
+		esw@110000 {
+			compatible = "ralink,esw";
+			reg = <0x110000 0x8000>;
+		};
+
+		dwc_otg@1c0000 {
+			compatible = "dwc_otg";
+			reg = <0x1c0000 0x40000>;
+		};
+	};
+
+	cfi@1f000000 {
+		compatible = "cfi-flash";
+		reg = <0x1f000000 0x800000>;
+
+		bank-width = <2>;
+		device-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "uboot";
+			reg = <0x0 0x30000>;
+			read-only;
+		};
+		partition@30000 {
+			label = "uboot-env";
+			reg = <0x30000 0x10000>;
+			read-only;
+		};
+		partition@40000 {
+			label = "calibration";
+			reg = <0x40000 0x10000>;
+			read-only;
+		};
+		partition@50000 {
+			label = "linux";
+			reg = <0x50000 0x7b0000>;
+		};
+	};
+};
-- 
1.7.10.4

[RFC 11/11] MIPS: ralink: adds Kbuild files

[John Crispin]

Add the Kbuild symbols and Makefiles needed to actually build the ralink code
from this series

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/Kbuild.platforms    |    1 +
 arch/mips/Kconfig             |   19 ++++++++++++++++++-
 arch/mips/ralink/Kconfig      |   27 +++++++++++++++++++++++++++
 arch/mips/ralink/Makefile     |   15 +++++++++++++++
 arch/mips/ralink/Platform     |   11 +++++++++++
 arch/mips/ralink/dts/Makefile |    1 +
 6 files changed, 73 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/ralink/Kconfig
 create mode 100644 arch/mips/ralink/Makefile
 create mode 100644 arch/mips/ralink/Platform
 create mode 100644 arch/mips/ralink/dts/Makefile

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 91b9d69..9a73ce6 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -22,6 +22,7 @@ platforms += pmc-sierra
 platforms += pnx833x
 platforms += pnx8550
 platforms += powertv
+platforms += ralink
 platforms += rb532
 platforms += sgi-ip22
 platforms += sgi-ip27
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2ac626a..89c92d3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -434,6 +434,22 @@ config POWERTV
 	help
 	  This enables support for the Cisco PowerTV Platform.
 
+config RALINK
+	bool "Ralink based machines"
+	select CEVT_R4K
+	select CSRC_R4K
+	select BOOT_RAW
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select USE_OF
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select HAVE_MACH_CLKDEV
+	select CLKDEV_LOOKUP
+
 config SGI_IP22
 	bool "SGI IP22 (Indy/Indigo2)"
 	select FW_ARC
@@ -846,6 +862,7 @@ source "arch/mips/lantiq/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
 source "arch/mips/powertv/Kconfig"
+source "arch/mips/ralink/Kconfig"
 source "arch/mips/sgi-ip27/Kconfig"
 source "arch/mips/sibyte/Kconfig"
 source "arch/mips/txx9/Kconfig"
@@ -1160,7 +1177,7 @@ config BOOT_ELF32
 
 config MIPS_L1_CACHE_SHIFT
 	int
-	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
+	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || RALINK_RT288X
 	default "6" if MIPS_CPU_SCACHE
 	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
 	default "5"
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
new file mode 100644
index 0000000..1be044c
--- /dev/null
+++ b/arch/mips/ralink/Kconfig
@@ -0,0 +1,27 @@
+if RALINK
+
+choice
+	prompt "Ralink SoC selection"
+	default SOC_RT305X
+	help
+	  Select Ralink MIPS SoC type.
+
+	config SOC_RT305X
+		bool "RT305x"
+		select USB_ARCH_HAS_OHCI
+		select USB_ARCH_HAS_EHCI
+
+endchoice
+
+choice
+	prompt "Devicetree selection"
+	default DTB_RT305X_EVAL
+	help
+	  Select the devicetree.
+
+	config DTB_RT305X_EVAL
+		bool "RT305x eval kit"
+
+endchoice
+
+endif
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
new file mode 100644
index 0000000..939757f
--- /dev/null
+++ b/arch/mips/ralink/Makefile
@@ -0,0 +1,15 @@
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 as published
+# by the Free Software Foundation.#
+# Makefile for the Ralink common stuff
+#
+# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+
+obj-y := prom.o of.o reset.o clk.o irq.o
+
+obj-$(CONFIG_SOC_RT305X) += rt305x.o
+
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+obj-y += dts/
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
new file mode 100644
index 0000000..1d7e8fb
--- /dev/null
+++ b/arch/mips/ralink/Platform
@@ -0,0 +1,11 @@
+#
+# Ralink SoC common stuff
+#
+core-$(CONFIG_RALINK)     += arch/mips/ralink/
+cflags-$(CONFIG_RALINK)   += -I$(srctree)/arch/mips/include/asm/mach-ralink
+
+#
+# Ralink RT305x
+#
+cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
+load-$(CONFIG_SOC_RT305X)   += 0xffffffff80000000
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
new file mode 100644
index 0000000..e2ce7b4
--- /dev/null
+++ b/arch/mips/ralink/dts/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DTB_RT305X_EVAL) := rt305x.dtb.o
-- 
1.7.10.4

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Florian Fainelli]

Hey John,

Le 23/01/2013 13:05, John Crispin a écrit :
> Add the code needed to make early printk work.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>   arch/mips/ralink/early_printk.c |   43 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 43 insertions(+)
>   create mode 100644 arch/mips/ralink/early_printk.c
>
> diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
> new file mode 100644
> index 0000000..c610084
> --- /dev/null
> +++ b/arch/mips/ralink/early_printk.c
> @@ -0,0 +1,43 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/serial_reg.h>
> +
> +#include <asm/addrspace.h>
> +
> +/* UART registers */
> +#define EARLY_UART_BASE         0x10000c00
> +
> +#define UART_REG_RX             0
> +#define UART_REG_TX             1
> +#define UART_REG_IER            2
> +#define UART_REG_IIR            3
> +#define UART_REG_FCR            4
> +#define UART_REG_LCR            5
> +#define UART_REG_MCR            6
> +#define UART_REG_LSR            7

Is that really required considering that you already include 
serial_reg.h and could use defines from there?

At some point I think that we might be able to come up with a some kind 
of generic 8250 earlyprintk code where people just tell what's the base 
address of their UART. Something like:

#define UART_BASE	KSEG1ADDR(MY_UART_BASE)
#include <asm/8250-earlyprintk.h>

> +
> +static inline void uart_w32(u32 val, unsigned reg)
> +{
> +	__raw_writel((val),
> +		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));
> +}
> +
> +static inline u32 uart_r32(unsigned reg)
> +{
> +	return __raw_readl(
> +		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));
> +}
> +
> +void prom_putchar(unsigned char ch)
> +{
> +	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);
> +	uart_w32(UART_REG_TX, ch);
> +	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);
> +}
>

Re: [RFC 00/11] MIPS: ralink: adds support for ralink platform

[Florian Fainelli]

Hey John,

Le 23/01/2013 13:05, John Crispin a écrit :
> This series adds support for the ralink SoC family. Currently RT305X type
> SoC is supported. RT2880/3883 are in my local queue already but require
> further testing.

This looks very good, and the diffstat is looking good too. Besides the 
lack of Device Tree bindings documentation for the bindings you add, I 
don't have particular comments. Maybe Gabor should be CC'd on these 
patches so he gets a chance to speak loud if he objects?

Thanks!

>
> John Crispin (11):
>    MIPS: allow platforms to override cp0_compare_irq
>    MIPS: ralink: adds include files
>    MIPS: ralink: adds irq code
>    MIPS: ralink: adds reset code
>    MIPS: ralink: adds prom and cmdline code
>    MIPS: ralink: adds clkdev code
>    MIPS: ralink: adds OF code
>    MIPS: ralink: adds early_printk support
>    MIPS: ralink: adds support for RT305x SoC family
>    MIPS: ralink: adds rt305x devicetree
>    MIPS: ralink: adds Kbuild files
>
>   arch/mips/Kbuild.platforms                      |    1 +
>   arch/mips/Kconfig                               |   19 +-
>   arch/mips/include/asm/mach-ralink/ralink_regs.h |   39 ++++
>   arch/mips/include/asm/mach-ralink/rt305x.h      |  139 ++++++++++++++
>   arch/mips/include/asm/mach-ralink/war.h         |   25 +++
>   arch/mips/include/asm/time.h                    |    1 +
>   arch/mips/kernel/traps.c                        |    7 +-
>   arch/mips/ralink/Kconfig                        |   27 +++
>   arch/mips/ralink/Makefile                       |   15 ++
>   arch/mips/ralink/Platform                       |   11 ++
>   arch/mips/ralink/clk.c                          |   72 +++++++
>   arch/mips/ralink/common.h                       |   43 +++++
>   arch/mips/ralink/dts/Makefile                   |    1 +
>   arch/mips/ralink/dts/rt305x.dts                 |  156 +++++++++++++++
>   arch/mips/ralink/early_printk.c                 |   43 +++++
>   arch/mips/ralink/irq.c                          |  182 ++++++++++++++++++
>   arch/mips/ralink/of.c                           |  105 +++++++++++
>   arch/mips/ralink/prom.c                         |   69 +++++++
>   arch/mips/ralink/reset.c                        |   44 +++++
>   arch/mips/ralink/rt305x.c                       |  231 +++++++++++++++++++++++
>   20 files changed, 1228 insertions(+), 2 deletions(-)
>   create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h
>   create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
>   create mode 100644 arch/mips/include/asm/mach-ralink/war.h
>   create mode 100644 arch/mips/ralink/Kconfig
>   create mode 100644 arch/mips/ralink/Makefile
>   create mode 100644 arch/mips/ralink/Platform
>   create mode 100644 arch/mips/ralink/clk.c
>   create mode 100644 arch/mips/ralink/common.h
>   create mode 100644 arch/mips/ralink/dts/Makefile
>   create mode 100644 arch/mips/ralink/dts/rt305x.dts
>   create mode 100644 arch/mips/ralink/early_printk.c
>   create mode 100644 arch/mips/ralink/irq.c
>   create mode 100644 arch/mips/ralink/of.c
>   create mode 100644 arch/mips/ralink/prom.c
>   create mode 100644 arch/mips/ralink/reset.c
>   create mode 100644 arch/mips/ralink/rt305x.c
>

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Sergei Shtylyov]

Hello.

On 23-01-2013 23:23, Florian Fainelli wrote:

>> Add the code needed to make early printk work.

>> Signed-off-by: John Crispin <blogic@openwrt.org>
>> ---
>>   arch/mips/ralink/early_printk.c |   43
>> +++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 43 insertions(+)
>>   create mode 100644 arch/mips/ralink/early_printk.c

>> diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
>> new file mode 100644
>> index 0000000..c610084
>> --- /dev/null
>> +++ b/arch/mips/ralink/early_printk.c
>> @@ -0,0 +1,43 @@
>> +/*
>> + *  This program is free software; you can redistribute it and/or modify it
>> + *  under the terms of the GNU General Public License version 2 as published
>> + *  by the Free Software Foundation.
>> + *
>> + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/serial_reg.h>
>> +
>> +#include <asm/addrspace.h>
>> +
>> +/* UART registers */
>> +#define EARLY_UART_BASE         0x10000c00
>> +
>> +#define UART_REG_RX             0
>> +#define UART_REG_TX             1
>> +#define UART_REG_IER            2
>> +#define UART_REG_IIR            3
>> +#define UART_REG_FCR            4
>> +#define UART_REG_LCR            5
>> +#define UART_REG_MCR            6
>> +#define UART_REG_LSR            7

> Is that really required considering that you already include serial_reg.h and
> could use defines from there?

    Off the top of my head, these #define's are not quite compatible with 
standard 8250 registers.

WBR, Sergei

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Sergei Shtylyov]

Hello.

On 23-01-2013 16:05, John Crispin wrote:

> Add the code needed to make early printk work.

> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>   arch/mips/ralink/early_printk.c |   43 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 43 insertions(+)
>   create mode 100644 arch/mips/ralink/early_printk.c

> diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
> new file mode 100644
> index 0000000..c610084
> --- /dev/null
> +++ b/arch/mips/ralink/early_printk.c
> @@ -0,0 +1,43 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/serial_reg.h>

    BTW, I don't see that file in the current Linus' tree... and in linux-next 
too.

WBR, Sergei

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[John Crispin]

On 23/01/13 23:15, Sergei Shtylyov wrote:
> Hello.
>
> On 23-01-2013 16:05, John Crispin wrote:
>
>> Add the code needed to make early printk work.
>
>> Signed-off-by: John Crispin <blogic@openwrt.org>
>> ---
>> arch/mips/ralink/early_printk.c | 43
>> +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 43 insertions(+)
>> create mode 100644 arch/mips/ralink/early_printk.c
>
>> diff --git a/arch/mips/ralink/early_printk.c
>> b/arch/mips/ralink/early_printk.c
>> new file mode 100644
>> index 0000000..c610084
>> --- /dev/null
>> +++ b/arch/mips/ralink/early_printk.c
>> @@ -0,0 +1,43 @@
>> +/*
>> + * This program is free software; you can redistribute it and/or
>> modify it
>> + * under the terms of the GNU General Public License version 2 as
>> published
>> + * by the Free Software Foundation.
>> + *
>> + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/serial_reg.h>
>
> BTW, I don't see that file in the current Linus' tree... and in
> linux-next too.
>
> WBR, Sergei
>
>
>
Hi,

./include/uapi/linux/serial_reg.h

if i recall correctly they differ to the defaults. all the defines were 
added as reference even if only a few are used. i will have a closer 
look at this today

	John

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[John Crispin]

Hi,

inside <linux/serial_reg.h> we have

#define UART_LSR        5       /* In:  Line Status Register */

while our driver needs

+#define UART_REG_LCR            5

we still inlcude the file because we use

#define UART_LSR_THRE           0x20 /* Transmit-hold-register empty */


to make the real tty work we also need this patch (which i will send to 
the tty people today, i guess the AU stuff needs to be renamed

http://git.linux-mips.org/?p=john/linux-john.git;a=commit;h=ad22b1d6987cb703b42db5bdd92feaceb62be961

and for reference there is also this patch to make the whole thing 
loadable from OF.
http://git.linux-mips.org/?p=john/linux-john.git;a=commit;h=bdfab6083da584ac74dddf442de7c7d044aa3c9b

	John

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[John Crispin]

brainfart ... its too early :-)


> while our driver needs
>
> +#define UART_REG_LCR 5
>
should read ....

#define UART_REG_LSR            7

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Florian Fainelli]

On 01/24/2013 08:25 AM, John Crispin wrote:
> brainfart ... its too early :-)
>
>
>> while our driver needs
>>
>> +#define UART_REG_LCR 5
>>
> should read ....
>
> #define UART_REG_LSR            7

Ok, I did not see the registers have different offsets compared to a 
traditional 8250 UART, makes sense then.
--
Florian

Re: [RFC 01/11] MIPS: allow platforms to override cp0_compare_irq

[John Crispin]

> Maybe we should use Felix's patch [1] to fix this. That seems simpler as it uses
> the existing 'get_c0_compare_int' function. Also it covers mips_r1 CPUs as well.
> I did not test that on Ralink SoCs though.
>
> -Gabor
>
> 1.
> https://dev.openwrt.org/browser/trunk/target/linux/atheros/patches-3.3/001-get_c0_compare_int_fix.patch
>

ok, i will test it on the eval board today ...

     John

Re: [RFC 02/11] MIPS: ralink: adds include files

[Gabor Juhos]

Hi John,

> Before we start adding the platform code we add the common include files.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/include/asm/mach-ralink/ralink_regs.h |   39 ++++++++++++++++++++
>  arch/mips/include/asm/mach-ralink/war.h         |   25 +++++++++++++
>  arch/mips/ralink/common.h                       |   43 +++++++++++++++++++++++
>  3 files changed, 107 insertions(+)
>  create mode 100644 arch/mips/include/asm/mach-ralink/ralink_regs.h
>  create mode 100644 arch/mips/include/asm/mach-ralink/war.h
>  create mode 100644 arch/mips/ralink/common.h

I prefer to introduce header files along with the code which uses that actually.
Several things are defined in 'common.h' and everyone have to look into the
subseqent patches for the actual code.

<...>

> diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
> new file mode 100644
> index 0000000..8c751f5
> --- /dev/null
> +++ b/arch/mips/ralink/common.h
> @@ -0,0 +1,43 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
> + */
> +
> +#ifndef _RALINK_COMMON_H__
> +#define _RALINK_COMMON_H__
> +
> +#define RAMIPS_SYS_TYPE_LEN	0x100

256 bytes are too much for this IMHO. In OpenWrt we are using 64, but even 32
should be enough for every SoC.

-Gabor

Re: [RFC 03/11] MIPS: ralink: adds irq code

[Gabor Juhos]

Hi John,

> All of the Ralink Wifi SoC currently supported by this series share the same
> interrupt controller (INTC).
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/irq.c |  182 ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 182 insertions(+)
>  create mode 100644 arch/mips/ralink/irq.c
> 
> diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
> new file mode 100644
> index 0000000..f858d5d
> --- /dev/null
> +++ b/arch/mips/ralink/irq.c
> @@ -0,0 +1,182 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + *
> + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/bitops.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/interrupt.h>
> +
> +#include <asm/irq_cpu.h>
> +#include <asm/mipsregs.h>
> +
> +#include "common.h"
> +
> +/* INTC register offsets */
> +#define INTC_REG_STATUS0	0x00
> +#define INTC_REG_STATUS1	0x04
> +#define INTC_REG_TYPE		0x20
> +#define INTC_REG_RAW_STATUS	0x30
> +#define INTC_REG_ENABLE		0x34
> +#define INTC_REG_DISABLE	0x38
> +
> +#define INTC_INT_GLOBAL		BIT(31)
> +#define INTC_IRQ_COUNT		32
> +
> +#define RALINK_CPU_IRQ_BASE	0
> +
> +#define RALINK_CPU_IRQ_INTC	(RALINK_CPU_IRQ_BASE + 2)
> +#define RALINK_CPU_IRQ_FE	(RALINK_CPU_IRQ_BASE + 5)
> +#define RALINK_CPU_IRQ_WIFI	(RALINK_CPU_IRQ_BASE + 6)
> +#define RALINK_CPU_IRQ_COUNTER	(RALINK_CPU_IRQ_BASE + 7)

It would be better to use MIPS_CPU_IRQ_BASE instead of introducing a separate
constant. Or assign MIPS_CPU_IRQ_BASE to RALINK_CPU_IRQ_BASE at least.

> +
> +/* we have a cascade of 8 irqs */
> +#define MIPS_CPU_IRQ_CASCADE	8

The code uses this as a base number for the IRQs routed through the INTC
controller. So I would call this to RALINK_INTC_IRQ_BASE.

> +
> +/* we have 32 SoC irqs */
> +#define RALINK_INTC_IRQ_COUNT	32
> +
> +#define RALINK_INTC_IRQ_PERFC   (MIPS_CPU_IRQ_CASCADE + 9)
> +
> +static void __iomem *rt_intc_membase;
> +
> +static inline void rt_intc_w32(u32 val, unsigned reg)
> +{
> +	__raw_writel(val, rt_intc_membase + reg);
> +}
> +
> +static inline u32 rt_intc_r32(unsigned reg)
> +{
> +	return __raw_readl(rt_intc_membase + reg);
> +}
> +
> +static void ralink_intc_irq_unmask(struct irq_data *d)
> +{
> +	unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE;

Because you are using irqdomains, you should use the hw_irq field of irq_data to
get the bit offset.

> +
> +	rt_intc_w32((1 << irq), INTC_REG_ENABLE);
> +}
> +
> +static void ralink_intc_irq_mask(struct irq_data *d)
> +{
> +	unsigned int irq = d->irq - MIPS_CPU_IRQ_CASCADE;
> +
> +	rt_intc_w32((1 << irq), INTC_REG_DISABLE);
> +}
> +
> +static struct irq_chip ralink_intc_irq_chip = {
> +	.name		= "INTC",
> +	.irq_unmask	= ralink_intc_irq_unmask,
> +	.irq_mask	= ralink_intc_irq_mask,
> +	.irq_mask_ack	= ralink_intc_irq_mask,
> +};
> +
> +static struct irqaction ralink_intc_irqaction = {
> +	.handler	= no_action,
> +	.name		= "cascade [INTC]",
> +};

It would be simpler to use 'irq_set_chained_handler' instead of 'irq_setup' in
'intc_of_init'. In that way you would not have to use a custom irq_action.

> +
> +unsigned int __cpuinit get_c0_compare_irq(void)
> +{
> +	return CP0_LEGACY_COMPARE_IRQ;
> +}
> +
> +void ralink_intc_dispatch(void)
> +{
> +	u32 pending = rt_intc_r32(INTC_REG_STATUS0);
> +
> +	do_IRQ((int)(__ffs(pending) + MIPS_CPU_IRQ_CASCADE));

You have to check that 'pending' is not zero before passing that to '__ffs',
because the result of '__ffs(x)' is not defined if 'x' is zero.

> +}
> +
> +asmlinkage void plat_irq_dispatch(void)
> +{
> +	unsigned long pending;
> +
> +	pending = read_c0_status() & read_c0_cause() & ST0_IM;
> +
> +	if (pending & STATUSF_IP7)
> +		do_IRQ(RALINK_CPU_IRQ_COUNTER);
> +
> +	else if (pending & STATUSF_IP5)
> +		do_IRQ(RALINK_CPU_IRQ_FE);
> +
> +	else if (pending & STATUSF_IP6)
> +		do_IRQ(RALINK_CPU_IRQ_WIFI);
> +
> +	else if (pending & STATUSF_IP2)
> +		ralink_intc_dispatch();
> +
> +	else
> +		spurious_interrupt();
> +}
> +
> +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
> +{
> +	if (hw < MIPS_CPU_IRQ_CASCADE)
> +		return 0;

The INTC controller can handle 32 IRQs, so the hardware IRQ numbers within the
0..31 range are valid. With this code, the hardware IRQ numbers from the 0..7
range can't be mapped.

> +
> +	irq_set_chip_and_handler(hw, &ralink_intc_irq_chip, handle_level_irq);
> +
> +	return 0;
> +}
> +
> +static const struct irq_domain_ops irq_domain_ops = {
> +	.xlate = irq_domain_xlate_onetwocell,

This should be either 'irq_domain_xlate_onecell' or 'irq_domain_xlate_twocell'.

Here is the note from linux/irq/irqdomain.c:

 * Note: don't use this function unless your interrupt controller explicitly
 * supports both one and two cell bindings.  For the majority of controllers
 * the _onecell() or _twocell() variants above should be used.

> +	.map = intc_map,
> +};
> +
> +int __init intc_of_init(struct device_node *node, struct device_node *parent)
> +{
> +	struct resource res;
> +
> +	mips_cpu_irq_init();
> +
> +	if (of_address_to_resource(node, 0, &res))
> +		panic("Failed to get intc memory range");
> +
> +	if (request_mem_region(res.start, resource_size(&res),
> +				res.name) < 0)
> +		pr_err("Failed to request intc memory");
> +
> +	rt_intc_membase = ioremap_nocache(res.start,
> +					resource_size(&res));
> +	if (!rt_intc_membase)
> +		panic("Failed to remap intc memory");
> +
> +	/* disable all interrupts */
> +	rt_intc_w32(~0, INTC_REG_DISABLE);
> +
> +	/* route all INTC interrupts to MIPS HW0 interrupt */
> +	rt_intc_w32(0, INTC_REG_TYPE);
> +
> +	setup_irq(RALINK_CPU_IRQ_INTC, &ralink_intc_irqaction);
> +
> +	irq_domain_add_linear(node,
> +		MIPS_CPU_IRQ_CASCADE + RALINK_INTC_IRQ_COUNT,
> +		&irq_domain_ops, 0);
> +
> +	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
> +
> +	cp0_perfcount_irq = RALINK_INTC_IRQ_PERFC;
> +
> +	return 0;
> +}
> +
> +static struct of_device_id __initdata of_irq_ids[] = {
> +	{ .compatible = "ralink,intc", .data = intc_of_init },
> +	{},
> +};
> +
> +void __init arch_init_irq(void)
> +{
> +	of_irq_init(of_irq_ids);
> +}
> +
> 

Re: [RFC 05/11] MIPS: ralink: adds prom and cmdline code

[Gabor Juhos]

Hi John,

> Add minimal code to handle commandlines.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/prom.c |   69 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 arch/mips/ralink/prom.c
> 
> diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
> new file mode 100644
> index 0000000..49238d3

<...>

> +void __init prom_init(void)
> +{
> +	int argc;
> +	char **argv;
> +
> +	prom_soc_init(&soc_info);
> +
> +	pr_info("CPU Type: %s\n", get_system_type());

Strictly speaking, this prints the SoC type, so the prefix should be changed.
The CPU revision and its type is already printed by the generic MIPS code.

-Gabor

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Sergei Shtylyov]

Hello.

On 24-01-2013 10:57, John Crispin wrote:

>>> Add the code needed to make early printk work.

>>> Signed-off-by: John Crispin <blogic@openwrt.org>
>>> ---
>>> arch/mips/ralink/early_printk.c | 43
>>> +++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 43 insertions(+)
>>> create mode 100644 arch/mips/ralink/early_printk.c

>>> diff --git a/arch/mips/ralink/early_printk.c
>>> b/arch/mips/ralink/early_printk.c
>>> new file mode 100644
>>> index 0000000..c610084
>>> --- /dev/null
>>> +++ b/arch/mips/ralink/early_printk.c
>>> @@ -0,0 +1,43 @@
>>> +/*
>>> + * This program is free software; you can redistribute it and/or
>>> modify it
>>> + * under the terms of the GNU General Public License version 2 as
>>> published
>>> + * by the Free Software Foundation.
>>> + *
>>> + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
>>> + */
>>> +
>>> +#include <linux/io.h>
>>> +#include <linux/serial_reg.h>

>> BTW, I don't see that file in the current Linus' tree... and in
>> linux-next too.

> Hi,

> ./include/uapi/linux/serial_reg.h

    Ah, didn't know include/uapi/ is in the #include search patch now.

>      John

WBR, Sergei

Re: [RFC 08/11] MIPS: ralink: adds early_printk support

[Gabor Juhos]

2013.01.23. 13:05 keltezéssel, John Crispin írta:
> Add the code needed to make early printk work.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/early_printk.c |   43 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 arch/mips/ralink/early_printk.c
> 
> diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
> new file mode 100644
> index 0000000..c610084
> --- /dev/null
> +++ b/arch/mips/ralink/early_printk.c
> @@ -0,0 +1,43 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/serial_reg.h>
> +
> +#include <asm/addrspace.h>
> +
> +/* UART registers */
> +#define EARLY_UART_BASE         0x10000c00
> +
> +#define UART_REG_RX             0
> +#define UART_REG_TX             1
> +#define UART_REG_IER            2
> +#define UART_REG_IIR            3
> +#define UART_REG_FCR            4
> +#define UART_REG_LCR            5
> +#define UART_REG_MCR            6
> +#define UART_REG_LSR            7
> +
> +static inline void uart_w32(u32 val, unsigned reg)
> +{
> +	__raw_writel((val),
> +		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));

Introducing a variable for the base address would make the code much more
readable. Additionaly, compared to the OpenWrt code this is not a macro anymore,
so the parentheses around 'val' and 'reg' are not needed.

> +}
> +
> +static inline u32 uart_r32(unsigned reg)
> +{
> +	return __raw_readl(
> +		(void __iomem *)(KSEG1ADDR(EARLY_UART_BASE) + 4 * (reg)));

Ditto.

> +}
> +
> +void prom_putchar(unsigned char ch)
> +{
> +	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);
> +	uart_w32(UART_REG_TX, ch);
> +	while (((uart_r32(UART_REG_LSR)) & UART_LSR_THRE) == 0);

There are some superfluous parentheses inside the conditions of the while
statements. Apart from that, the trailing semicolons will cause checkpatch errors.

-Gabor

-Gabor

Re: [RFC 09/11] MIPS: ralink: adds support for RT305x SoC family

[Gabor Juhos]

2013.01.23. 13:05 keltezéssel, John Crispin írta:
> Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.
> 
> The code detects the SoC and registers the clk / pinmux settings.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/include/asm/mach-ralink/rt305x.h |  139 +++++++++++++++++
>  arch/mips/ralink/rt305x.c                  |  231 ++++++++++++++++++++++++++++
>  2 files changed, 370 insertions(+)
>  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
>  create mode 100644 arch/mips/ralink/rt305x.c

<...>

> diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
> new file mode 100644
> index 0000000..23ea087
> --- /dev/null
> +++ b/arch/mips/ralink/rt305x.c
> @@ -0,0 +1,231 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + *
> + * Parts of this file are based on Ralink's 2.6.21 BSP
> + *
> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

It seems that you forgot to add your copyright notice here.

> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +
> +#include <asm/mipsregs.h>
> +#include <asm/mach-ralink/ralink_regs.h>
> +#include <asm/mach-ralink/rt305x.h>
> +
> +#include "common.h"
> +
> +enum rt305x_soc_type rt305x_soc;
> +
> +struct ralink_pinmux_grp mode_mux[] = {
> +	{
> +		.name = "i2c",
> +		.mask = RT305X_GPIO_MODE_I2C,
> +		.gpio_first = RT305X_GPIO_I2C_SD,
> +		.gpio_last = RT305X_GPIO_I2C_SCLK,
> +	}, {
> +		.name = "spi",
> +		.mask = RT305X_GPIO_MODE_SPI,
> +		.gpio_first = RT305X_GPIO_SPI_EN,
> +		.gpio_last = RT305X_GPIO_SPI_CLK,
> +	}, {
> +		.name = "uartlite",
> +		.mask = RT305X_GPIO_MODE_UART1,
> +		.gpio_first = RT305X_GPIO_UART1_TXD,
> +		.gpio_last = RT305X_GPIO_UART1_RXD,
> +	}, {
> +		.name = "jtag",
> +		.mask = RT305X_GPIO_MODE_JTAG,
> +		.gpio_first = RT305X_GPIO_JTAG_TDO,
> +		.gpio_last = RT305X_GPIO_JTAG_TDI,
> +	}, {
> +		.name = "mdio",
> +		.mask = RT305X_GPIO_MODE_MDIO,
> +		.gpio_first = RT305X_GPIO_MDIO_MDC,
> +		.gpio_last = RT305X_GPIO_MDIO_MDIO,
> +	}, {
> +		.name = "sdram",
> +		.mask = RT305X_GPIO_MODE_SDRAM,
> +		.gpio_first = RT305X_GPIO_SDRAM_MD16,
> +		.gpio_last = RT305X_GPIO_SDRAM_MD31,
> +	}, {
> +		.name = "rgmii",
> +		.mask = RT305X_GPIO_MODE_RGMII,
> +		.gpio_first = RT305X_GPIO_GE0_TXD0,
> +		.gpio_last = RT305X_GPIO_GE0_RXCLK,
> +	}, {0}
> +};
> +
> +struct ralink_pinmux_grp uart_mux[] = {
> +	{
> +		.name = "uartf",
> +		.mask = RT305X_GPIO_MODE_UARTF,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "pcm uartf",
> +		.mask = RT305X_GPIO_MODE_PCM_UARTF,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "pcm i2s",
> +		.mask = RT305X_GPIO_MODE_PCM_I2S,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "i2s uartf",
> +		.mask = RT305X_GPIO_MODE_I2S_UARTF,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "pcm gio",

s/gio/gpio/

> +		.mask = RT305X_GPIO_MODE_PCM_GPIO,
> +		.gpio_first = RT305X_GPIO_10,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "gpio uartf",
> +		.mask = RT305X_GPIO_MODE_GPIO_UARTF,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "gpio i2s",
> +		.mask = RT305X_GPIO_MODE_GPIO_I2S,
> +		.gpio_first = RT305X_GPIO_7,
> +		.gpio_last = RT305X_GPIO_14,
> +	}, {
> +		.name = "gpio",
> +		.mask = RT305X_GPIO_MODE_GPIO,
> +	}, {0}
> +};
> +

<...>

> +
> +void prom_soc_init(struct ralink_soc_info *soc_info)
> +{
> +	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
> +	u32 n0;
> +	u32 n1;
> +	u32 id;
> +
> +	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
> +	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
> +
> +	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
> +		unsigned long icache_sets;
> +
> +		icache_sets = (read_c0_config1() >> 22) & 7;
> +		if (icache_sets == 1) {
> +			rt305x_soc = RT305X_SOC_RT3050;
> +			soc_info->name = "RT3050";
> +			soc_info->compatible = "ralink,rt3050";
> +		} else {
> +			rt305x_soc = RT305X_SOC_RT3052;
> +			soc_info->name = "RT3052";
> +			soc_info->compatible = "ralink,rt3052";
> +		}
> +	} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
> +		rt305x_soc = RT305X_SOC_RT3350;
> +		soc_info->name = "RT3350";
> +		soc_info->compatible = "ralink,rt3250";

I guess that the compatible strig should be "ralink,rt3350"?

> +	} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
> +		rt305x_soc = RT305X_SOC_RT3352;
> +		soc_info->name = "RT3352";
> +		soc_info->compatible = "ralink,rt3352";
> +	} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
> +		rt305x_soc = RT305X_SOC_RT5350;
> +		soc_info->name = "RT5350";
> +		soc_info->compatible = "ralink,rt5350";
> +	} else {
> +		panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
> +	}
> +
> +	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
> +
> +	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
> +		"Ralink %s id:%u rev:%u",
> +		soc_info->name,

I might be wrong, but it seems that the soc_info->name field is only used by
this code. If that is the case, it should be removed from the structure and you
can use a local variable here instead.

> +		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
> +		(id & CHIP_ID_REV_MASK));
> +}
> 

-Gabor

Re: [RFC 07/11] MIPS: ralink: adds OF code

[Gabor Juhos]

2013.01.23. 13:05 keltezéssel, John Crispin írta:
> Until there is a generic MIPS way of handing the DTB over from bootloader to
> kernel we rely on a built in devicetrees. The OF code also remaps those register
> ranges that we use global in our drivers.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/of.c |  105 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 105 insertions(+)
>  create mode 100644 arch/mips/ralink/of.c
> 
> diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
> new file mode 100644
> index 0000000..02814b3
> --- /dev/null
> +++ b/arch/mips/ralink/of.c
> @@ -0,0 +1,105 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + *
> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
> + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/init.h>
> +#include <linux/of_fdt.h>
> +#include <linux/kernel.h>
> +#include <linux/bootmem.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +
> +#include <asm/reboot.h>
> +#include <asm/bootinfo.h>
> +#include <asm/addrspace.h>
> +
> +#include "common.h"
> +
> +__iomem void *rt_sysc_membase;
> +__iomem void *rt_memc_membase;
> +
> +extern struct boot_param_header __dtb_start;
> +
> +void __init ralink_of_remap(void)
> +{
> +	struct resource res_sysc, res_memc;
> +	struct device_node *np_sysc =
> +			of_find_compatible_node(NULL, NULL, "ralink,sysc");
> +	struct device_node *np_memc =
> +			of_find_compatible_node(NULL, NULL, "ralink,memc");

If you would initialize these variables after the declaration part, you would
not have to break the lines.

> +
> +	if (!np_sysc || !np_memc)
> +		panic("Failed to load core nodes from devicetree");
> +
> +	if (of_address_to_resource(np_sysc, 0, &res_sysc) ||
> +			of_address_to_resource(np_memc, 0, &res_memc))
> +		panic("Failed to get core resources");
> +
> +	if ((request_mem_region(res_sysc.start, resource_size(&res_sysc),
> +				res_sysc.name) < 0) ||
> +		(request_mem_region(res_memc.start, resource_size(&res_memc),
> +				res_memc.name) < 0))
> +		pr_err("Failed to request core resources");

This also should be a panic to make it consistent with the others.

> +
> +	rt_sysc_membase = ioremap_nocache(res_sysc.start,
> +						resource_size(&res_sysc));
> +	rt_memc_membase = ioremap_nocache(res_memc.start,
> +						resource_size(&res_memc));
> +
> +	if (!rt_sysc_membase || !rt_memc_membase)
> +		panic("Failed to remap core resources");

It would worth it to introduce a helper routine which gets the node name and
returns with the remapped address. Then the helper should be used both for the
sysc and for memc nodes. That would make the code more readable and it would
reduce stack usage as well.

-Gabor

Re: [RFC 10/11] MIPS: ralink: adds rt305x devicetree

[Gabor Juhos]

2013.01.23. 13:05 keltezéssel, John Crispin írta:
> This adds the devicetree file that describes the rt305x evaluation kit.
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
>  arch/mips/ralink/dts/rt305x.dts |  156 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 156 insertions(+)
>  create mode 100644 arch/mips/ralink/dts/rt305x.dts
> 
> diff --git a/arch/mips/ralink/dts/rt305x.dts b/arch/mips/ralink/dts/rt305x.dts
> new file mode 100644
> index 0000000..6554cfd
> --- /dev/null
> +++ b/arch/mips/ralink/dts/rt305x.dts
> @@ -0,0 +1,156 @@
> +/dts-v1/;
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "ralink,rt305x";
> +
> +	cpus {
> +		cpu@0 {
> +			compatible = "mips,mips24KEc";
> +		};
> +	};
> +
> +	memory@0 {
> +		reg = <0x0 0x4000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,57600 init=/init";
> +	};
> +
> +	palmbus@10000000 {
> +		compatible = "palmbus";
> +		reg = <0x10000000 0x200000>;
> +                ranges = <0x0 0x10000000 0x1FFFFF>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		sysc@0 {
> +			compatible = "ralink,sysc";

The <model> part of the compatible string should contain the SoC name as well.

For this particular node, the compatible property should be:
    compatible = "ralink,rt3050-sysc", "ralink,rt2880-sysc";

The first entry specifies the exact device and the second entry states that it
is compatible with the SYSC controller introduced in the RT2880 SoC.

This note applies to all other nodes as well.

-Gabor

Re: [RFC 11/11] MIPS: ralink: adds Kbuild files

[Gabor Juhos]

2013.01.23. 13:05 keltezéssel, John Crispin írta:
> Add the Kbuild symbols and Makefiles needed to actually build the ralink code
> from this series
> 
> Signed-off-by: John Crispin <blogic@openwrt.org>

<...>

> @@ -1160,7 +1177,7 @@ config BOOT_ELF32
>  
>  config MIPS_L1_CACHE_SHIFT
>  	int
> -	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
> +	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || RALINK_RT288X
>  	default "6" if MIPS_CPU_SCACHE
>  	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
>  	default "5"

This hunk is specific to the RT288X SoC, so it should be dropped from the patch.

-Gabor

Re: [RFC 11/11] MIPS: ralink: adds Kbuild files

[John Crispin]

Hi Gabor,

thanks for the review. I will fold the comments into my series and repost

     John