Re: [PATCH 2/2] clk: tegra: Make gr2d and gr3d clocks children of pll_c

["Terje Bergström" <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

On 29.03.2013 23:46, Stephen Warren wrote:
> On 03/28/2013 02:31 PM, Thierry Reding wrote:
>> By default these clocks are children of pll_m, but in downstream kernels
>> they are reparented to pll_c. While at it, decrease their frequencies to
>> 300 MHz because the defaults aren't in the specified range.
>>
>> gr2d can reportedly run at much higher frequencies, but 300 MHz works
>> and is a more conservative default.
> 
> Questions on this patch:
> 
> Do we need to do the same thing for Tegra30 and/or Tegra114?
> 
> Is 300MHz the right value?
> 
> I'm hoping that Peter, Prashant, and/or Terje can provide guidance here.

We need a patch for all SoC's. 2D can fail subtly with the too high
clocks, even though most of the time it seems to be doing just fine.

In Tegra20, 300MHz is the max rate we drive 2D in. Later Tegras have a
higher max clock, and in Tegra114 we drive it from a different PLL. But
for all of them 300MHz and PLLC should be a working configuration. I
haven't checked how we use PLLC in upstream, so I'm not 100% sure.

In downstream, the nvhost driver is responsible for setting a sane value
to the host1x clients. In upstream host1x, we missed that because we
didn't include the clock management code.

Terje