* [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
@ 2013-03-22 12:26 Akshay Saraswat
2013-03-23 0:41 ` Simon Glass
2013-05-21 11:19 ` Minkyu Kang
0 siblings, 2 replies; 4+ messages in thread
From: Akshay Saraswat @ 2013-03-22 12:26 UTC (permalink / raw)
To: u-boot
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
arch/arm/cpu/armv7/exynos/clock.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 956427c..5299bc7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));
} else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
}
return fout;
--
1.8.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
2013-03-22 12:26 [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency Akshay Saraswat
@ 2013-03-23 0:41 ` Simon Glass
2013-05-21 11:19 ` Minkyu Kang
1 sibling, 0 replies; 4+ messages in thread
From: Simon Glass @ 2013-03-23 0:41 UTC (permalink / raw)
To: u-boot
On Fri, Mar 22, 2013 at 5:26 AM, Akshay Saraswat <akshay.s@samsung.com> wrote:
> According to the latest exynos5 user manual, the equation for
> calculating PLL output was changed to
> FOUT= MDIV x FIN/(PDIV x 2^SDIV)
> earlier it was
> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
> So updating the clock code accordingly.
>
> Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
I think this is EVT1 silicon, right?
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 956427c..5299bc7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
> fout = (m + k / 1024) * (freq / (p * (1 << s)));
> } else {
> - if (s < 1)
> - s = 1;
> - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
> - fout = m * (freq / (p * (1 << (s - 1))));
> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> + fout = m * (freq / (p * (1 << s)));
> }
>
> return fout;
> --
> 1.8.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
2013-03-22 12:26 [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency Akshay Saraswat
2013-03-23 0:41 ` Simon Glass
@ 2013-05-21 11:19 ` Minkyu Kang
1 sibling, 0 replies; 4+ messages in thread
From: Minkyu Kang @ 2013-05-21 11:19 UTC (permalink / raw)
To: u-boot
Dear Akshay Saraswat,
On 22/03/13 21:26, Akshay Saraswat wrote:
> According to the latest exynos5 user manual, the equation for
> calculating PLL output was changed to
> FOUT= MDIV x FIN/(PDIV x 2^SDIV)
> earlier it was
> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
> So updating the clock code accordingly.
>
> Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 956427c..5299bc7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
> /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
> fout = (m + k / 1024) * (freq / (p * (1 << s)));
> } else {
> - if (s < 1)
> - s = 1;
> - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
> - fout = m * (freq / (p * (1 << (s - 1))));
> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> + fout = m * (freq / (p * (1 << s)));
> }
>
> return fout;
>
applied to u-boot-samsung.
Thanks,
Minkyu Kang.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
@ 2013-03-27 8:58 Akshay Saraswat
0 siblings, 0 replies; 4+ messages in thread
From: Akshay Saraswat @ 2013-03-27 8:58 UTC (permalink / raw)
To: u-boot
>On Fri, Mar 22, 2013 at 5:26 AM, Akshay Saraswat <akshay.s@samsung.com> wrote:
>> According to the latest exynos5 user manual, the equation for
>> calculating PLL output was changed to
>> FOUT= MDIV x FIN/(PDIV x 2^SDIV)
>> earlier it was
>> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
>> So updating the clock code accordingly.
>>
>> Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>
>Acked-by: Simon Glass <sjg@chromium.org>
>
>I think this is EVT1 silicon, right?
>
Yes, this is for evt1 silicon.
>> ---
>> arch/arm/cpu/armv7/exynos/clock.c | 6 ++----
>> 1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>> index 956427c..5299bc7 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
>> /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
>> fout = (m + k / 1024) * (freq / (p * (1 << s)));
>> } else {
>> - if (s < 1)
>> - s = 1;
>> - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
>> - fout = m * (freq / (p * (1 << (s - 1))));
>> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
>> + fout = m * (freq / (p * (1 << s)));
>> }
>>
>> return fout;
>> --
>> 1.8.0
>>
>
Regards,
Akshay Saraswat
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-05-21 11:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2013-03-22 12:26 [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency Akshay Saraswat
2013-03-23 0:41 ` Simon Glass
2013-05-21 11:19 ` Minkyu Kang
2013-03-27 8:58 Akshay Saraswat
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