* [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
[not found] ` <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44330@PG-ITMSG03.altera.priv.altera.com>
@ 2013-06-27 13:26 ` Chin Liang See
2013-06-28 11:22 ` Pavel Machek
0 siblings, 1 reply; 8+ messages in thread
From: Chin Liang See @ 2013-06-27 13:26 UTC (permalink / raw)
To: u-boot
socfpga: Separating the configuration file for Virtual Target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
---
include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
1 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 5633d2a..86563b7 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -22,6 +22,8 @@
/*
* High level configuration
*/
+/* Running on virtual target or real hardware */ #define
+CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -32,11 +34,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040
-#define V_NS16550_CLK 1000000
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
@@ -165,7 +168,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x00000000
@@ -181,8 +184,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 115200
/*
* FLASH
@@ -195,9 +203,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-27 13:26 ` [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Chin Liang See
@ 2013-06-28 11:22 ` Pavel Machek
2013-06-28 16:05 ` Chin Liang See
2013-06-28 20:23 ` [U-Boot] [PATCH v2 1/1] " Chin Liang See
0 siblings, 2 replies; 8+ messages in thread
From: Pavel Machek @ 2013-06-28 11:22 UTC (permalink / raw)
To: u-boot
Hi!
> socfpga: Separating the configuration file for Virtual Target and
> real hardware Cyclone V development kit
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> ---
> include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
> 1 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/include/configs/socfpga_cyclone5.h
> b/include/configs/socfpga_cyclone5.h
> index 5633d2a..86563b7 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -22,6 +22,8 @@
> /*
> * High level configuration
> */
> +/* Running on virtual target or real hardware */ #define
> +CONFIG_SOCFPGA_VIRTUAL_TARGET
>
Unfortunately, it came word-wrapped. Looks ok otherwise.
Reviewed-by: Pavel Machek <pavel@denx.de>
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-28 11:22 ` Pavel Machek
@ 2013-06-28 16:05 ` Chin Liang See
2013-06-28 16:09 ` Stefan Roese
2013-06-28 20:23 ` [U-Boot] [PATCH v2 1/1] " Chin Liang See
1 sibling, 1 reply; 8+ messages in thread
From: Chin Liang See @ 2013-06-28 16:05 UTC (permalink / raw)
To: u-boot
Hi Pavel,
On Fri, 2013-06-28 at 13:22 +0200, ZY - pavel wrote:
> Hi!
>
> > socfpga: Separating the configuration file for Virtual Target and
> > real hardware Cyclone V development kit
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > ---
> > include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
> > 1 files changed, 21 insertions(+), 7 deletions(-)
> >
> > diff --git a/include/configs/socfpga_cyclone5.h
> > b/include/configs/socfpga_cyclone5.h
> > index 5633d2a..86563b7 100644
> > --- a/include/configs/socfpga_cyclone5.h
> > +++ b/include/configs/socfpga_cyclone5.h
> > @@ -22,6 +22,8 @@
> > /*
> > * High level configuration
> > */
> > +/* Running on virtual target or real hardware */ #define
> > +CONFIG_SOCFPGA_VIRTUAL_TARGET
> >
>
> Unfortunately, it came word-wrapped. Looks ok otherwise.
Hmmm... seems the mail client did this when sending.
I will resubmit this patch with new mail client.
Thanks
Chin Liang
>
> Reviewed-by: Pavel Machek <pavel@denx.de>
>
> Thanks,
> Pavel
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-28 16:05 ` Chin Liang See
@ 2013-06-28 16:09 ` Stefan Roese
0 siblings, 0 replies; 8+ messages in thread
From: Stefan Roese @ 2013-06-28 16:09 UTC (permalink / raw)
To: u-boot
Hi Chin Liang,
On 06/28/2013 06:05 PM, Chin Liang See wrote:
>>> socfpga: Separating the configuration file for Virtual Target and
>>> real hardware Cyclone V development kit
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> ---
>>> include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
>>> 1 files changed, 21 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/include/configs/socfpga_cyclone5.h
>>> b/include/configs/socfpga_cyclone5.h
>>> index 5633d2a..86563b7 100644
>>> --- a/include/configs/socfpga_cyclone5.h
>>> +++ b/include/configs/socfpga_cyclone5.h
>>> @@ -22,6 +22,8 @@
>>> /*
>>> * High level configuration
>>> */
>>> +/* Running on virtual target or real hardware */ #define
>>> +CONFIG_SOCFPGA_VIRTUAL_TARGET
>>>
>>
>> Unfortunately, it came word-wrapped. Looks ok otherwise.
>
> Hmmm... seems the mail client did this when sending.
> I will resubmit this patch with new mail client.
It always recommended to use "git send-email" for patch submission.
Best regards,
Stefan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-28 11:22 ` Pavel Machek
2013-06-28 16:05 ` Chin Liang See
@ 2013-06-28 20:23 ` Chin Liang See
2013-06-28 22:47 ` Wolfgang Denk
1 sibling, 1 reply; 8+ messages in thread
From: Chin Liang See @ 2013-06-28 20:23 UTC (permalink / raw)
To: u-boot
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
---
include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 5633d2a..be3799b 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -22,6 +22,8 @@
/*
* High level configuration
*/
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -32,11 +34,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040
-#define V_NS16550_CLK 1000000
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
@@ -165,7 +168,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x00000000
@@ -181,8 +184,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,
115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 115200
/*
* FLASH
@@ -195,9 +203,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-28 20:23 ` [U-Boot] [PATCH v2 1/1] " Chin Liang See
@ 2013-06-28 22:47 ` Wolfgang Denk
2013-07-01 13:44 ` Chin Liang See
2013-07-01 14:05 ` [U-Boot] [PATCH v3 1/1] socfpga: Adding configuration for " Chin Liang See
0 siblings, 2 replies; 8+ messages in thread
From: Wolfgang Denk @ 2013-06-28 22:47 UTC (permalink / raw)
To: u-boot
Dear Chin Liang See,
In message <1372451028.11240.2.camel@drezykow-VirtualBox.altera.com> you wrote:
> socfpga: Separating the configuration file for Virtual
> Target and real hardware Cyclone V development kit
Please keep the Subject SHORT - it should be 50 characters or less!
And please do not repeat the Subject in the commit messgae - this is
redundant and thus makes no sense.
Chose a short and descriptive Subject, and provide prosa in the
commit mesage.
Thanks!!
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The alternative to genuflecting before the god of code-bumming is
finding a better algorithm. It should be clear that none such was
available. If your code is too slow, you must make it faster. If no
better algorithm is available, you must trim cycles.
- td at alice.UUCP (Tom Duff) 29 Aug 88
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v2 1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit
2013-06-28 22:47 ` Wolfgang Denk
@ 2013-07-01 13:44 ` Chin Liang See
2013-07-01 14:05 ` [U-Boot] [PATCH v3 1/1] socfpga: Adding configuration for " Chin Liang See
1 sibling, 0 replies; 8+ messages in thread
From: Chin Liang See @ 2013-07-01 13:44 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Sat, 2013-06-29 at 00:47 +0200, ZY - wd wrote:
> Dear Chin Liang See,
>
> In message <1372451028.11240.2.camel@drezykow-VirtualBox.altera.com> you wrote:
> > socfpga: Separating the configuration file for Virtual
> > Target and real hardware Cyclone V development kit
>
> Please keep the Subject SHORT - it should be 50 characters or less!
>
> And please do not repeat the Subject in the commit messgae - this is
> redundant and thus makes no sense.
>
> Chose a short and descriptive Subject, and provide prosa in the
> commit mesage.
>
Noted with thanks.
Let me fix it on next revision
Chin Liang
> Thanks!!
>
>
> Wolfgang Denk
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH v3 1/1] socfpga: Adding configuration for development kit
2013-06-28 22:47 ` Wolfgang Denk
2013-07-01 13:44 ` Chin Liang See
@ 2013-07-01 14:05 ` Chin Liang See
1 sibling, 0 replies; 8+ messages in thread
From: Chin Liang See @ 2013-07-01 14:05 UTC (permalink / raw)
To: u-boot
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
---
include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 5633d2a..be3799b 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -22,6 +22,8 @@
/*
* High level configuration
*/
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -32,11 +34,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040
-#define V_NS16550_CLK 1000000
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
@@ -165,7 +168,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x00000000
@@ -181,8 +184,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,
115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 115200
/*
* FLASH
@@ -195,9 +203,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.9.5
^ permalink raw reply related [flat|nested] 8+ messages in thread
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[not found] <CAEM3b1DEZZBX2rm6c8ctR7TYz7X4OSUYucWdC+n7m4_9tKn+Xg@mail.gmail.com>
[not found] ` <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44330@PG-ITMSG03.altera.priv.altera.com>
2013-06-27 13:26 ` [U-Boot] [PATCH1/1] socfpga: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Chin Liang See
2013-06-28 11:22 ` Pavel Machek
2013-06-28 16:05 ` Chin Liang See
2013-06-28 16:09 ` Stefan Roese
2013-06-28 20:23 ` [U-Boot] [PATCH v2 1/1] " Chin Liang See
2013-06-28 22:47 ` Wolfgang Denk
2013-07-01 13:44 ` Chin Liang See
2013-07-01 14:05 ` [U-Boot] [PATCH v3 1/1] socfpga: Adding configuration for " Chin Liang See
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