From: "\"“tiejun.chen”\"" <tiejun.chen@windriver.com> To: Bhushan Bharat-R65777 <R65777@freescale.com> Cc: "kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, "agraf@suse.de" <agraf@suse.de>, Wood Scott-B07421 <B07421@freescale.com> Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages Date: Thu, 18 Jul 2013 15:31:28 +0800 [thread overview] Message-ID: <51E799D0.1030406@windriver.com> (raw) In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D070D6AFF@039-SN2MPN1-013.039d.mgd.msft.net> On 07/18/2013 03:12 PM, Bhushan Bharat-R65777 wrote: > > >> -----Original Message----- >> From: "“tiejun.chen”" [mailto:tiejun.chen@windriver.com] >> Sent: Thursday, July 18, 2013 11:56 AM >> To: Bhushan Bharat-R65777 >> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; agraf@suse.de; Wood Scott- >> B07421; Bhushan Bharat-R65777 >> Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel >> managed pages >> >> On 07/18/2013 02:04 PM, Bharat Bhushan wrote: >>> If there is a struct page for the requested mapping then it's normal >>> DDR and the mapping sets "M" bit (coherent, cacheable) else this is >>> treated as I/O and we set "I + G" (cache inhibited, guarded) >>> >>> This helps setting proper TLB mapping for direct assigned device >>> >>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> >>> --- >>> arch/powerpc/kvm/e500_mmu_host.c | 17 ++++++++++++----- >>> 1 files changed, 12 insertions(+), 5 deletions(-) >>> >>> diff --git a/arch/powerpc/kvm/e500_mmu_host.c >>> b/arch/powerpc/kvm/e500_mmu_host.c >>> index 1c6a9d7..089c227 100644 >>> --- a/arch/powerpc/kvm/e500_mmu_host.c >>> +++ b/arch/powerpc/kvm/e500_mmu_host.c >>> @@ -64,13 +64,20 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int >> usermode) >>> return mas3; >>> } >>> >>> -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode) >>> +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn) >>> { >>> + u32 mas2_attr; >>> + >>> + mas2_attr = mas2 & MAS2_ATTRIB_MASK; >>> + >>> + if (!pfn_valid(pfn)) { >> >> Why not directly use kvm_is_mmio_pfn()? > > What I understand from this function (someone can correct me) is that it returns "false" when the page is managed by kernel and is not marked as RESERVED (for some reason). For us it does not matter whether the page is reserved or not, if it is kernel visible page then it is DDR. > I think you are setting I|G by addressing all mmio pages, right? If so, KVM: direct mmio pfn check Userspace may specify memory slots that are backed by mmio pages rather than normal RAM. In some cases it is not enough to identify these mmio pages by pfn_valid(). This patch adds checking the PageReserved as well. Tiejun > -Bharat > >> >> Tiejun >> >>> + mas2_attr |= MAS2_I | MAS2_G; >>> + } else { >>> #ifdef CONFIG_SMP >>> - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M; >>> -#else >>> - return mas2 & MAS2_ATTRIB_MASK; >>> + mas2_attr |= MAS2_M; >>> #endif >>> + } >>> + return mas2_attr; >>> } >>> >>> /* >>> @@ -313,7 +320,7 @@ static void kvmppc_e500_setup_stlbe( >>> /* Force IPROT=0 for all guest mappings. */ >>> stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; >>> stlbe->mas2 = (gvaddr & MAS2_EPN) | >>> - e500_shadow_mas2_attrib(gtlbe->mas2, pr); >>> + e500_shadow_mas2_attrib(gtlbe->mas2, pfn); >>> stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | >>> e500_shadow_mas3_attrib(gtlbe->mas7_3, pr); >>> >>> >> >
WARNING: multiple messages have this Message-ID (diff)
From: "\"“tiejun.chen”\"" <tiejun.chen@windriver.com> To: Bhushan Bharat-R65777 <R65777@freescale.com> Cc: "kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, "agraf@suse.de" <agraf@suse.de>, Wood Scott-B07421 <B07421@freescale.com> Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages Date: Thu, 18 Jul 2013 07:31:28 +0000 [thread overview] Message-ID: <51E799D0.1030406@windriver.com> (raw) In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D070D6AFF@039-SN2MPN1-013.039d.mgd.msft.net> On 07/18/2013 03:12 PM, Bhushan Bharat-R65777 wrote: > > >> -----Original Message----- >> From: "“tiejun.chen”" [mailto:tiejun.chen@windriver.com] >> Sent: Thursday, July 18, 2013 11:56 AM >> To: Bhushan Bharat-R65777 >> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; agraf@suse.de; Wood Scott- >> B07421; Bhushan Bharat-R65777 >> Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel >> managed pages >> >> On 07/18/2013 02:04 PM, Bharat Bhushan wrote: >>> If there is a struct page for the requested mapping then it's normal >>> DDR and the mapping sets "M" bit (coherent, cacheable) else this is >>> treated as I/O and we set "I + G" (cache inhibited, guarded) >>> >>> This helps setting proper TLB mapping for direct assigned device >>> >>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> >>> --- >>> arch/powerpc/kvm/e500_mmu_host.c | 17 ++++++++++++----- >>> 1 files changed, 12 insertions(+), 5 deletions(-) >>> >>> diff --git a/arch/powerpc/kvm/e500_mmu_host.c >>> b/arch/powerpc/kvm/e500_mmu_host.c >>> index 1c6a9d7..089c227 100644 >>> --- a/arch/powerpc/kvm/e500_mmu_host.c >>> +++ b/arch/powerpc/kvm/e500_mmu_host.c >>> @@ -64,13 +64,20 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int >> usermode) >>> return mas3; >>> } >>> >>> -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode) >>> +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn) >>> { >>> + u32 mas2_attr; >>> + >>> + mas2_attr = mas2 & MAS2_ATTRIB_MASK; >>> + >>> + if (!pfn_valid(pfn)) { >> >> Why not directly use kvm_is_mmio_pfn()? > > What I understand from this function (someone can correct me) is that it returns "false" when the page is managed by kernel and is not marked as RESERVED (for some reason). For us it does not matter whether the page is reserved or not, if it is kernel visible page then it is DDR. > I think you are setting I|G by addressing all mmio pages, right? If so, KVM: direct mmio pfn check Userspace may specify memory slots that are backed by mmio pages rather than normal RAM. In some cases it is not enough to identify these mmio pages by pfn_valid(). This patch adds checking the PageReserved as well. Tiejun > -Bharat > >> >> Tiejun >> >>> + mas2_attr |= MAS2_I | MAS2_G; >>> + } else { >>> #ifdef CONFIG_SMP >>> - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M; >>> -#else >>> - return mas2 & MAS2_ATTRIB_MASK; >>> + mas2_attr |= MAS2_M; >>> #endif >>> + } >>> + return mas2_attr; >>> } >>> >>> /* >>> @@ -313,7 +320,7 @@ static void kvmppc_e500_setup_stlbe( >>> /* Force IPROT=0 for all guest mappings. */ >>> stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; >>> stlbe->mas2 = (gvaddr & MAS2_EPN) | >>> - e500_shadow_mas2_attrib(gtlbe->mas2, pr); >>> + e500_shadow_mas2_attrib(gtlbe->mas2, pfn); >>> stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | >>> e500_shadow_mas3_attrib(gtlbe->mas7_3, pr); >>> >>> >> >
next prev parent reply other threads:[~2013-07-18 7:31 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-07-18 6:04 [PATCH 1/2] kvm: powerpc: Do not ignore "E" attribute in mas2 Bharat Bhushan 2013-07-18 6:16 ` Bharat Bhushan 2013-07-18 6:04 ` [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages Bharat Bhushan 2013-07-18 6:16 ` Bharat Bhushan 2013-07-18 6:26 ` "“tiejun.chen”" 2013-07-18 6:26 ` "“tiejun.chen”" 2013-07-18 7:12 ` Bhushan Bharat-R65777 2013-07-18 7:12 ` Bhushan Bharat-R65777 2013-07-18 7:31 ` "“tiejun.chen”" [this message] 2013-07-18 7:31 ` "“tiejun.chen”" 2013-07-18 8:08 ` Bhushan Bharat-R65777 2013-07-18 8:08 ` Bhushan Bharat-R65777 2013-07-18 8:21 ` "“tiejun.chen”" 2013-07-18 8:21 ` "“tiejun.chen”" 2013-07-18 8:22 ` Bhushan Bharat-R65777 2013-07-18 8:22 ` Bhushan Bharat-R65777 2013-07-18 8:25 ` Bhushan Bharat-R65777 2013-07-18 8:25 ` Bhushan Bharat-R65777 2013-07-18 8:55 ` "“tiejun.chen”" 2013-07-18 8:55 ` "“tiejun.chen”" 2013-07-18 9:44 ` Alexander Graf 2013-07-18 9:44 ` Alexander Graf 2013-07-18 9:56 ` "“tiejun.chen”" 2013-07-18 9:56 ` "“tiejun.chen”" 2013-07-18 10:00 ` Alexander Graf 2013-07-18 10:00 ` Alexander Graf 2013-07-18 10:14 ` "“tiejun.chen”" 2013-07-18 10:14 ` "“tiejun.chen”" 2013-07-18 16:11 ` Scott Wood 2013-07-18 16:11 ` Scott Wood 2013-07-18 9:48 ` Alexander Graf 2013-07-18 9:48 ` Alexander Graf 2013-07-18 9:51 ` Bhushan Bharat-R65777 2013-07-18 10:08 ` "“tiejun.chen”" 2013-07-18 10:08 ` "“tiejun.chen”" 2013-07-18 10:12 ` Alexander Graf 2013-07-18 10:12 ` Alexander Graf 2013-07-18 10:19 ` "“tiejun.chen”" 2013-07-18 10:19 ` "“tiejun.chen”" 2013-07-18 10:27 ` Alexander Graf 2013-07-18 10:27 ` Alexander Graf 2013-07-24 2:26 ` "“tiejun.chen”" 2013-07-24 2:26 ` "“tiejun.chen”" 2013-07-24 8:25 ` Alexander Graf 2013-07-24 8:25 ` Alexander Graf 2013-07-24 9:11 ` Bhushan Bharat-R65777 2013-07-24 9:11 ` Bhushan Bharat-R65777 2013-07-24 9:21 ` Alexander Graf 2013-07-24 9:21 ` Alexander Graf 2013-07-24 9:35 ` Gleb Natapov 2013-07-24 9:35 ` Gleb Natapov 2013-07-24 9:39 ` Alexander Graf 2013-07-24 9:39 ` Alexander Graf 2013-07-24 20:32 ` Scott Wood 2013-07-24 20:32 ` Scott Wood 2013-07-24 20:32 ` Scott Wood 2013-07-25 8:50 ` Gleb Natapov 2013-07-25 8:50 ` Gleb Natapov 2013-07-25 8:50 ` Gleb Natapov 2013-07-25 16:07 ` Alexander Graf 2013-07-25 16:07 ` Alexander Graf 2013-07-25 16:07 ` Alexander Graf 2013-07-25 16:14 ` Gleb Natapov 2013-07-25 16:14 ` Gleb Natapov 2013-07-25 16:14 ` Gleb Natapov 2013-07-26 22:27 ` Scott Wood 2013-07-26 22:27 ` Scott Wood 2013-07-26 22:27 ` Scott Wood 2013-07-24 10:01 ` Gleb Natapov 2013-07-24 10:01 ` Gleb Natapov 2013-07-24 10:09 ` Alexander Graf 2013-07-24 10:09 ` Alexander Graf 2013-07-24 10:19 ` Gleb Natapov 2013-07-24 10:19 ` Gleb Natapov 2013-07-24 10:25 ` Alexander Graf 2013-07-24 10:25 ` Alexander Graf 2013-07-24 10:30 ` Gleb Natapov 2013-07-24 10:30 ` Gleb Natapov 2013-07-25 1:04 ` Andrea Arcangeli 2013-07-25 1:04 ` Andrea Arcangeli 2013-07-18 8:27 ` "“tiejun.chen”" 2013-07-18 8:27 ` "“tiejun.chen”"
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