[PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Mark Zhang]

T114 sbc1-sbc6 have more possible parent clocks than t30.
So correct the parents and mux width for them.

Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra114.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index f74ed19..71db736 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1844,12 +1844,12 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
 	TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
 	TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
-	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
-	TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
-	TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
-	TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
-	TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
-	TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
+	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
+	TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
+	TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
+	TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
+	TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
+	TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
 	TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
 	TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
 	TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
-- 
1.7.9.5

[PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Mark Zhang]

T114 sbc1-sbc6 have more possible parent clocks than t30.
So correct the parents and mux width for them.

Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index f74ed19..71db736 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1844,12 +1844,12 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
 	TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
 	TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
-	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
-	TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
-	TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
-	TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
-	TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
-	TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
+	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
+	TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
+	TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
+	TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
+	TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
+	TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
 	TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
 	TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
 	TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
-- 
1.7.9.5

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Mark Zhang]

From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

COP is a reset only clock. So this patch adds NO_CLK support
then adds the COP clock.

Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-periph-gate.c |   15 +++++++++++++++
 drivers/clk/tegra/clk-tegra114.c    |    9 ++++++++-
 drivers/clk/tegra/clk.h             |    2 ++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index bafee98..092f256 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -51,6 +51,11 @@ static int clk_periph_is_enabled(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	int state = 1;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return 0;
+	}
+
 	if (!(read_enb(gate) & periph_clk_to_bit(gate)))
 		state = 0;
 
@@ -66,6 +71,11 @@ static int clk_periph_enable(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	unsigned long flags = 0;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return -EINVAL;
+	}
+
 	spin_lock_irqsave(&periph_ref_lock, flags);
 
 	gate->enable_refcnt[gate->clk_num]++;
@@ -102,6 +112,11 @@ static void clk_periph_disable(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	unsigned long flags = 0;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return;
+	}
+
 	spin_lock_irqsave(&periph_ref_lock, flags);
 
 	gate->enable_refcnt[gate->clk_num]--;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 71db736..7172faf 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -863,7 +863,7 @@ static unsigned long tegra114_input_freq[] = {
 			mux_d_audio_clk_idx, 0)
 
 enum tegra114_clk {
-	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
+	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
 	ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
 	gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
 	host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
@@ -1921,6 +1921,13 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 	int i;
 	u32 val;
 
+	/* cop */
+	clk = tegra_clk_register_periph_gate("cop", NULL, TEGRA_PERIPH_NO_CLK,
+						clk_base, CLK_IGNORE_UNUSED, 1,
+						&periph_l_regs,
+						periph_clk_enb_refcnt);
+	clks[cop] = clk;
+
 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
 				  0, 34, &periph_h_regs,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 07cfacd..0124e11 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -375,6 +375,7 @@ struct tegra_clk_periph_regs {
  *     bus to flush the write operation in apb bus. This flag indicates
  *     that this peripheral is in apb bus.
  * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
+ * TEGRA_PERIPH_NO_CLK - Reset only clock node
  */
 struct tegra_clk_periph_gate {
 	u32			magic;
@@ -395,6 +396,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
+#define TEGRA_PERIPH_NO_CLK BIT(4)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
-- 
1.7.9.5

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Mark Zhang]

From: Peter De Schrijver <pdeschrijver@nvidia.com>

COP is a reset only clock. So this patch adds NO_CLK support
then adds the COP clock.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 drivers/clk/tegra/clk-periph-gate.c |   15 +++++++++++++++
 drivers/clk/tegra/clk-tegra114.c    |    9 ++++++++-
 drivers/clk/tegra/clk.h             |    2 ++
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index bafee98..092f256 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -51,6 +51,11 @@ static int clk_periph_is_enabled(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	int state = 1;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return 0;
+	}
+
 	if (!(read_enb(gate) & periph_clk_to_bit(gate)))
 		state = 0;
 
@@ -66,6 +71,11 @@ static int clk_periph_enable(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	unsigned long flags = 0;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return -EINVAL;
+	}
+
 	spin_lock_irqsave(&periph_ref_lock, flags);
 
 	gate->enable_refcnt[gate->clk_num]++;
@@ -102,6 +112,11 @@ static void clk_periph_disable(struct clk_hw *hw)
 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
 	unsigned long flags = 0;
 
+	if (gate->flags & TEGRA_PERIPH_NO_CLK) {
+		WARN_ON(1);
+		return;
+	}
+
 	spin_lock_irqsave(&periph_ref_lock, flags);
 
 	gate->enable_refcnt[gate->clk_num]--;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 71db736..7172faf 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -863,7 +863,7 @@ static unsigned long tegra114_input_freq[] = {
 			mux_d_audio_clk_idx, 0)
 
 enum tegra114_clk {
-	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
+	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
 	ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
 	gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
 	host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
@@ -1921,6 +1921,13 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
 	int i;
 	u32 val;
 
+	/* cop */
+	clk = tegra_clk_register_periph_gate("cop", NULL, TEGRA_PERIPH_NO_CLK,
+						clk_base, CLK_IGNORE_UNUSED, 1,
+						&periph_l_regs,
+						periph_clk_enb_refcnt);
+	clks[cop] = clk;
+
 	/* apbdma */
 	clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
 				  0, 34, &periph_h_regs,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 07cfacd..0124e11 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -375,6 +375,7 @@ struct tegra_clk_periph_regs {
  *     bus to flush the write operation in apb bus. This flag indicates
  *     that this peripheral is in apb bus.
  * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
+ * TEGRA_PERIPH_NO_CLK - Reset only clock node
  */
 struct tegra_clk_periph_gate {
 	u32			magic;
@@ -395,6 +396,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
+#define TEGRA_PERIPH_NO_CLK BIT(4)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
-- 
1.7.9.5

[PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Mark Zhang]

In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".

Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.

Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra114.c |   13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 7172faf..a45ea68 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -806,13 +806,6 @@ static unsigned long tegra114_input_freq[] = {
 			periph_clk_enb_refcnt, _gate_flags, _clk_id,	\
 			_parents##_idx, 0)
 
-#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset,	\
-			    _clk_num, _regs, _gate_flags, _clk_id)	\
-	TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
-			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
-			_clk_num, periph_clk_enb_refcnt, _gate_flags,	\
-			_clk_id, _parents##_idx, 0)
-
 #define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 			    _clk_num, _regs, _gate_flags, _clk_id, flags)\
 	TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
@@ -1857,7 +1850,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
 	TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
 	TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
-	TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
+	TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
 	TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
 	TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
 	TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
@@ -1873,8 +1866,8 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
 	TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
 	TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
-	TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
-	TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
+	TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
+	TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
 	TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
 	TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
 	TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
-- 
1.7.9.5

[PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Mark Zhang]

In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".

Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.

Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |   13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 7172faf..a45ea68 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -806,13 +806,6 @@ static unsigned long tegra114_input_freq[] = {
 			periph_clk_enb_refcnt, _gate_flags, _clk_id,	\
 			_parents##_idx, 0)
 
-#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset,	\
-			    _clk_num, _regs, _gate_flags, _clk_id)	\
-	TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
-			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
-			_clk_num, periph_clk_enb_refcnt, _gate_flags,	\
-			_clk_id, _parents##_idx, 0)
-
 #define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 			    _clk_num, _regs, _gate_flags, _clk_id, flags)\
 	TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
@@ -1857,7 +1850,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
 	TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
 	TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
-	TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
+	TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
 	TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
 	TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
 	TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
@@ -1873,8 +1866,8 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
 	TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
 	TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
-	TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
-	TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
+	TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
+	TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
 	TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
 	TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
 	TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
-- 
1.7.9.5

[PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

[Mark Zhang]

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra114.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index a45ea68..72976a2 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2199,6 +2199,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{i2s4, pll_a_out0, 11289600, 0},
 	{dfll_soc, pll_p, 51000000, 1},
 	{dfll_ref, pll_p, 51000000, 1},
+	{gr_2d, pll_c2, 300000000, 0},
+	{gr_3d, pll_c2, 300000000, 0},
 	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 
-- 
1.7.9.5

[PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

[Mark Zhang]

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index a45ea68..72976a2 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2199,6 +2199,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{i2s4, pll_a_out0, 11289600, 0},
 	{dfll_soc, pll_p, 51000000, 1},
 	{dfll_ref, pll_p, 51000000, 1},
+	{gr_2d, pll_c2, 300000000, 0},
+	{gr_3d, pll_c2, 300000000, 0},
 	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 
-- 
1.7.9.5

[PATCH 5/5] clk: tegra: Set the clk parent of host1x to pll_p

[Mark Zhang]

From: Andrew Chew <achew-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: Andrew Chew <achew-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/clk/tegra/clk-tegra114.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 72976a2..100105b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2197,6 +2197,7 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{i2s2, pll_a_out0, 11289600, 0},
 	{i2s3, pll_a_out0, 11289600, 0},
 	{i2s4, pll_a_out0, 11289600, 0},
+	{host1x, pll_p, 136000000, 0},
 	{dfll_soc, pll_p, 51000000, 1},
 	{dfll_ref, pll_p, 51000000, 1},
 	{gr_2d, pll_c2, 300000000, 0},
-- 
1.7.9.5

[PATCH 5/5] clk: tegra: Set the clk parent of host1x to pll_p

[Mark Zhang]

From: Andrew Chew <achew@nvidia.com>

The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 72976a2..100105b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2197,6 +2197,7 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{i2s2, pll_a_out0, 11289600, 0},
 	{i2s3, pll_a_out0, 11289600, 0},
 	{i2s4, pll_a_out0, 11289600, 0},
+	{host1x, pll_p, 136000000, 0},
 	{dfll_soc, pll_p, 51000000, 1},
 	{dfll_ref, pll_p, 51000000, 1},
 	{gr_2d, pll_c2, 300000000, 0},
-- 
1.7.9.5

Re: [PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> T114 sbc1-sbc6 have more possible parent clocks than t30.
> So correct the parents and mux width for them.

s/T114/Tegra114/ s/t30/Tegra30/

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

> -	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
...
> +	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),

This isn't a comment on this patch, but sometime later, can we remove
those device names from these entries? They're wrong on many different
levels, and shouldn't be required now that all our devices get clocks
from DT.

[PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> T114 sbc1-sbc6 have more possible parent clocks than t30.
> So correct the parents and mux width for them.

s/T114/Tegra114/ s/t30/Tegra30/

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

> -	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
...
> +	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),

This isn't a comment on this patch, but sometime later, can we remove
those device names from these entries? They're wrong on many different
levels, and shouldn't be required now that all our devices get clocks
from DT.

Re: [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> 
> COP is a reset only clock. So this patch adds NO_CLK support
> then adds the COP clock.

Do we actually need this clock upstream yet?

IIRC, Prashant was working on implementing the common reset API, so I'd
prefer not to add any reset-only "clocks" to the clock driver, but
rather to simply make sure that the new reset driver exposes them.

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

>  enum tegra114_clk {
> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,

To make this change, you would also need to edit
include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
clock driver include that file rather than defining its own enum?

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> COP is a reset only clock. So this patch adds NO_CLK support
> then adds the COP clock.

Do we actually need this clock upstream yet?

IIRC, Prashant was working on implementing the common reset API, so I'd
prefer not to add any reset-only "clocks" to the clock driver, but
rather to simply make sure that the new reset driver exposes them.

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

>  enum tegra114_clk {
> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,

To make this change, you would also need to edit
include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
clock driver include that file rather than defining its own enum?

Re: [PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
> So change the clock init macro for these clocks from
> "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
> 
> Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
> remove this macro.

Patches 3-5 look fine as far as I'm concerned, although I'd like Peter
or Prashant to ack them too.

Patches 3-5,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Stephen Warren]

On 08/07/2013 05:25 AM, Mark Zhang wrote:
> In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
> So change the clock init macro for these clocks from
> "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
> 
> Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
> remove this macro.

Patches 3-5 look fine as far as I'm concerned, although I'd like Peter
or Prashant to ack them too.

Patches 3-5,
Acked-by: Stephen Warren <swarren@nvidia.com>

Re: [PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Mark Zhang]

On 08/08/2013 12:56 AM, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>> T114 sbc1-sbc6 have more possible parent clocks than t30.
>> So correct the parents and mux width for them.
> 
> s/T114/Tegra114/ s/t30/Tegra30/
> 

Got it.

>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
>> -	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
> ...
>> +	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
> 
> This isn't a comment on this patch, but sometime later, can we remove
> those device names from these entries? They're wrong on many different
> levels, and shouldn't be required now that all our devices get clocks
> from DT.
> 

Correct. Actually they're useless if all drivers get their clocks via
DT. Just as you said, we can do it later and will rewrite all clock
declarations at that time.

[PATCH 1/5] clk: tegra: Correct sbc mux width & parent

[Mark Zhang]

On 08/08/2013 12:56 AM, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>> T114 sbc1-sbc6 have more possible parent clocks than t30.
>> So correct the parents and mux width for them.
> 
> s/T114/Tegra114/ s/t30/Tegra30/
> 

Got it.

>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
>> -	TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
> ...
>> +	TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
> 
> This isn't a comment on this patch, but sometime later, can we remove
> those device names from these entries? They're wrong on many different
> levels, and shouldn't be required now that all our devices get clocks
> from DT.
> 

Correct. Actually they're useless if all drivers get their clocks via
DT. Just as you said, we can do it later and will rewrite all clock
declarations at that time.

Re: [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Mark Zhang]

Okay, I don't know these background infos. If so, there is no reason to
upstream this kind of patches.

On 08/08/2013 12:58 AM, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>> From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> COP is a reset only clock. So this patch adds NO_CLK support
>> then adds the COP clock.
> 
> Do we actually need this clock upstream yet?
> 
> IIRC, Prashant was working on implementing the common reset API, so I'd
> prefer not to add any reset-only "clocks" to the clock driver, but
> rather to simply make sure that the new reset driver exposes them.
> 
>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
>>  enum tegra114_clk {
>> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> 
> To make this change, you would also need to edit
> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
> clock driver include that file rather than defining its own enum?
> 

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Mark Zhang]

Okay, I don't know these background infos. If so, there is no reason to
upstream this kind of patches.

On 08/08/2013 12:58 AM, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>>
>> COP is a reset only clock. So this patch adds NO_CLK support
>> then adds the COP clock.
> 
> Do we actually need this clock upstream yet?
> 
> IIRC, Prashant was working on implementing the common reset API, so I'd
> prefer not to add any reset-only "clocks" to the clock driver, but
> rather to simply make sure that the new reset driver exposes them.
> 
>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
>>  enum tegra114_clk {
>> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> 
> To make this change, you would also need to edit
> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
> clock driver include that file rather than defining its own enum?
> 

Re: [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 06:58:03PM +0200, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
> > From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > 
> > COP is a reset only clock. So this patch adds NO_CLK support
> > then adds the COP clock.
> 
> Do we actually need this clock upstream yet?
> 
> IIRC, Prashant was working on implementing the common reset API, so I'd
> prefer not to add any reset-only "clocks" to the clock driver, but
> rather to simply make sure that the new reset driver exposes them.
> 

It would be better if we can switch to the reset API.

> > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
> >  enum tegra114_clk {
> > -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> > +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> 
> To make this change, you would also need to edit
> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
> clock driver include that file rather than defining its own enum?

History. include/dt-bindings/clock/tegra114-car.h didn't exist when
clk-tegra114.c was written.

Cheers,

Peter.

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 06:58:03PM +0200, Stephen Warren wrote:
> On 08/07/2013 05:25 AM, Mark Zhang wrote:
> > From: Peter De Schrijver <pdeschrijver@nvidia.com>
> > 
> > COP is a reset only clock. So this patch adds NO_CLK support
> > then adds the COP clock.
> 
> Do we actually need this clock upstream yet?
> 
> IIRC, Prashant was working on implementing the common reset API, so I'd
> prefer not to add any reset-only "clocks" to the clock driver, but
> rather to simply make sure that the new reset driver exposes them.
> 

It would be better if we can switch to the reset API.

> > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> 
> >  enum tegra114_clk {
> > -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> > +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
> 
> To make this change, you would also need to edit
> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
> clock driver include that file rather than defining its own enum?

History. include/dt-bindings/clock/tegra114-car.h didn't exist when
clk-tegra114.c was written.

Cheers,

Peter.

Re: [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Stephen Warren]

On 08/19/2013 08:53 AM, Peter De Schrijver wrote:
> On Wed, Aug 07, 2013 at 06:58:03PM +0200, Stephen Warren wrote:
>> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>>> From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>
>>> COP is a reset only clock. So this patch adds NO_CLK support
>>> then adds the COP clock.
>>
>> Do we actually need this clock upstream yet?
>>
>> IIRC, Prashant was working on implementing the common reset API, so I'd
>> prefer not to add any reset-only "clocks" to the clock driver, but
>> rather to simply make sure that the new reset driver exposes them.
>>
> 
> It would be better if we can switch to the reset API.
> 
>>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
>>
>>>  enum tegra114_clk {
>>> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>>> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>>
>> To make this change, you would also need to edit
>> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
>> clock driver include that file rather than defining its own enum?
> 
> History. include/dt-bindings/clock/tegra114-car.h didn't exist when
> clk-tegra114.c was written.

Right, but then someone created tegra114-car.h, but didn't bother to
follow through and update the clock driver:-(

[PATCH 2/5] clk: tegra: Add reset only clock node flag and COP

[Stephen Warren]

On 08/19/2013 08:53 AM, Peter De Schrijver wrote:
> On Wed, Aug 07, 2013 at 06:58:03PM +0200, Stephen Warren wrote:
>> On 08/07/2013 05:25 AM, Mark Zhang wrote:
>>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>
>>> COP is a reset only clock. So this patch adds NO_CLK support
>>> then adds the COP clock.
>>
>> Do we actually need this clock upstream yet?
>>
>> IIRC, Prashant was working on implementing the common reset API, so I'd
>> prefer not to add any reset-only "clocks" to the clock driver, but
>> rather to simply make sure that the new reset driver exposes them.
>>
> 
> It would be better if we can switch to the reset API.
> 
>>> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
>>
>>>  enum tegra114_clk {
>>> -	rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>>> +	cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
>>
>> To make this change, you would also need to edit
>> include/dt-bindings/clock/tegra114-car.h. BTW, why doesn't the Tegra
>> clock driver include that file rather than defining its own enum?
> 
> History. include/dt-bindings/clock/tegra114-car.h didn't exist when
> clk-tegra114.c was written.

Right, but then someone created tegra114-car.h, but didn't bother to
follow through and update the clock driver:-(

Re: [PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 01:25:07PM +0200, Mark Zhang wrote:
> In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
> So change the clock init macro for these clocks from
> "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
> 
> Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
> remove this macro.
> 
> Signed-off-by: Mark Zhang <markz-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Acked-By: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

[PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 01:25:07PM +0200, Mark Zhang wrote:
> In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
> So change the clock init macro for these clocks from
> "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
> 
> Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
> remove this macro.
> 
> Signed-off-by: Mark Zhang <markz@nvidia.com>

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

Re: [PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 01:25:08PM +0200, Mark Zhang wrote:
> pll_m will be the parent of gr2d/gr3d if we don't do this.
> And because pll_m runs at a high rate so gr2d/gr3d will be
> unstable. So change the parent of them to pll_c2.
> 
> Signed-off-by: Mark Zhang <markz@nvidia.com>

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

[PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

[Peter De Schrijver]

On Wed, Aug 07, 2013 at 01:25:08PM +0200, Mark Zhang wrote:
> pll_m will be the parent of gr2d/gr3d if we don't do this.
> And because pll_m runs at a high rate so gr2d/gr3d will be
> unstable. So change the parent of them to pll_c2.
> 
> Signed-off-by: Mark Zhang <markz@nvidia.com>

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>