* [PATCH v2 0/4] Add AM65x ICSSG Ethernet support
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
Hi All,
This series adds support for ICSSG ethernet on AM65x SR2.0.
This series also enables TI_ICSSG_PRUETH as loadable kernel module.
This series is based on the latest next-20230921 linux-next.
This is the v2 of the series [v1]. This addresses comments made on v1.
Changes from v1 to v2:
*) Moved ICSSG2 nodes from k3-am654-base-board.dts to new overlay file
k3-am654-icssg2.dtso as asked by Andrew.
*) Renamed k3-am654-base-board.dts to k3-am654-common-board.dts
*) Added "Enable TI_ICSSG_PRUETH" patch to this series.
[v1] https://lore.kernel.org/all/20230911071245.2173520-1-danishanwar@ti.com/
Thanks and Regards,
MD Danish Anwar
MD Danish Anwar (4):
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
arm64: defconfig: Enable TI_ICSSG_PRUETH
arch/arm64/boot/dts/ti/Makefile | 6 +-
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 +++
...se-board.dts => k3-am654-common-board.dts} | 0
arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 +++++++++
arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
6 files changed, 483 insertions(+), 1 deletion(-)
rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
base-commit: 940fcc189c51032dd0282cbee4497542c982ac59
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 0/4] Add AM65x ICSSG Ethernet support
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
Hi All,
This series adds support for ICSSG ethernet on AM65x SR2.0.
This series also enables TI_ICSSG_PRUETH as loadable kernel module.
This series is based on the latest next-20230921 linux-next.
This is the v2 of the series [v1]. This addresses comments made on v1.
Changes from v1 to v2:
*) Moved ICSSG2 nodes from k3-am654-base-board.dts to new overlay file
k3-am654-icssg2.dtso as asked by Andrew.
*) Renamed k3-am654-base-board.dts to k3-am654-common-board.dts
*) Added "Enable TI_ICSSG_PRUETH" patch to this series.
[v1] https://lore.kernel.org/all/20230911071245.2173520-1-danishanwar@ti.com/
Thanks and Regards,
MD Danish Anwar
MD Danish Anwar (4):
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
arm64: defconfig: Enable TI_ICSSG_PRUETH
arch/arm64/boot/dts/ti/Makefile | 6 +-
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 +++
...se-board.dts => k3-am654-common-board.dts} | 0
arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 +++++++++
arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
6 files changed, 483 insertions(+), 1 deletion(-)
rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
base-commit: 940fcc189c51032dd0282cbee4497542c982ac59
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 6:09 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index bc460033a37a..fdb042d04ad9 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -1151,6 +1151,18 @@ icssg0_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1293,6 +1305,18 @@ icssg1_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1435,6 +1459,18 @@ icssg2_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index bc460033a37a..fdb042d04ad9 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -1151,6 +1151,18 @@ icssg0_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1293,6 +1305,18 @@ icssg1_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1435,6 +1459,18 @@ icssg2_iepclk_mux: iepclk-mux@30 {
};
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 6:09 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
ICSSG2 provides dual Gigabit Ethernet support.
For support SR2.0 ICSSG Ethernet firmware:
- provide different firmware blobs and use TX_PRU.
- IEP0 is used as PTP Hardware Clock and can only be used for one port.
- TX timestamp notification comes via INTC interrupt.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 4 +-
...se-board.dts => k3-am654-common-board.dts} | 0
arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
3 files changed, 148 insertions(+), 1 deletion(-)
rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index e7b8e2e7f083..85c91f5e832e 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
# Boards with AM65x SoC
-k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
+k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
+k3-am654-base-board-dtbs := k3-am654-common-board.dtb k3-am654-icssg2.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
similarity index 100%
rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
new file mode 100644
index 000000000000..e91c20947d05
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for IDK application board on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = &icssg2_emac0;
+ ethernet2 = &icssg2_emac1;
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG2 */
+ icssg2_eth: icssg2-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
+ <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,mii-rt = <&icssg2_mii_rt>;
+ ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
+
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc300>, /* egress slice 0 */
+ <&main_udmap 0xc301>, /* egress slice 0 */
+ <&main_udmap 0xc302>, /* egress slice 0 */
+ <&main_udmap 0xc303>, /* egress slice 0 */
+ <&main_udmap 0xc304>, /* egress slice 1 */
+ <&main_udmap 0xc305>, /* egress slice 1 */
+ <&main_udmap 0xc306>, /* egress slice 1 */
+ <&main_udmap 0xc307>, /* egress slice 1 */
+ <&main_udmap 0x4300>, /* ingress slice 0 */
+ <&main_udmap 0x4301>; /* ingress slice 1 */
+
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg2_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg2_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg2_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg2_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+
+ icssg2_mdio_pins_default: icssg2-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
+ AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
+ >;
+ };
+
+ icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
+ AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
+ AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
+ AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
+ AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
+ AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
+ AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
+ AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
+ AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
+ AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
+ AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
+ AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
+ AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
+ AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
+ AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
+ AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
+ AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
+ AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
+ AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
+ AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
+ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
+ >;
+ };
+};
+
+&icssg2_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg2_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.34.1
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
ICSSG2 provides dual Gigabit Ethernet support.
For support SR2.0 ICSSG Ethernet firmware:
- provide different firmware blobs and use TX_PRU.
- IEP0 is used as PTP Hardware Clock and can only be used for one port.
- TX timestamp notification comes via INTC interrupt.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 4 +-
...se-board.dts => k3-am654-common-board.dts} | 0
arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
3 files changed, 148 insertions(+), 1 deletion(-)
rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index e7b8e2e7f083..85c91f5e832e 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
# Boards with AM65x SoC
-k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
+k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
+k3-am654-base-board-dtbs := k3-am654-common-board.dtb k3-am654-icssg2.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
similarity index 100%
rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
new file mode 100644
index 000000000000..e91c20947d05
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for IDK application board on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = &icssg2_emac0;
+ ethernet2 = &icssg2_emac1;
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG2 */
+ icssg2_eth: icssg2-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
+ <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,mii-rt = <&icssg2_mii_rt>;
+ ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
+
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc300>, /* egress slice 0 */
+ <&main_udmap 0xc301>, /* egress slice 0 */
+ <&main_udmap 0xc302>, /* egress slice 0 */
+ <&main_udmap 0xc303>, /* egress slice 0 */
+ <&main_udmap 0xc304>, /* egress slice 1 */
+ <&main_udmap 0xc305>, /* egress slice 1 */
+ <&main_udmap 0xc306>, /* egress slice 1 */
+ <&main_udmap 0xc307>, /* egress slice 1 */
+ <&main_udmap 0x4300>, /* ingress slice 0 */
+ <&main_udmap 0x4301>; /* ingress slice 1 */
+
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg2_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg2_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg2_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg2_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+
+ icssg2_mdio_pins_default: icssg2-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
+ AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
+ >;
+ };
+
+ icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
+ AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
+ AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
+ AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
+ AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
+ AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
+ AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
+ AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
+ AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
+ AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
+ AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
+ AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
+ AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
+ AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
+ AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
+ AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
+ AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
+ AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
+ AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
+ AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
+ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
+ >;
+ };
+};
+
+&icssg2_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg2_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 6:09 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The IDK application board has 4 Gigabit Ethernet ports.
This patch adds support for the 4 Gigabit Ethernet ports
which are provided by ICSSG0 and ICSSG1.
The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
2 files changed, 298 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 85c91f5e832e..ff3f90bf0333 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
# Boards with J7200 SoC
@@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-am654-common-board += -@
diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
new file mode 100644
index 000000000000..7aa10827ed65
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for IDK application board on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
+ ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
+ ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
+ ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG0 */
+ icssg0_eth: icssg0-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg0_mii_g_rt>;
+ ti,mii-rt = <&icssg0_mii_rt>;
+ ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
+
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc100>, /* egress slice 0 */
+ <&main_udmap 0xc101>, /* egress slice 0 */
+ <&main_udmap 0xc102>, /* egress slice 0 */
+ <&main_udmap 0xc103>, /* egress slice 0 */
+ <&main_udmap 0xc104>, /* egress slice 1 */
+ <&main_udmap 0xc105>, /* egress slice 1 */
+ <&main_udmap 0xc106>, /* egress slice 1 */
+ <&main_udmap 0xc107>, /* egress slice 1 */
+
+ <&main_udmap 0x4100>, /* ingress slice 0 */
+ <&main_udmap 0x4101>, /* ingress slice 1 */
+ <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
+ <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg0_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg0_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg0_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg0_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG1 */
+ icssg1_eth: icssg1-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg1_mii_g_rt>;
+ ti,mii-rt = <&icssg1_mii_rt>;
+ ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
+
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc200>, /* egress slice 0 */
+ <&main_udmap 0xc201>, /* egress slice 0 */
+ <&main_udmap 0xc202>, /* egress slice 0 */
+ <&main_udmap 0xc203>, /* egress slice 0 */
+ <&main_udmap 0xc204>, /* egress slice 1 */
+ <&main_udmap 0xc205>, /* egress slice 1 */
+ <&main_udmap 0xc206>, /* egress slice 1 */
+ <&main_udmap 0xc207>, /* egress slice 1 */
+
+ <&main_udmap 0x4200>, /* ingress slice 0 */
+ <&main_udmap 0x4201>, /* ingress slice 1 */
+ <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
+ <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg1_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg1_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg1_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg1_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+
+ icssg0_mdio_pins_default: icssg0-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
+ AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
+ >;
+ };
+
+ icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
+ AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
+ AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
+ AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
+ AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
+ AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
+ AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
+ AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
+ AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
+ AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
+ AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
+ AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
+ AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
+ AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
+ AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
+ AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
+ AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
+ AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
+ AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
+ AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
+ AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+ >;
+ };
+
+ icssg0_iep0_pins_default: icssg0-iep0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
+ >;
+ };
+
+ icssg1_mdio_pins_default: icssg1-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
+ AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
+ >;
+ };
+
+ icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
+ AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
+ AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
+ AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
+ AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
+ AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
+ AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
+ AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
+ AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
+ AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
+ AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
+ AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
+ AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
+ AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
+ AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
+ AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
+ AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
+ AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
+ AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
+ AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
+ AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
+ >;
+ };
+
+ icssg1_iep0_pins_default: icssg1-iep0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
+ >;
+ };
+};
+
+&icssg0_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg0_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg0_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&icssg0_iep0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_iep0_pins_default>;
+};
+
+&icssg1_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg1_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&icssg1_iep0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_iep0_pins_default>;
+};
--
2.34.1
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^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The IDK application board has 4 Gigabit Ethernet ports.
This patch adds support for the 4 Gigabit Ethernet ports
which are provided by ICSSG0 and ICSSG1.
The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
2 files changed, 298 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 85c91f5e832e..ff3f90bf0333 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
# Boards with J7200 SoC
@@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-am654-common-board += -@
diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
new file mode 100644
index 000000000000..7aa10827ed65
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for IDK application board on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
+ ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
+ ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
+ ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG0 */
+ icssg0_eth: icssg0-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg0_mii_g_rt>;
+ ti,mii-rt = <&icssg0_mii_rt>;
+ ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
+
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc100>, /* egress slice 0 */
+ <&main_udmap 0xc101>, /* egress slice 0 */
+ <&main_udmap 0xc102>, /* egress slice 0 */
+ <&main_udmap 0xc103>, /* egress slice 0 */
+ <&main_udmap 0xc104>, /* egress slice 1 */
+ <&main_udmap 0xc105>, /* egress slice 1 */
+ <&main_udmap 0xc106>, /* egress slice 1 */
+ <&main_udmap 0xc107>, /* egress slice 1 */
+
+ <&main_udmap 0x4100>, /* ingress slice 0 */
+ <&main_udmap 0x4101>, /* ingress slice 1 */
+ <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
+ <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg0_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg0_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg0_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg0_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+ /* Dual Ethernet application node on PRU-ICSSG1 */
+ icssg1_eth: icssg1-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg1_mii_g_rt>;
+ ti,mii-rt = <&icssg1_mii_rt>;
+ ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
+
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc200>, /* egress slice 0 */
+ <&main_udmap 0xc201>, /* egress slice 0 */
+ <&main_udmap 0xc202>, /* egress slice 0 */
+ <&main_udmap 0xc203>, /* egress slice 0 */
+ <&main_udmap 0xc204>, /* egress slice 1 */
+ <&main_udmap 0xc205>, /* egress slice 1 */
+ <&main_udmap 0xc206>, /* egress slice 1 */
+ <&main_udmap 0xc207>, /* egress slice 1 */
+
+ <&main_udmap 0x4200>, /* ingress slice 0 */
+ <&main_udmap 0x4201>, /* ingress slice 1 */
+ <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
+ <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg1_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg1_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg1_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg1_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+
+ icssg0_mdio_pins_default: icssg0-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
+ AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
+ >;
+ };
+
+ icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
+ AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
+ AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
+ AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
+ AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
+ AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
+ AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
+ AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
+ AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
+ AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
+ AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
+ AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
+ AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
+ AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
+ AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
+ AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
+ AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
+ AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
+ AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
+ AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
+ AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+ >;
+ };
+
+ icssg0_iep0_pins_default: icssg0-iep0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
+ >;
+ };
+
+ icssg1_mdio_pins_default: icssg1-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
+ AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
+ >;
+ };
+
+ icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
+ AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
+ AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
+ AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
+ AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
+ AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
+ AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
+ AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
+ AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
+ AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
+ AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
+ AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
+ AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
+ AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
+ AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
+ AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
+ AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
+ AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
+ AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
+ AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
+ AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
+ >;
+ };
+
+ icssg1_iep0_pins_default: icssg1-iep0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
+ >;
+ };
+};
+
+&icssg0_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg0_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg0_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&icssg0_iep0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_iep0_pins_default>;
+};
+
+&icssg1_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_mdio_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg1_phy1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&icssg1_iep0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_iep0_pins_default>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 4/4] arm64: defconfig: Enable TI_ICSSG_PRUETH
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 6:09 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The Programmable Real-time Unit and Industrial Communication Subsystem
Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI
K3 SoCs such as AM654x, AM64x. This subsystem is provided for the use
cases like implementation of custom peripheral interfaces, offloading of
tasks from the other processor cores of the SoC, etc.
Currently AM654x-EVM uses ICSSG driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5f77f5d1fe94..4e6e3cefcd67 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -368,6 +368,7 @@ CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_TEGRA=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
+CONFIG_TI_ICSSG_PRUETH=m
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
CONFIG_AQUANTIA_PHY=y
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 4/4] arm64: defconfig: Enable TI_ICSSG_PRUETH
@ 2023-09-21 6:09 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-21 6:09 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: afd, Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran,
danishanwar
The Programmable Real-time Unit and Industrial Communication Subsystem
Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI
K3 SoCs such as AM654x, AM64x. This subsystem is provided for the use
cases like implementation of custom peripheral interfaces, offloading of
tasks from the other processor cores of the SoC, etc.
Currently AM654x-EVM uses ICSSG driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5f77f5d1fe94..4e6e3cefcd67 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -368,6 +368,7 @@ CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_TEGRA=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
+CONFIG_TI_ICSSG_PRUETH=m
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
CONFIG_AQUANTIA_PHY=y
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 16:10 ` Andrew Lunn
-1 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2023-09-21 16:10 UTC (permalink / raw)
To: MD Danish Anwar
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
> + /* Dual Ethernet application node on PRU-ICSSG2 */
How relevant is "Dual Ethernet" here? You are talking of adding
switchdev support, and runtime swapping the application. All these
properties should be valid for the switch application as well?
In fact, you are describing hardware here, so the application should
not actually matter.
So maybe this comment should be:
Ethernet node on PRU-ICSSG2
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-21 16:10 ` Andrew Lunn
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2023-09-21 16:10 UTC (permalink / raw)
To: MD Danish Anwar
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
> + /* Dual Ethernet application node on PRU-ICSSG2 */
How relevant is "Dual Ethernet" here? You are talking of adding
switchdev support, and runtime swapping the application. All these
properties should be valid for the switch application as well?
In fact, you are describing hardware here, so the application should
not actually matter.
So maybe this comment should be:
Ethernet node on PRU-ICSSG2
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 16:14 ` Andrew Lunn
-1 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2023-09-21 16:14 UTC (permalink / raw)
To: MD Danish Anwar
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
> + /* Dual Ethernet application node on PRU-ICSSG0 */
> + /* Dual Ethernet application node on PRU-ICSSG1 */
Not relevant to this patch, but to the ongoing discussions around
adding switchdev support.
Are these two PRU-ICSSG instances completely separate? It is
physically impossible to combine these four ethernet ports in one
acceleration domain? It will always be two separate switches, and if
frames need to go from one switch to the other it happens in software?
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
@ 2023-09-21 16:14 ` Andrew Lunn
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2023-09-21 16:14 UTC (permalink / raw)
To: MD Danish Anwar
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
> + /* Dual Ethernet application node on PRU-ICSSG0 */
> + /* Dual Ethernet application node on PRU-ICSSG1 */
Not relevant to this patch, but to the ongoing discussions around
adding switchdev support.
Are these two PRU-ICSSG instances completely separate? It is
physically impossible to combine these four ethernet ports in one
acceleration domain? It will always be two separate switches, and if
frames need to go from one switch to the other it happens in software?
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 17:27 ` Andrew Davis
-1 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-21 17:27 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/21/23 1:09 AM, MD Danish Anwar wrote:
> ICSSG2 provides dual Gigabit Ethernet support.
>
> For support SR2.0 ICSSG Ethernet firmware:
> - provide different firmware blobs and use TX_PRU.
> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
> - TX timestamp notification comes via INTC interrupt.
>
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 4 +-
> ...se-board.dts => k3-am654-common-board.dts} | 0
> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
> 3 files changed, 148 insertions(+), 1 deletion(-)
> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index e7b8e2e7f083..85c91f5e832e 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>
> # Boards with AM65x SoC
> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does it work
to keep this line like before or is there some conflict having both enabled?
Andrew
> +k3-am654-base-board-dtbs := k3-am654-common-board.dtb k3-am654-icssg2.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
> similarity index 100%
> rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
> new file mode 100644
> index 000000000000..e91c20947d05
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT overlay for IDK application board on AM654 EVM
> + *
> + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet1 = &icssg2_emac0;
> + ethernet2 = &icssg2_emac1;
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG2 */
> + icssg2_eth: icssg2-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg2_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
> + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg2_mii_g_rt>;
> + ti,mii-rt = <&icssg2_mii_rt>;
> + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
> +
> + interrupt-parent = <&icssg2_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc300>, /* egress slice 0 */
> + <&main_udmap 0xc301>, /* egress slice 0 */
> + <&main_udmap 0xc302>, /* egress slice 0 */
> + <&main_udmap 0xc303>, /* egress slice 0 */
> + <&main_udmap 0xc304>, /* egress slice 1 */
> + <&main_udmap 0xc305>, /* egress slice 1 */
> + <&main_udmap 0xc306>, /* egress slice 1 */
> + <&main_udmap 0xc307>, /* egress slice 1 */
> + <&main_udmap 0x4300>, /* ingress slice 0 */
> + <&main_udmap 0x4301>; /* ingress slice 1 */
> +
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg2_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg2_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg2_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg2_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +};
> +
> +&main_pmx0 {
> +
> + icssg2_mdio_pins_default: icssg2-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
> + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
> + >;
> + };
> +
> + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
> + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
> + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
> + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
> + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
> + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
> + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
> + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
> + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
> + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
> + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
> + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
> + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
> + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
> + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
> + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
> + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
> + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
> + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
> + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
> + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
> + >;
> + };
> +};
> +
> +&icssg2_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg2_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg2_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg2_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-21 17:27 ` Andrew Davis
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-21 17:27 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/21/23 1:09 AM, MD Danish Anwar wrote:
> ICSSG2 provides dual Gigabit Ethernet support.
>
> For support SR2.0 ICSSG Ethernet firmware:
> - provide different firmware blobs and use TX_PRU.
> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
> - TX timestamp notification comes via INTC interrupt.
>
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 4 +-
> ...se-board.dts => k3-am654-common-board.dts} | 0
> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
> 3 files changed, 148 insertions(+), 1 deletion(-)
> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts => k3-am654-common-board.dts} (100%)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index e7b8e2e7f083..85c91f5e832e 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>
> # Boards with AM65x SoC
> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does it work
to keep this line like before or is there some conflict having both enabled?
Andrew
> +k3-am654-base-board-dtbs := k3-am654-common-board.dtb k3-am654-icssg2.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
> similarity index 100%
> rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
> new file mode 100644
> index 000000000000..e91c20947d05
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT overlay for IDK application board on AM654 EVM
> + *
> + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet1 = &icssg2_emac0;
> + ethernet2 = &icssg2_emac1;
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG2 */
> + icssg2_eth: icssg2-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg2_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
> + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg2_mii_g_rt>;
> + ti,mii-rt = <&icssg2_mii_rt>;
> + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
> +
> + interrupt-parent = <&icssg2_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc300>, /* egress slice 0 */
> + <&main_udmap 0xc301>, /* egress slice 0 */
> + <&main_udmap 0xc302>, /* egress slice 0 */
> + <&main_udmap 0xc303>, /* egress slice 0 */
> + <&main_udmap 0xc304>, /* egress slice 1 */
> + <&main_udmap 0xc305>, /* egress slice 1 */
> + <&main_udmap 0xc306>, /* egress slice 1 */
> + <&main_udmap 0xc307>, /* egress slice 1 */
> + <&main_udmap 0x4300>, /* ingress slice 0 */
> + <&main_udmap 0x4301>; /* ingress slice 1 */
> +
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg2_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg2_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg2_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg2_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +};
> +
> +&main_pmx0 {
> +
> + icssg2_mdio_pins_default: icssg2-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
> + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
> + >;
> + };
> +
> + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
> + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
> + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
> + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
> + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
> + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
> + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
> + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
> + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
> + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
> + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
> + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
> + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
> + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
> + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
> + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
> + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
> + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
> + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
> + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
> + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
> + >;
> + };
> +};
> +
> +&icssg2_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg2_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg2_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg2_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
2023-09-21 6:09 ` MD Danish Anwar
@ 2023-09-21 17:33 ` Andrew Davis
-1 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-21 17:33 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/21/23 1:09 AM, MD Danish Anwar wrote:
> The IDK application board has 4 Gigabit Ethernet ports.
>
> This patch adds support for the 4 Gigabit Ethernet ports
> which are provided by ICSSG0 and ICSSG1.
> The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
>
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
> 2 files changed, 298 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 85c91f5e832e..ff3f90bf0333 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
You'll want to apply this at build time to the base-board so this
overlay can be tested, no more orphan DTBO files[0]. So instead do:
k3-am654-idk-dtbs := k3-am654-base-board.dtb k3-am654-idk.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
Then you can drop the extra "+= -@" line below too, symbols
will be added for you.
Andrew
[0] https://lore.kernel.org/all/CAL_Jsq+GR3hP6hFvFn2z5aXvSXnh9butD3aKZ-y_XJgx0_YPTw@mail.gmail.com/
> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>
> # Boards with J7200 SoC
> @@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
> DTC_FLAGS_k3-j721e-common-proc-board += -@
> DTC_FLAGS_k3-j721s2-common-proc-board += -@
> +DTC_FLAGS_k3-am654-common-board += -@
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
> new file mode 100644
> index 000000000000..7aa10827ed65
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT overlay for IDK application board on AM654 EVM
> + *
> + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
> + ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
> + ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
> + ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG0 */
> + icssg0_eth: icssg0-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg0_mii_g_rt>;
> + ti,mii-rt = <&icssg0_mii_rt>;
> + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
> +
> + interrupt-parent = <&icssg0_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc100>, /* egress slice 0 */
> + <&main_udmap 0xc101>, /* egress slice 0 */
> + <&main_udmap 0xc102>, /* egress slice 0 */
> + <&main_udmap 0xc103>, /* egress slice 0 */
> + <&main_udmap 0xc104>, /* egress slice 1 */
> + <&main_udmap 0xc105>, /* egress slice 1 */
> + <&main_udmap 0xc106>, /* egress slice 1 */
> + <&main_udmap 0xc107>, /* egress slice 1 */
> +
> + <&main_udmap 0x4100>, /* ingress slice 0 */
> + <&main_udmap 0x4101>, /* ingress slice 1 */
> + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
> + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg0_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg0_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg0_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg0_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG1 */
> + icssg1_eth: icssg1-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg1_mii_g_rt>;
> + ti,mii-rt = <&icssg1_mii_rt>;
> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
> +
> + interrupt-parent = <&icssg1_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc200>, /* egress slice 0 */
> + <&main_udmap 0xc201>, /* egress slice 0 */
> + <&main_udmap 0xc202>, /* egress slice 0 */
> + <&main_udmap 0xc203>, /* egress slice 0 */
> + <&main_udmap 0xc204>, /* egress slice 1 */
> + <&main_udmap 0xc205>, /* egress slice 1 */
> + <&main_udmap 0xc206>, /* egress slice 1 */
> + <&main_udmap 0xc207>, /* egress slice 1 */
> +
> + <&main_udmap 0x4200>, /* ingress slice 0 */
> + <&main_udmap 0x4201>, /* ingress slice 1 */
> + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
> + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg1_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg1_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg1_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg1_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +};
> +
> +&main_pmx0 {
> +
> + icssg0_mdio_pins_default: icssg0-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
> + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
> + >;
> + };
> +
> + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
> + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
> + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
> + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
> + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
> + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
> + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
> + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
> + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
> + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
> + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
> + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
> + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
> + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
> + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
> + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
> + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
> + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
> + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
> + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
> + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
> + >;
> + };
> +
> + icssg0_iep0_pins_default: icssg0-iep0-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
> + >;
> + };
> +
> + icssg1_mdio_pins_default: icssg1-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
> + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
> + >;
> + };
> +
> + icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
> + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
> + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
> + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
> + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
> + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
> + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
> + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
> + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
> + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
> + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
> + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
> + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
> + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
> + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
> + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
> + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
> + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
> + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
> + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
> + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
> + >;
> + };
> +
> + icssg1_iep0_pins_default: icssg1-iep0-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
> + >;
> + };
> +};
> +
> +&icssg0_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg0_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg0_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
> +
> +&icssg0_iep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_iep0_pins_default>;
> +};
> +
> +&icssg1_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg1_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg1_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
> +
> +&icssg1_iep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_iep0_pins_default>;
> +};
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
@ 2023-09-21 17:33 ` Andrew Davis
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-21 17:33 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/21/23 1:09 AM, MD Danish Anwar wrote:
> The IDK application board has 4 Gigabit Ethernet ports.
>
> This patch adds support for the 4 Gigabit Ethernet ports
> which are provided by ICSSG0 and ICSSG1.
> The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
>
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
> 2 files changed, 298 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 85c91f5e832e..ff3f90bf0333 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
You'll want to apply this at build time to the base-board so this
overlay can be tested, no more orphan DTBO files[0]. So instead do:
k3-am654-idk-dtbs := k3-am654-base-board.dtb k3-am654-idk.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
Then you can drop the extra "+= -@" line below too, symbols
will be added for you.
Andrew
[0] https://lore.kernel.org/all/CAL_Jsq+GR3hP6hFvFn2z5aXvSXnh9butD3aKZ-y_XJgx0_YPTw@mail.gmail.com/
> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>
> # Boards with J7200 SoC
> @@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
> DTC_FLAGS_k3-j721e-common-proc-board += -@
> DTC_FLAGS_k3-j721s2-common-proc-board += -@
> +DTC_FLAGS_k3-am654-common-board += -@
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
> new file mode 100644
> index 000000000000..7aa10827ed65
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT overlay for IDK application board on AM654 EVM
> + *
> + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
> + ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
> + ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
> + ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG0 */
> + icssg0_eth: icssg0-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg0_mii_g_rt>;
> + ti,mii-rt = <&icssg0_mii_rt>;
> + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
> +
> + interrupt-parent = <&icssg0_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc100>, /* egress slice 0 */
> + <&main_udmap 0xc101>, /* egress slice 0 */
> + <&main_udmap 0xc102>, /* egress slice 0 */
> + <&main_udmap 0xc103>, /* egress slice 0 */
> + <&main_udmap 0xc104>, /* egress slice 1 */
> + <&main_udmap 0xc105>, /* egress slice 1 */
> + <&main_udmap 0xc106>, /* egress slice 1 */
> + <&main_udmap 0xc107>, /* egress slice 1 */
> +
> + <&main_udmap 0x4100>, /* ingress slice 0 */
> + <&main_udmap 0x4101>, /* ingress slice 1 */
> + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
> + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg0_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg0_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg0_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg0_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +
> + /* Dual Ethernet application node on PRU-ICSSG1 */
> + icssg1_eth: icssg1-eth {
> + compatible = "ti,am654-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_rgmii_pins_default>;
> + sram = <&msmc_ram>;
> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg1_mii_g_rt>;
> + ti,mii-rt = <&icssg1_mii_rt>;
> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
> +
> + interrupt-parent = <&icssg1_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_udmap 0xc200>, /* egress slice 0 */
> + <&main_udmap 0xc201>, /* egress slice 0 */
> + <&main_udmap 0xc202>, /* egress slice 0 */
> + <&main_udmap 0xc203>, /* egress slice 0 */
> + <&main_udmap 0xc204>, /* egress slice 1 */
> + <&main_udmap 0xc205>, /* egress slice 1 */
> + <&main_udmap 0xc206>, /* egress slice 1 */
> + <&main_udmap 0xc207>, /* egress slice 1 */
> +
> + <&main_udmap 0x4200>, /* ingress slice 0 */
> + <&main_udmap 0x4201>, /* ingress slice 1 */
> + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
> + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + icssg1_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg1_phy0>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + icssg1_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg1_phy1>;
> + phy-mode = "rgmii-id";
> + ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +};
> +
> +&main_pmx0 {
> +
> + icssg0_mdio_pins_default: icssg0-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
> + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
> + >;
> + };
> +
> + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
> + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
> + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
> + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
> + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
> + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
> + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
> + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
> + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
> + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
> + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
> + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
> + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
> + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
> + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
> + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
> + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
> + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
> + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
> + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
> + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
> + >;
> + };
> +
> + icssg0_iep0_pins_default: icssg0-iep0-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
> + >;
> + };
> +
> + icssg1_mdio_pins_default: icssg1-mdio-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
> + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
> + >;
> + };
> +
> + icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
> + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
> + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
> + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
> + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
> + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
> + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
> + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
> + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
> + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
> + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
> + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
> +
> + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
> + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
> + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
> + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
> + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
> + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
> + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
> + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
> + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
> + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
> + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
> + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
> + >;
> + };
> +
> + icssg1_iep0_pins_default: icssg1-iep0-default-pins {
> + pinctrl-single,pins = <
> + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
> + >;
> + };
> +};
> +
> +&icssg0_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg0_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg0_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
> +
> +&icssg0_iep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_iep0_pins_default>;
> +};
> +
> +&icssg1_mdio {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg1_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +
> + icssg1_phy1: ethernet-phy@3 {
> + reg = <3>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + };
> +};
> +
> +&icssg1_iep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg1_iep0_pins_default>;
> +};
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-21 17:27 ` Andrew Davis
@ 2023-09-22 4:22 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:22 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 22:57, Andrew Davis wrote:
> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>> ICSSG2 provides dual Gigabit Ethernet support.
>>
>> For support SR2.0 ICSSG Ethernet firmware:
>> - provide different firmware blobs and use TX_PRU.
>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>> - TX timestamp notification comes via INTC interrupt.
>>
>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>> ...se-board.dts => k3-am654-common-board.dts} | 0
>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>> 3 files changed, 148 insertions(+), 1 deletion(-)
>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>> k3-am654-common-board.dts} (100%)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>> b/arch/arm64/boot/dts/ti/Makefile
>> index e7b8e2e7f083..85c91f5e832e 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>> # Boards with AM65x SoC
>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
> it work
> to keep this line like before or is there some conflict having both
> enabled?
>
I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
icssg2 support as well. But I haven't tested the combination of
base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
> Andrew
>
>> +k3-am654-base-board-dtbs := k3-am654-common-board.dtb
>> k3-am654-icssg2.dtbo
>> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
>> b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
>> similarity index 100%
>> rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
>> rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> new file mode 100644
>> index 000000000000..e91c20947d05
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> @@ -0,0 +1,145 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * DT overlay for IDK application board on AM654 EVM
>> + *
>> + * Copyright (C) 2018-2023 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/net/ti-dp83867.h>
>> +#include "k3-pinctrl.h"
>> +
>> +&{/} {
>> + aliases {
>> + ethernet1 = &icssg2_emac0;
>> + ethernet2 = &icssg2_emac1;
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG2 */
>> + icssg2_eth: icssg2-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg2_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
>> + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg2_mii_g_rt>;
>> + ti,mii-rt = <&icssg2_mii_rt>;
>> + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
>> +
>> + interrupt-parent = <&icssg2_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc300>, /* egress slice 0 */
>> + <&main_udmap 0xc301>, /* egress slice 0 */
>> + <&main_udmap 0xc302>, /* egress slice 0 */
>> + <&main_udmap 0xc303>, /* egress slice 0 */
>> + <&main_udmap 0xc304>, /* egress slice 1 */
>> + <&main_udmap 0xc305>, /* egress slice 1 */
>> + <&main_udmap 0xc306>, /* egress slice 1 */
>> + <&main_udmap 0xc307>, /* egress slice 1 */
>> + <&main_udmap 0x4300>, /* ingress slice 0 */
>> + <&main_udmap 0x4301>; /* ingress slice 1 */
>> +
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg2_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg2_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg2_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg2_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +};
>> +
>> +&main_pmx0 {
>> +
>> + icssg2_mdio_pins_default: icssg2-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19)
>> PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
>> + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15)
>> PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15)
>> PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
>> + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16)
>> PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
>> + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17)
>> PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
>> + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14)
>> PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
>> + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15)
>> PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
>> + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14)
>> PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
>> + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15)
>> PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
>> + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14)
>> PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
>> + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14)
>> PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
>> + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17)
>> PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15)
>> PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
>> + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14)
>> PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18)
>> PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
>> + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18)
>> PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
>> + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17)
>> PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
>> + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18)
>> PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16)
>> PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
>> + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16)
>> PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
>> + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16)
>> PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
>> + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16)
>> PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
>> + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16)
>> PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
>> + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17)
>> PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17)
>> PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
>> + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17)
>> PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
>> + >;
>> + };
>> +};
>> +
>> +&icssg2_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg2_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg2_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg2_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
--
Thanks and Regards,
Danish
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-22 4:22 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:22 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 22:57, Andrew Davis wrote:
> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>> ICSSG2 provides dual Gigabit Ethernet support.
>>
>> For support SR2.0 ICSSG Ethernet firmware:
>> - provide different firmware blobs and use TX_PRU.
>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>> - TX timestamp notification comes via INTC interrupt.
>>
>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>> ...se-board.dts => k3-am654-common-board.dts} | 0
>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>> 3 files changed, 148 insertions(+), 1 deletion(-)
>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>> k3-am654-common-board.dts} (100%)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>> b/arch/arm64/boot/dts/ti/Makefile
>> index e7b8e2e7f083..85c91f5e832e 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>> # Boards with AM65x SoC
>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
> it work
> to keep this line like before or is there some conflict having both
> enabled?
>
I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
icssg2 support as well. But I haven't tested the combination of
base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
> Andrew
>
>> +k3-am654-base-board-dtbs := k3-am654-common-board.dtb
>> k3-am654-icssg2.dtbo
>> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
>> b/arch/arm64/boot/dts/ti/k3-am654-common-board.dts
>> similarity index 100%
>> rename from arch/arm64/boot/dts/ti/k3-am654-base-board.dts
>> rename to arch/arm64/boot/dts/ti/k3-am654-common-board.dts
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> new file mode 100644
>> index 000000000000..e91c20947d05
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>> @@ -0,0 +1,145 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * DT overlay for IDK application board on AM654 EVM
>> + *
>> + * Copyright (C) 2018-2023 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/net/ti-dp83867.h>
>> +#include "k3-pinctrl.h"
>> +
>> +&{/} {
>> + aliases {
>> + ethernet1 = &icssg2_emac0;
>> + ethernet2 = &icssg2_emac1;
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG2 */
>> + icssg2_eth: icssg2-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg2_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
>> + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg2_mii_g_rt>;
>> + ti,mii-rt = <&icssg2_mii_rt>;
>> + ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
>> +
>> + interrupt-parent = <&icssg2_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc300>, /* egress slice 0 */
>> + <&main_udmap 0xc301>, /* egress slice 0 */
>> + <&main_udmap 0xc302>, /* egress slice 0 */
>> + <&main_udmap 0xc303>, /* egress slice 0 */
>> + <&main_udmap 0xc304>, /* egress slice 1 */
>> + <&main_udmap 0xc305>, /* egress slice 1 */
>> + <&main_udmap 0xc306>, /* egress slice 1 */
>> + <&main_udmap 0xc307>, /* egress slice 1 */
>> + <&main_udmap 0x4300>, /* ingress slice 0 */
>> + <&main_udmap 0x4301>; /* ingress slice 1 */
>> +
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg2_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg2_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg2_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg2_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +};
>> +
>> +&main_pmx0 {
>> +
>> + icssg2_mdio_pins_default: icssg2-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19)
>> PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
>> + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15)
>> PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15)
>> PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
>> + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16)
>> PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
>> + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17)
>> PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
>> + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14)
>> PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
>> + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15)
>> PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
>> + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14)
>> PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
>> + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15)
>> PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
>> + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14)
>> PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
>> + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14)
>> PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
>> + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17)
>> PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15)
>> PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
>> + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14)
>> PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18)
>> PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
>> + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18)
>> PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
>> + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17)
>> PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
>> + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18)
>> PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16)
>> PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
>> + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16)
>> PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
>> + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16)
>> PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
>> + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16)
>> PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
>> + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16)
>> PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
>> + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17)
>> PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17)
>> PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
>> + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17)
>> PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
>> + >;
>> + };
>> +};
>> +
>> +&icssg2_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg2_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg2_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg2_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
--
Thanks and Regards,
Danish
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
2023-09-21 17:33 ` Andrew Davis
@ 2023-09-22 4:24 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:24 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 23:03, Andrew Davis wrote:
> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>> The IDK application board has 4 Gigabit Ethernet ports.
>>
>> This patch adds support for the 4 Gigabit Ethernet ports
>> which are provided by ICSSG0 and ICSSG1.
>> The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
>>
>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/Makefile | 2 +
>> arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
>> 2 files changed, 298 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>> b/arch/arm64/boot/dts/ti/Makefile
>> index 85c91f5e832e..ff3f90bf0333 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) +=
>> k3-am6548-iot2050-advanced-m2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
>
> You'll want to apply this at build time to the base-board so this
> overlay can be tested, no more orphan DTBO files[0]. So instead do:
>
I was not aware about having orphan DTBO files. I will do the suggested
change.
> k3-am654-idk-dtbs := k3-am654-base-board.dtb k3-am654-idk.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
>
> Then you can drop the extra "+= -@" line below too, symbols
> will be added for you.
>
> Andrew
>
> [0]
> https://lore.kernel.org/all/CAL_Jsq+GR3hP6hFvFn2z5aXvSXnh9butD3aKZ-y_XJgx0_YPTw@mail.gmail.com/
>
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>> # Boards with J7200 SoC
>> @@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
>> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
>> DTC_FLAGS_k3-j721e-common-proc-board += -@
>> DTC_FLAGS_k3-j721s2-common-proc-board += -@
>> +DTC_FLAGS_k3-am654-common-board += -@
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> new file mode 100644
>> index 000000000000..7aa10827ed65
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> @@ -0,0 +1,296 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * DT overlay for IDK application board on AM654 EVM
>> + *
>> + * Copyright (C) 2018-2023 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/net/ti-dp83867.h>
>> +#include "k3-pinctrl.h"
>> +
>> +&{/} {
>> + aliases {
>> + ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
>> + ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
>> + ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
>> + ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG0 */
>> + icssg0_eth: icssg0-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>,
>> <&rtu0_1>, <&tx_pru0_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg0_mii_g_rt>;
>> + ti,mii-rt = <&icssg0_mii_rt>;
>> + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
>> +
>> + interrupt-parent = <&icssg0_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc100>, /* egress slice 0 */
>> + <&main_udmap 0xc101>, /* egress slice 0 */
>> + <&main_udmap 0xc102>, /* egress slice 0 */
>> + <&main_udmap 0xc103>, /* egress slice 0 */
>> + <&main_udmap 0xc104>, /* egress slice 1 */
>> + <&main_udmap 0xc105>, /* egress slice 1 */
>> + <&main_udmap 0xc106>, /* egress slice 1 */
>> + <&main_udmap 0xc107>, /* egress slice 1 */
>> +
>> + <&main_udmap 0x4100>, /* ingress slice 0 */
>> + <&main_udmap 0x4101>, /* ingress slice 1 */
>> + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
>> + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> +
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg0_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg0_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg0_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg0_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG1 */
>> + icssg1_eth: icssg1-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>,
>> <&rtu1_1>, <&tx_pru1_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg1_mii_g_rt>;
>> + ti,mii-rt = <&icssg1_mii_rt>;
>> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
>> +
>> + interrupt-parent = <&icssg1_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc200>, /* egress slice 0 */
>> + <&main_udmap 0xc201>, /* egress slice 0 */
>> + <&main_udmap 0xc202>, /* egress slice 0 */
>> + <&main_udmap 0xc203>, /* egress slice 0 */
>> + <&main_udmap 0xc204>, /* egress slice 1 */
>> + <&main_udmap 0xc205>, /* egress slice 1 */
>> + <&main_udmap 0xc206>, /* egress slice 1 */
>> + <&main_udmap 0xc207>, /* egress slice 1 */
>> +
>> + <&main_udmap 0x4200>, /* ingress slice 0 */
>> + <&main_udmap 0x4201>, /* ingress slice 1 */
>> + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
>> + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> +
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg1_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg1_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg1_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg1_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +};
>> +
>> +&main_pmx0 {
>> +
>> + icssg0_mdio_pins_default: icssg0-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26)
>> PRG0_MDIO0_MDIO */
>> + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28)
>> PRG0_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28)
>> PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
>> + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28)
>> PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
>> + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27)
>> PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
>> + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26)
>> PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
>> + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25)
>> PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
>> + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25)
>> PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
>> + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24)
>> PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
>> + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27)
>> PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
>> + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24)
>> PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
>> + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24)
>> PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27)
>> PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
>> + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25)
>> PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24)
>> PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
>> + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25)
>> PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
>> + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24)
>> PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
>> + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27)
>> PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27)
>> PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
>> + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26)
>> PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
>> + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26)
>> PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
>> + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24)
>> PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
>> + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28)
>> PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
>> + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25)
>> PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25)
>> PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
>> + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24)
>> PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
>> + >;
>> + };
>> +
>> + icssg0_iep0_pins_default: icssg0-iep0-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24)
>> PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
>> + >;
>> + };
>> +
>> + icssg1_mdio_pins_default: icssg1-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18)
>> PRG1_MDIO0_MDIO */
>> + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18)
>> PRG1_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24)
>> PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
>> + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23)
>> PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
>> + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21)
>> PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
>> + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22)
>> PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
>> + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20)
>> PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
>> + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19)
>> PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
>> + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19)
>> PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
>> + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19)
>> PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
>> + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19)
>> PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
>> + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20)
>> PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22)
>> PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
>> + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21)
>> PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22)
>> PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
>> + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24)
>> PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
>> + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23)
>> PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
>> + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21)
>> PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20)
>> PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
>> + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21)
>> PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
>> + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20)
>> PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
>> + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19)
>> PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
>> + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20)
>> PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
>> + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21)
>> PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22)
>> PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
>> + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23)
>> PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
>> + >;
>> + };
>> +
>> + icssg1_iep0_pins_default: icssg1-iep0-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26)
>> PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
>> + >;
>> + };
>> +};
>> +
>> +&icssg0_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg0_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg0_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
>> +
>> +&icssg0_iep0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_iep0_pins_default>;
>> +};
>> +
>> +&icssg1_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg1_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg1_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
>> +
>> +&icssg1_iep0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_iep0_pins_default>;
>> +};
--
Thanks and Regards,
Danish
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
@ 2023-09-22 4:24 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:24 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 23:03, Andrew Davis wrote:
> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>> The IDK application board has 4 Gigabit Ethernet ports.
>>
>> This patch adds support for the 4 Gigabit Ethernet ports
>> which are provided by ICSSG0 and ICSSG1.
>> The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card.
>>
>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/Makefile | 2 +
>> arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++
>> 2 files changed, 298 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>> b/arch/arm64/boot/dts/ti/Makefile
>> index 85c91f5e832e..ff3f90bf0333 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) +=
>> k3-am6548-iot2050-advanced-m2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-common-board.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtbo
>
> You'll want to apply this at build time to the base-board so this
> overlay can be tested, no more orphan DTBO files[0]. So instead do:
>
I was not aware about having orphan DTBO files. I will do the suggested
change.
> k3-am654-idk-dtbs := k3-am654-base-board.dtb k3-am654-idk.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
>
> Then you can drop the extra "+= -@" line below too, symbols
> will be added for you.
>
> Andrew
>
> [0]
> https://lore.kernel.org/all/CAL_Jsq+GR3hP6hFvFn2z5aXvSXnh9butD3aKZ-y_XJgx0_YPTw@mail.gmail.com/
>
>> dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
>> # Boards with J7200 SoC
>> @@ -79,3 +80,4 @@ DTC_FLAGS_k3-am62-lp-sk += -@
>> DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
>> DTC_FLAGS_k3-j721e-common-proc-board += -@
>> DTC_FLAGS_k3-j721s2-common-proc-board += -@
>> +DTC_FLAGS_k3-am654-common-board += -@
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> new file mode 100644
>> index 000000000000..7aa10827ed65
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
>> @@ -0,0 +1,296 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * DT overlay for IDK application board on AM654 EVM
>> + *
>> + * Copyright (C) 2018-2023 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/net/ti-dp83867.h>
>> +#include "k3-pinctrl.h"
>> +
>> +&{/} {
>> + aliases {
>> + ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
>> + ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
>> + ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
>> + ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG0 */
>> + icssg0_eth: icssg0-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>,
>> <&rtu0_1>, <&tx_pru0_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg0_mii_g_rt>;
>> + ti,mii-rt = <&icssg0_mii_rt>;
>> + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
>> +
>> + interrupt-parent = <&icssg0_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc100>, /* egress slice 0 */
>> + <&main_udmap 0xc101>, /* egress slice 0 */
>> + <&main_udmap 0xc102>, /* egress slice 0 */
>> + <&main_udmap 0xc103>, /* egress slice 0 */
>> + <&main_udmap 0xc104>, /* egress slice 1 */
>> + <&main_udmap 0xc105>, /* egress slice 1 */
>> + <&main_udmap 0xc106>, /* egress slice 1 */
>> + <&main_udmap 0xc107>, /* egress slice 1 */
>> +
>> + <&main_udmap 0x4100>, /* ingress slice 0 */
>> + <&main_udmap 0x4101>, /* ingress slice 1 */
>> + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
>> + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> +
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg0_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg0_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg0_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg0_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +
>> + /* Dual Ethernet application node on PRU-ICSSG1 */
>> + icssg1_eth: icssg1-eth {
>> + compatible = "ti,am654-icssg-prueth";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_rgmii_pins_default>;
>> + sram = <&msmc_ram>;
>> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>,
>> <&rtu1_1>, <&tx_pru1_1>;
>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
>> +
>> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
>> + <2>,
>> + <2>,
>> + <2>, /* MII mode */
>> + <2>,
>> + <2>;
>> +
>> + ti,mii-g-rt = <&icssg1_mii_g_rt>;
>> + ti,mii-rt = <&icssg1_mii_rt>;
>> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
>> +
>> + interrupt-parent = <&icssg1_intc>;
>> + interrupts = <24 0 2>, <25 1 3>;
>> + interrupt-names = "tx_ts0", "tx_ts1";
>> +
>> + dmas = <&main_udmap 0xc200>, /* egress slice 0 */
>> + <&main_udmap 0xc201>, /* egress slice 0 */
>> + <&main_udmap 0xc202>, /* egress slice 0 */
>> + <&main_udmap 0xc203>, /* egress slice 0 */
>> + <&main_udmap 0xc204>, /* egress slice 1 */
>> + <&main_udmap 0xc205>, /* egress slice 1 */
>> + <&main_udmap 0xc206>, /* egress slice 1 */
>> + <&main_udmap 0xc207>, /* egress slice 1 */
>> +
>> + <&main_udmap 0x4200>, /* ingress slice 0 */
>> + <&main_udmap 0x4201>, /* ingress slice 1 */
>> + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
>> + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
>> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
>> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
>> + "rx0", "rx1";
>> +
>> + ethernet-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + icssg1_emac0: port@0 {
>> + reg = <0>;
>> + phy-handle = <&icssg1_phy0>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + icssg1_emac1: port@1 {
>> + reg = <1>;
>> + phy-handle = <&icssg1_phy1>;
>> + phy-mode = "rgmii-id";
>> + ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
>> + /* Filled in by bootloader */
>> + local-mac-address = [00 00 00 00 00 00];
>> + };
>> + };
>> + };
>> +};
>> +
>> +&main_pmx0 {
>> +
>> + icssg0_mdio_pins_default: icssg0-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26)
>> PRG0_MDIO0_MDIO */
>> + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28)
>> PRG0_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28)
>> PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
>> + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28)
>> PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
>> + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27)
>> PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
>> + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26)
>> PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
>> + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25)
>> PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
>> + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25)
>> PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
>> + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24)
>> PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
>> + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27)
>> PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
>> + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24)
>> PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
>> + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24)
>> PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27)
>> PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
>> + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25)
>> PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24)
>> PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
>> + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25)
>> PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
>> + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24)
>> PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
>> + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27)
>> PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27)
>> PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
>> + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26)
>> PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
>> + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26)
>> PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
>> + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24)
>> PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
>> + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28)
>> PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
>> + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25)
>> PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25)
>> PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
>> + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24)
>> PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
>> + >;
>> + };
>> +
>> + icssg0_iep0_pins_default: icssg0-iep0-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24)
>> PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
>> + >;
>> + };
>> +
>> + icssg1_mdio_pins_default: icssg1-mdio-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18)
>> PRG1_MDIO0_MDIO */
>> + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18)
>> PRG1_MDIO0_MDC */
>> + >;
>> + };
>> +
>> + icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24)
>> PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
>> + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23)
>> PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
>> + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21)
>> PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
>> + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22)
>> PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
>> + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20)
>> PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
>> + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19)
>> PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
>> + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19)
>> PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
>> + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19)
>> PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
>> + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19)
>> PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
>> + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20)
>> PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
>> + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22)
>> PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
>> + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21)
>> PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
>> +
>> + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22)
>> PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
>> + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24)
>> PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
>> + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23)
>> PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
>> + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21)
>> PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
>> + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20)
>> PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
>> + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21)
>> PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
>> + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20)
>> PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
>> + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19)
>> PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
>> + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20)
>> PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
>> + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21)
>> PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
>> + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22)
>> PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
>> + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23)
>> PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
>> + >;
>> + };
>> +
>> + icssg1_iep0_pins_default: icssg1-iep0-default-pins {
>> + pinctrl-single,pins = <
>> + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26)
>> PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
>> + >;
>> + };
>> +};
>> +
>> +&icssg0_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg0_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg0_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
>> +
>> +&icssg0_iep0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg0_iep0_pins_default>;
>> +};
>> +
>> +&icssg1_mdio {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_mdio_pins_default>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + icssg1_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +
>> + icssg1_phy1: ethernet-phy@3 {
>> + reg = <3>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + };
>> +};
>> +
>> +&icssg1_iep0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&icssg1_iep0_pins_default>;
>> +};
--
Thanks and Regards,
Danish
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-21 16:10 ` Andrew Lunn
@ 2023-09-22 4:28 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:28 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 21:40, Andrew Lunn wrote:
>> + /* Dual Ethernet application node on PRU-ICSSG2 */
>
> How relevant is "Dual Ethernet" here? You are talking of adding
> switchdev support, and runtime swapping the application. All these
> properties should be valid for the switch application as well?
>
All these properties and nodes are valid for switch mode as well. The
comment of "Dual Ethernet application node" is mainly to describe the
two physical ports that are present on the AM654x-EVM.
> In fact, you are describing hardware here, so the application should
> not actually matter.
>
> So maybe this comment should be:
>
> Ethernet node on PRU-ICSSG2
>
Sure, this makes more sense. I will change the comment.
> Andrew
--
Thanks and Regards,
Danish
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-22 4:28 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:28 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 21:40, Andrew Lunn wrote:
>> + /* Dual Ethernet application node on PRU-ICSSG2 */
>
> How relevant is "Dual Ethernet" here? You are talking of adding
> switchdev support, and runtime swapping the application. All these
> properties should be valid for the switch application as well?
>
All these properties and nodes are valid for switch mode as well. The
comment of "Dual Ethernet application node" is mainly to describe the
two physical ports that are present on the AM654x-EVM.
> In fact, you are describing hardware here, so the application should
> not actually matter.
>
> So maybe this comment should be:
>
> Ethernet node on PRU-ICSSG2
>
Sure, this makes more sense. I will change the comment.
> Andrew
--
Thanks and Regards,
Danish
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
2023-09-21 16:14 ` Andrew Lunn
@ 2023-09-22 4:33 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:33 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 21:44, Andrew Lunn wrote:
>> + /* Dual Ethernet application node on PRU-ICSSG0 */
>> + /* Dual Ethernet application node on PRU-ICSSG1 */
>
> Not relevant to this patch, but to the ongoing discussions around
> adding switchdev support.
>
> Are these two PRU-ICSSG instances completely separate? It is
> physically impossible to combine these four ethernet ports in one
> acceleration domain? It will always be two separate switches, and if
> frames need to go from one switch to the other it happens in software?
>
Yes Andrew, these PRU-ICSSG instances are completely separate.
AM654x-IDK has 3 PRU-ICSSG instances (ICSSG0, ICSSG1, ICSSG2). Each
instance has two slices i.e. two physical ports. Totaling the ports
count to 6. The two slices of a single ICSSG instance can be combined in
the same acceleration domain. However ICSSG ports of different instances
can not be combined together.
The switching in firmware can only happen between two ports in the same
instance. To do switching between ports of different ICSSG instance,
switching will be required to be done in software.
> Andrew
--
Thanks and Regards,
Danish
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
@ 2023-09-22 4:33 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-22 4:33 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vignesh Raghavendra, Nishanth Menon, afd, Conor Dooley,
Krzysztof Kozlowski, Rob Herring, Tero Kristo, linux-kernel,
devicetree, linux-arm-kernel, srk, r-gunasekaran
On 21/09/23 21:44, Andrew Lunn wrote:
>> + /* Dual Ethernet application node on PRU-ICSSG0 */
>> + /* Dual Ethernet application node on PRU-ICSSG1 */
>
> Not relevant to this patch, but to the ongoing discussions around
> adding switchdev support.
>
> Are these two PRU-ICSSG instances completely separate? It is
> physically impossible to combine these four ethernet ports in one
> acceleration domain? It will always be two separate switches, and if
> frames need to go from one switch to the other it happens in software?
>
Yes Andrew, these PRU-ICSSG instances are completely separate.
AM654x-IDK has 3 PRU-ICSSG instances (ICSSG0, ICSSG1, ICSSG2). Each
instance has two slices i.e. two physical ports. Totaling the ports
count to 6. The two slices of a single ICSSG instance can be combined in
the same acceleration domain. However ICSSG ports of different instances
can not be combined together.
The switching in firmware can only happen between two ports in the same
instance. To do switching between ports of different ICSSG instance,
switching will be required to be done in software.
> Andrew
--
Thanks and Regards,
Danish
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-22 4:22 ` MD Danish Anwar
@ 2023-09-25 8:21 ` MD Danish Anwar
-1 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-25 8:21 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
Hi Andrew,
On 22/09/23 09:52, MD Danish Anwar wrote:
> On 21/09/23 22:57, Andrew Davis wrote:
>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>
>>> For support SR2.0 ICSSG Ethernet firmware:
>>> - provide different firmware blobs and use TX_PRU.
>>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>>> - TX timestamp notification comes via INTC interrupt.
>>>
>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>> ---
>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>> k3-am654-common-board.dts} (100%)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>> b/arch/arm64/boot/dts/ti/Makefile
>>> index e7b8e2e7f083..85c91f5e832e 100644
>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>> # Boards with AM65x SoC
>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>> it work
>> to keep this line like before or is there some conflict having both
>> enabled?
>>
>
> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
> icssg2 support as well. But I haven't tested the combination of
> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>
>> Andrew
>>
I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
combination below (having k3-am654-base-board-dtbs :=
k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
both the scenarios and I didn't see any issue. I don't have a rocktech
panel with me so couldn't test that. But as far as ICSSG is concerned it
works fine with the both the combinations. Please let me know which one
should I use. Should I keep gp-evm as it is (use dtb without the icssg2
overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
k3-am654-base-board-rocktech-rk101-panel.dtbo
2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
k3-am654-base-board-rocktech-rk101-panel.dtbo
--
Thanks and Regards,
Danish
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-25 8:21 ` MD Danish Anwar
0 siblings, 0 replies; 32+ messages in thread
From: MD Danish Anwar @ 2023-09-25 8:21 UTC (permalink / raw)
To: Andrew Davis, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
Hi Andrew,
On 22/09/23 09:52, MD Danish Anwar wrote:
> On 21/09/23 22:57, Andrew Davis wrote:
>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>
>>> For support SR2.0 ICSSG Ethernet firmware:
>>> - provide different firmware blobs and use TX_PRU.
>>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>>> - TX timestamp notification comes via INTC interrupt.
>>>
>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>> ---
>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>> k3-am654-common-board.dts} (100%)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>> b/arch/arm64/boot/dts/ti/Makefile
>>> index e7b8e2e7f083..85c91f5e832e 100644
>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>> # Boards with AM65x SoC
>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>> it work
>> to keep this line like before or is there some conflict having both
>> enabled?
>>
>
> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
> icssg2 support as well. But I haven't tested the combination of
> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>
>> Andrew
>>
I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
combination below (having k3-am654-base-board-dtbs :=
k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
both the scenarios and I didn't see any issue. I don't have a rocktech
panel with me so couldn't test that. But as far as ICSSG is concerned it
works fine with the both the combinations. Please let me know which one
should I use. Should I keep gp-evm as it is (use dtb without the icssg2
overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
k3-am654-base-board-rocktech-rk101-panel.dtbo
2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
k3-am654-base-board-rocktech-rk101-panel.dtbo
--
Thanks and Regards,
Danish
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-25 8:21 ` MD Danish Anwar
@ 2023-09-25 13:45 ` Andrew Davis
-1 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-25 13:45 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/25/23 3:21 AM, MD Danish Anwar wrote:
> Hi Andrew,
>
> On 22/09/23 09:52, MD Danish Anwar wrote:
>> On 21/09/23 22:57, Andrew Davis wrote:
>>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>>
>>>> For support SR2.0 ICSSG Ethernet firmware:
>>>> - provide different firmware blobs and use TX_PRU.
>>>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>>>> - TX timestamp notification comes via INTC interrupt.
>>>>
>>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>>> ---
>>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>>> k3-am654-common-board.dts} (100%)
>>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>>> b/arch/arm64/boot/dts/ti/Makefile
>>>> index e7b8e2e7f083..85c91f5e832e 100644
>>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>>> # Boards with AM65x SoC
>>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>
>>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>>> it work
>>> to keep this line like before or is there some conflict having both
>>> enabled?
>>>
>>
>> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
>> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
>> icssg2 support as well. But I haven't tested the combination of
>> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
>> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
>> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>>
>>> Andrew
>>>
>
> I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
> combination below (having k3-am654-base-board-dtbs :=
> k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
> both the scenarios and I didn't see any issue. I don't have a rocktech
> panel with me so couldn't test that. But as far as ICSSG is concerned it
> works fine with the both the combinations. Please let me know which one
> should I use. Should I keep gp-evm as it is (use dtb without the icssg2
> overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
>
>
> 1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
>
> 2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
As you said here before, most will expect the icssg2 to work
on the EVM out of box, you should include it. If anyone wants
something else they can apply the set of overlays that match
on their own.
So, use base-board.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-25 13:45 ` Andrew Davis
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Davis @ 2023-09-25 13:45 UTC (permalink / raw)
To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/25/23 3:21 AM, MD Danish Anwar wrote:
> Hi Andrew,
>
> On 22/09/23 09:52, MD Danish Anwar wrote:
>> On 21/09/23 22:57, Andrew Davis wrote:
>>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>>
>>>> For support SR2.0 ICSSG Ethernet firmware:
>>>> - provide different firmware blobs and use TX_PRU.
>>>> - IEP0 is used as PTP Hardware Clock and can only be used for one port.
>>>> - TX timestamp notification comes via INTC interrupt.
>>>>
>>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>>> ---
>>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145 ++++++++++++++++++
>>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>>> k3-am654-common-board.dts} (100%)
>>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>>> b/arch/arm64/boot/dts/ti/Makefile
>>>> index e7b8e2e7f083..85c91f5e832e 100644
>>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>>> # Boards with AM65x SoC
>>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>
>>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>>> it work
>>> to keep this line like before or is there some conflict having both
>>> enabled?
>>>
>>
>> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
>> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
>> icssg2 support as well. But I haven't tested the combination of
>> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
>> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
>> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>>
>>> Andrew
>>>
>
> I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
> combination below (having k3-am654-base-board-dtbs :=
> k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
> both the scenarios and I didn't see any issue. I don't have a rocktech
> panel with me so couldn't test that. But as far as ICSSG is concerned it
> works fine with the both the combinations. Please let me know which one
> should I use. Should I keep gp-evm as it is (use dtb without the icssg2
> overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
>
>
> 1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
>
> 2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
> k3-am654-base-board-rocktech-rk101-panel.dtbo
>
As you said here before, most will expect the icssg2 to work
on the EVM out of box, you should include it. If anyone wants
something else they can apply the set of overlays that match
on their own.
So, use base-board.
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
2023-09-25 13:45 ` Andrew Davis
@ 2023-09-26 4:10 ` Anwar, Md Danish
-1 siblings, 0 replies; 32+ messages in thread
From: Anwar, Md Danish @ 2023-09-26 4:10 UTC (permalink / raw)
To: Andrew Davis, MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/25/2023 7:15 PM, Andrew Davis wrote:
> On 9/25/23 3:21 AM, MD Danish Anwar wrote:
>> Hi Andrew,
>>
>> On 22/09/23 09:52, MD Danish Anwar wrote:
>>> On 21/09/23 22:57, Andrew Davis wrote:
>>>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>>>
>>>>> For support SR2.0 ICSSG Ethernet firmware:
>>>>> - provide different firmware blobs and use TX_PRU.
>>>>> - IEP0 is used as PTP Hardware Clock and can only be used for one
>>>>> port.
>>>>> - TX timestamp notification comes via INTC interrupt.
>>>>>
>>>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145
>>>>> ++++++++++++++++++
>>>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>>>> k3-am654-common-board.dts} (100%)
>>>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>>>> b/arch/arm64/boot/dts/ti/Makefile
>>>>> index e7b8e2e7f083..85c91f5e832e 100644
>>>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>>>> # Boards with AM65x SoC
>>>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>>
>>>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>>>> it work
>>>> to keep this line like before or is there some conflict having both
>>>> enabled?
>>>>
>>>
>>> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
>>> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
>>> icssg2 support as well. But I haven't tested the combination of
>>> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
>>> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
>>> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>>>
>>>> Andrew
>>>>
>>
>> I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
>> combination below (having k3-am654-base-board-dtbs :=
>> k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
>> both the scenarios and I didn't see any issue. I don't have a rocktech
>> panel with me so couldn't test that. But as far as ICSSG is concerned it
>> works fine with the both the combinations. Please let me know which one
>> should I use. Should I keep gp-evm as it is (use dtb without the icssg2
>> overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
>>
>>
>> 1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>>
>> 2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>
> As you said here before, most will expect the icssg2 to work
> on the EVM out of box, you should include it. If anyone wants
> something else they can apply the set of overlays that match
> on their own.
>
> So, use base-board.
>
> Andrew
Sure Andrew, I will make the change and send v3.
--
Thanks and Regards,
Md Danish Anwar
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
@ 2023-09-26 4:10 ` Anwar, Md Danish
0 siblings, 0 replies; 32+ messages in thread
From: Anwar, Md Danish @ 2023-09-26 4:10 UTC (permalink / raw)
To: Andrew Davis, MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon
Cc: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
linux-kernel, devicetree, linux-arm-kernel, srk, r-gunasekaran
On 9/25/2023 7:15 PM, Andrew Davis wrote:
> On 9/25/23 3:21 AM, MD Danish Anwar wrote:
>> Hi Andrew,
>>
>> On 22/09/23 09:52, MD Danish Anwar wrote:
>>> On 21/09/23 22:57, Andrew Davis wrote:
>>>> On 9/21/23 1:09 AM, MD Danish Anwar wrote:
>>>>> ICSSG2 provides dual Gigabit Ethernet support.
>>>>>
>>>>> For support SR2.0 ICSSG Ethernet firmware:
>>>>> - provide different firmware blobs and use TX_PRU.
>>>>> - IEP0 is used as PTP Hardware Clock and can only be used for one
>>>>> port.
>>>>> - TX timestamp notification comes via INTC interrupt.
>>>>>
>>>>> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/ti/Makefile | 4 +-
>>>>> ...se-board.dts => k3-am654-common-board.dts} | 0
>>>>> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 145
>>>>> ++++++++++++++++++
>>>>> 3 files changed, 148 insertions(+), 1 deletion(-)
>>>>> rename arch/arm64/boot/dts/ti/{k3-am654-base-board.dts =>
>>>>> k3-am654-common-board.dts} (100%)
>>>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>>>>> b/arch/arm64/boot/dts/ti/Makefile
>>>>> index e7b8e2e7f083..85c91f5e832e 100644
>>>>> --- a/arch/arm64/boot/dts/ti/Makefile
>>>>> +++ b/arch/arm64/boot/dts/ti/Makefile
>>>>> @@ -42,12 +42,14 @@ dtb-$(CONFIG_ARCH_K3) +=
>>>>> k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
>>>>> dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
>>>>> # Boards with AM65x SoC
>>>>> -k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>>> +k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>>>>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>>>
>>>> Should the k3-am654-gp-evm.dtb not also have this icssg2 support? Does
>>>> it work
>>>> to keep this line like before or is there some conflict having both
>>>> enabled?
>>>>
>>>
>>> I have not tested this dtb (k3-am654-gp-evm.dtb). So just to be on the
>>> safe side I kept gp-evm.dtb as it was. Ideally gp-evm.dtb should have
>>> icssg2 support as well. But I haven't tested the combination of
>>> base-board + icssg dtbo + rockteck dtbo. That is why I kept gp-evm dtb
>>> as it was. Anyways, for ICSSG2's use case only k3-am654-base-board.dtb
>>> is used so I think it's ok to leave k3-am654-gp-evm.dtb to as it was.
>>>
>>>> Andrew
>>>>
>>
>> I tested AM654x-GP EVM with k3-am654-gp-evm.dtb with both the
>> combination below (having k3-am654-base-board-dtbs :=
>> k3-am654-common-board.dtb k3-am654-icssg2.dtbo), ICSSG worked fine in
>> both the scenarios and I didn't see any issue. I don't have a rocktech
>> panel with me so couldn't test that. But as far as ICSSG is concerned it
>> works fine with the both the combinations. Please let me know which one
>> should I use. Should I keep gp-evm as it is (use dtb without the icssg2
>> overlay) or should I add icssg2 overlay in gp-evm.dtb as well.
>>
>>
>> 1. k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>>
>> 2. k3-am654-gp-evm-dtbs := k3-am654-common-board.dtb
>> k3-am654-base-board-rocktech-rk101-panel.dtbo
>>
>
> As you said here before, most will expect the icssg2 to work
> on the EVM out of box, you should include it. If anyone wants
> something else they can apply the set of overlays that match
> on their own.
>
> So, use base-board.
>
> Andrew
Sure Andrew, I will make the change and send v3.
--
Thanks and Regards,
Md Danish Anwar
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^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2023-09-26 4:11 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-21 6:09 [PATCH v2 0/4] Add AM65x ICSSG Ethernet support MD Danish Anwar
2023-09-21 6:09 ` MD Danish Anwar
2023-09-21 6:09 ` [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes MD Danish Anwar
2023-09-21 6:09 ` MD Danish Anwar
2023-09-21 6:09 ` [PATCH v2 2/4] arm64: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support MD Danish Anwar
2023-09-21 6:09 ` MD Danish Anwar
2023-09-21 16:10 ` Andrew Lunn
2023-09-21 16:10 ` Andrew Lunn
2023-09-22 4:28 ` MD Danish Anwar
2023-09-22 4:28 ` MD Danish Anwar
2023-09-21 17:27 ` Andrew Davis
2023-09-21 17:27 ` Andrew Davis
2023-09-22 4:22 ` MD Danish Anwar
2023-09-22 4:22 ` MD Danish Anwar
2023-09-25 8:21 ` MD Danish Anwar
2023-09-25 8:21 ` MD Danish Anwar
2023-09-25 13:45 ` Andrew Davis
2023-09-25 13:45 ` Andrew Davis
2023-09-26 4:10 ` Anwar, Md Danish
2023-09-26 4:10 ` Anwar, Md Danish
2023-09-21 6:09 ` [PATCH v2 3/4] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports MD Danish Anwar
2023-09-21 6:09 ` MD Danish Anwar
2023-09-21 16:14 ` Andrew Lunn
2023-09-21 16:14 ` Andrew Lunn
2023-09-22 4:33 ` MD Danish Anwar
2023-09-22 4:33 ` MD Danish Anwar
2023-09-21 17:33 ` Andrew Davis
2023-09-21 17:33 ` Andrew Davis
2023-09-22 4:24 ` MD Danish Anwar
2023-09-22 4:24 ` MD Danish Anwar
2023-09-21 6:09 ` [PATCH v2 4/4] arm64: defconfig: Enable TI_ICSSG_PRUETH MD Danish Anwar
2023-09-21 6:09 ` MD Danish Anwar
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