All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andrii Anisov <andrii.anisov@gmail.com>
To: Julien Grall <julien.grall@arm.com>, xen-devel@lists.xenproject.org
Cc: Oleksandr_Tyshchenko@epam.com, sstabellini@kernel.org,
	Andrii_Anisov@epam.com
Subject: Re: [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
Date: Thu, 25 Apr 2019 21:00:51 +0300	[thread overview]
Message-ID: <52b107e1-fa03-54aa-3b64-3bba7104661b@gmail.com> (raw)
In-Reply-To: <20190417175815.16905-2-julien.grall@arm.com>



On 17.04.19 20:58, Julien Grall wrote:
> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
> non-boot CPU. So introduce a function to set the bit and clear TBLs.
s/TBL/TLB/

> 
> This new function will help us to document and update the logic in a
> single place.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

> ---
>   xen/arch/arm/mm.c | 22 +++++++++++++++-------
>   1 file changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 01ae2cccc0..93ad118183 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
>       flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
>   }
>   
> +/*
> + * After boot, Xen page-tables should not contain mapping that are both
> + * Writable and eXecutables.
> + *
> + * This should be called on each CPU to enforce the policy.
> + */
> +static void xen_pt_enforce_wnx(void)
Could it be inline?

> +{
> +    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> +    /* Flush everything after setting WXN bit. */
> +    flush_xen_text_tlb_local();
> +}
> +
>   extern void switch_ttbr(uint64_t ttbr);
>   
>   /* Clear a translation table and clean & invalidate the cache */
> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
>       clear_table(boot_second);
>       clear_table(boot_third);
>   
> -    /* From now on, no mapping may be both writable and executable. */
> -    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> -    /* Flush everything after setting WXN bit. */
> -    flush_xen_text_tlb_local();
> +    xen_pt_enforce_wnx();
>   
>   #ifdef CONFIG_ARM_32
>       per_cpu(xen_pgtable, 0) = cpu0_pgtable;
> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
>   /* MMU setup for secondary CPUS (which already have paging enabled) */
>   void mmu_init_secondary_cpu(void)
>   {
> -    /* From now on, no mapping may be both writable and executable. */
> -    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> -    flush_xen_text_tlb_local();
> +    xen_pt_enforce_wnx();
>   }
>   
>   #ifdef CONFIG_ARM_32
> 

With minor notes,

Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>

-- 
Sincerely,
Andrii Anisov.

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

WARNING: multiple messages have this Message-ID (diff)
From: Andrii Anisov <andrii.anisov@gmail.com>
To: Julien Grall <julien.grall@arm.com>, xen-devel@lists.xenproject.org
Cc: Oleksandr_Tyshchenko@epam.com, sstabellini@kernel.org,
	Andrii_Anisov@epam.com
Subject: Re: [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place
Date: Thu, 25 Apr 2019 21:00:51 +0300	[thread overview]
Message-ID: <52b107e1-fa03-54aa-3b64-3bba7104661b@gmail.com> (raw)
Message-ID: <20190425180051.k3AwApbgQirKrWO0BOwodonQM9dgUfoQq3HXNptE1BY@z> (raw)
In-Reply-To: <20190417175815.16905-2-julien.grall@arm.com>



On 17.04.19 20:58, Julien Grall wrote:
> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and
> non-boot CPU. So introduce a function to set the bit and clear TBLs.
s/TBL/TLB/

> 
> This new function will help us to document and update the logic in a
> single place.
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

> ---
>   xen/arch/arm/mm.c | 22 +++++++++++++++-------
>   1 file changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 01ae2cccc0..93ad118183 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void)
>       flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE);
>   }
>   
> +/*
> + * After boot, Xen page-tables should not contain mapping that are both
> + * Writable and eXecutables.
> + *
> + * This should be called on each CPU to enforce the policy.
> + */
> +static void xen_pt_enforce_wnx(void)
Could it be inline?

> +{
> +    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> +    /* Flush everything after setting WXN bit. */
> +    flush_xen_text_tlb_local();
> +}
> +
>   extern void switch_ttbr(uint64_t ttbr);
>   
>   /* Clear a translation table and clean & invalidate the cache */
> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
>       clear_table(boot_second);
>       clear_table(boot_third);
>   
> -    /* From now on, no mapping may be both writable and executable. */
> -    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> -    /* Flush everything after setting WXN bit. */
> -    flush_xen_text_tlb_local();
> +    xen_pt_enforce_wnx();
>   
>   #ifdef CONFIG_ARM_32
>       per_cpu(xen_pgtable, 0) = cpu0_pgtable;
> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu)
>   /* MMU setup for secondary CPUS (which already have paging enabled) */
>   void mmu_init_secondary_cpu(void)
>   {
> -    /* From now on, no mapping may be both writable and executable. */
> -    WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2);
> -    flush_xen_text_tlb_local();
> +    xen_pt_enforce_wnx();
>   }
>   
>   #ifdef CONFIG_ARM_32
> 

With minor notes,

Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>

-- 
Sincerely,
Andrii Anisov.

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

  reply	other threads:[~2019-04-25 18:00 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-17 17:58 [PATCH 0/7] xen/arm: TLB flush helpers rework Julien Grall
2019-04-17 17:58 ` [Xen-devel] " Julien Grall
2019-04-17 17:58 ` [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:00   ` Andrii Anisov [this message]
2019-04-25 18:00     ` Andrii Anisov
2019-04-25 20:26     ` Julien Grall
2019-04-25 20:26       ` [Xen-devel] " Julien Grall
2019-04-26 13:48       ` Andrii Anisov
2019-04-26 13:48         ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local() Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:00   ` Andrii Anisov
2019-04-25 18:00     ` [Xen-devel] " Andrii Anisov
2019-04-25 20:37     ` Julien Grall
2019-04-25 20:37       ` [Xen-devel] " Julien Grall
2019-04-26 13:50       ` Andrii Anisov
2019-04-26 13:50         ` [Xen-devel] " Andrii Anisov
2019-04-26 14:15         ` Andrii Anisov
2019-04-26 14:15           ` [Xen-devel] " Andrii Anisov
2019-04-26 14:31           ` Julien Grall
2019-04-26 14:31             ` [Xen-devel] " Julien Grall
2019-04-26 15:08             ` Andrii Anisov
2019-04-26 15:08               ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:00   ` Andrii Anisov
2019-04-25 18:00     ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs " Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:00   ` Andrii Anisov
2019-04-25 18:00     ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:01   ` Andrii Anisov
2019-04-25 18:01     ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:01   ` Andrii Anisov
2019-04-25 18:01     ` [Xen-devel] " Andrii Anisov
2019-04-25 20:42     ` Julien Grall
2019-04-25 20:42       ` [Xen-devel] " Julien Grall
2019-04-26 13:49       ` Andrii Anisov
2019-04-26 13:49         ` [Xen-devel] " Andrii Anisov
2019-04-26 14:06         ` Julien Grall
2019-04-26 14:06           ` [Xen-devel] " Julien Grall
2019-04-26 15:17           ` Andrii Anisov
2019-04-26 15:17             ` [Xen-devel] " Andrii Anisov
2019-04-17 17:58 ` [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries Julien Grall
2019-04-17 17:58   ` [Xen-devel] " Julien Grall
2019-04-25 18:03   ` Andrii Anisov
2019-04-25 18:03     ` [Xen-devel] " Andrii Anisov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=52b107e1-fa03-54aa-3b64-3bba7104661b@gmail.com \
    --to=andrii.anisov@gmail.com \
    --cc=Andrii_Anisov@epam.com \
    --cc=Oleksandr_Tyshchenko@epam.com \
    --cc=julien.grall@arm.com \
    --cc=sstabellini@kernel.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.