From: Julien Grall <Julien.Grall@arm.com> To: Andrii Anisov <andrii.anisov@gmail.com>, "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org> Cc: "Oleksandr_Tyshchenko@epam.com" <Oleksandr_Tyshchenko@epam.com>, nd <nd@arm.com>, "Andrii_Anisov@epam.com" <Andrii_Anisov@epam.com>, "sstabellini@kernel.org" <sstabellini@kernel.org> Subject: Re: [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place Date: Thu, 25 Apr 2019 20:26:07 +0000 [thread overview] Message-ID: <8bcf25e7-3c7a-b61d-6caf-a11eaf68a232@arm.com> (raw) In-Reply-To: <52b107e1-fa03-54aa-3b64-3bba7104661b@gmail.com> Hi, On 25/04/2019 19:00, Andrii Anisov wrote: > > > On 17.04.19 20:58, Julien Grall wrote: >> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and >> non-boot CPU. So introduce a function to set the bit and clear TBLs. > s/TBL/TLB/ > >> >> This new function will help us to document and update the logic in a >> single place. >> >> Signed-off-by: Julien Grall <julien.grall@arm.com> > >> --- >> xen/arch/arm/mm.c | 22 +++++++++++++++------- >> 1 file changed, 15 insertions(+), 7 deletions(-) >> >> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c >> index 01ae2cccc0..93ad118183 100644 >> --- a/xen/arch/arm/mm.c >> +++ b/xen/arch/arm/mm.c >> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void) >> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, >> BOOT_FDT_SLOT_SIZE); >> } >> +/* >> + * After boot, Xen page-tables should not contain mapping that are both >> + * Writable and eXecutables. >> + * >> + * This should be called on each CPU to enforce the policy. >> + */ >> +static void xen_pt_enforce_wnx(void) > Could it be inline? Why can't we let the compiler deciding for us? The more that inline is pretty broken. See: https://www.kernel.org/doc/local/inline.html > >> +{ >> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> + /* Flush everything after setting WXN bit. */ >> + flush_xen_text_tlb_local(); >> +} >> + >> extern void switch_ttbr(uint64_t ttbr); >> /* Clear a translation table and clean & invalidate the cache */ >> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long >> boot_phys_offset) >> clear_table(boot_second); >> clear_table(boot_third); >> - /* From now on, no mapping may be both writable and executable. */ >> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> - /* Flush everything after setting WXN bit. */ >> - flush_xen_text_tlb_local(); >> + xen_pt_enforce_wnx(); >> #ifdef CONFIG_ARM_32 >> per_cpu(xen_pgtable, 0) = cpu0_pgtable; >> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu) >> /* MMU setup for secondary CPUS (which already have paging enabled) */ >> void mmu_init_secondary_cpu(void) >> { >> - /* From now on, no mapping may be both writable and executable. */ >> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> - flush_xen_text_tlb_local(); >> + xen_pt_enforce_wnx(); >> } >> #ifdef CONFIG_ARM_32 >> > > With minor notes, > > Reviewed-by: Andrii Anisov <andrii_anisov@epam.com> Thank you! Cheers, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
WARNING: multiple messages have this Message-ID (diff)
From: Julien Grall <Julien.Grall@arm.com> To: Andrii Anisov <andrii.anisov@gmail.com>, "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org> Cc: "Oleksandr_Tyshchenko@epam.com" <Oleksandr_Tyshchenko@epam.com>, nd <nd@arm.com>, "Andrii_Anisov@epam.com" <Andrii_Anisov@epam.com>, "sstabellini@kernel.org" <sstabellini@kernel.org> Subject: Re: [Xen-devel] [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place Date: Thu, 25 Apr 2019 20:26:07 +0000 [thread overview] Message-ID: <8bcf25e7-3c7a-b61d-6caf-a11eaf68a232@arm.com> (raw) Message-ID: <20190425202607.ys6BDRKULIaUyr1B94O0JxXr0-3XqifExXZjByqeugE@z> (raw) In-Reply-To: <52b107e1-fa03-54aa-3b64-3bba7104661b@gmail.com> Hi, On 25/04/2019 19:00, Andrii Anisov wrote: > > > On 17.04.19 20:58, Julien Grall wrote: >> The logic to set SCTLR_EL2.WXN is the same for the boot CPU and >> non-boot CPU. So introduce a function to set the bit and clear TBLs. > s/TBL/TLB/ > >> >> This new function will help us to document and update the logic in a >> single place. >> >> Signed-off-by: Julien Grall <julien.grall@arm.com> > >> --- >> xen/arch/arm/mm.c | 22 +++++++++++++++------- >> 1 file changed, 15 insertions(+), 7 deletions(-) >> >> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c >> index 01ae2cccc0..93ad118183 100644 >> --- a/xen/arch/arm/mm.c >> +++ b/xen/arch/arm/mm.c >> @@ -601,6 +601,19 @@ void __init remove_early_mappings(void) >> flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, >> BOOT_FDT_SLOT_SIZE); >> } >> +/* >> + * After boot, Xen page-tables should not contain mapping that are both >> + * Writable and eXecutables. >> + * >> + * This should be called on each CPU to enforce the policy. >> + */ >> +static void xen_pt_enforce_wnx(void) > Could it be inline? Why can't we let the compiler deciding for us? The more that inline is pretty broken. See: https://www.kernel.org/doc/local/inline.html > >> +{ >> + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> + /* Flush everything after setting WXN bit. */ >> + flush_xen_text_tlb_local(); >> +} >> + >> extern void switch_ttbr(uint64_t ttbr); >> /* Clear a translation table and clean & invalidate the cache */ >> @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long >> boot_phys_offset) >> clear_table(boot_second); >> clear_table(boot_third); >> - /* From now on, no mapping may be both writable and executable. */ >> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> - /* Flush everything after setting WXN bit. */ >> - flush_xen_text_tlb_local(); >> + xen_pt_enforce_wnx(); >> #ifdef CONFIG_ARM_32 >> per_cpu(xen_pgtable, 0) = cpu0_pgtable; >> @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu) >> /* MMU setup for secondary CPUS (which already have paging enabled) */ >> void mmu_init_secondary_cpu(void) >> { >> - /* From now on, no mapping may be both writable and executable. */ >> - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); >> - flush_xen_text_tlb_local(); >> + xen_pt_enforce_wnx(); >> } >> #ifdef CONFIG_ARM_32 >> > > With minor notes, > > Reviewed-by: Andrii Anisov <andrii_anisov@epam.com> Thank you! Cheers, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2019-04-25 20:26 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-17 17:58 [PATCH 0/7] xen/arm: TLB flush helpers rework Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-17 17:58 ` [PATCH 1/7] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:00 ` Andrii Anisov 2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov 2019-04-25 20:26 ` Julien Grall [this message] 2019-04-25 20:26 ` Julien Grall 2019-04-26 13:48 ` Andrii Anisov 2019-04-26 13:48 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 2/7] xen/arm: Remove flush_xen_text_tlb_local() Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:00 ` Andrii Anisov 2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov 2019-04-25 20:37 ` Julien Grall 2019-04-25 20:37 ` [Xen-devel] " Julien Grall 2019-04-26 13:50 ` Andrii Anisov 2019-04-26 13:50 ` [Xen-devel] " Andrii Anisov 2019-04-26 14:15 ` Andrii Anisov 2019-04-26 14:15 ` [Xen-devel] " Andrii Anisov 2019-04-26 14:31 ` Julien Grall 2019-04-26 14:31 ` [Xen-devel] " Julien Grall 2019-04-26 15:08 ` Andrii Anisov 2019-04-26 15:08 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 3/7] xen/arm: tlbflush: Clarify the TLB helpers name Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:00 ` Andrii Anisov 2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 4/7] xen/arm: page: Clarify the Xen TLBs " Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:00 ` Andrii Anisov 2019-04-25 18:00 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 5/7] xen/arm: Gather all TLB flush helpers in tlbflush.h Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:01 ` Andrii Anisov 2019-04-25 18:01 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 6/7] xen/arm: tlbflush: Rework TLB helpers Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:01 ` Andrii Anisov 2019-04-25 18:01 ` [Xen-devel] " Andrii Anisov 2019-04-25 20:42 ` Julien Grall 2019-04-25 20:42 ` [Xen-devel] " Julien Grall 2019-04-26 13:49 ` Andrii Anisov 2019-04-26 13:49 ` [Xen-devel] " Andrii Anisov 2019-04-26 14:06 ` Julien Grall 2019-04-26 14:06 ` [Xen-devel] " Julien Grall 2019-04-26 15:17 ` Andrii Anisov 2019-04-26 15:17 ` [Xen-devel] " Andrii Anisov 2019-04-17 17:58 ` [PATCH 7/7] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries Julien Grall 2019-04-17 17:58 ` [Xen-devel] " Julien Grall 2019-04-25 18:03 ` Andrii Anisov 2019-04-25 18:03 ` [Xen-devel] " Andrii Anisov
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