Re: [PATCH] pc-bios/s390-ccw: Use memory barriers in virtio code

From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Thomas Huth <thuth@redhat.com>, Cornelia Huck <cohuck@redhat.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Halil Pasic <pasic@linux.ibm.com>,
	Christian Borntraeger <borntraeger@de.ibm.com>,
	qemu-s390x <qemu-s390x@nongnu.org>
Subject: Re: [PATCH] pc-bios/s390-ccw: Use memory barriers in virtio code
Date: Wed, 17 Feb 2021 07:11:37 -0800	[thread overview]
Message-ID: <52bc865c-9e4d-ebfa-e7c0-15747f194532@linaro.org> (raw)
In-Reply-To: <CAFEAcA-sgkxazKcR8tbLdj_B3F5bwg2c4TqkNd7gCSCQ5BYQEQ@mail.gmail.com>

On 2/17/21 3:15 AM, Peter Maydell wrote:
> This isn't aarch64-host-specific, though, is it? It's going to be
> the situation for any host with a relaxed memory model.

Yes.  I intend to make the code-generation changes generic.

> Do we really
> want to make all loads and stores lower-performance by adding in
> the ldacq/strel (or worse, barriers everywhere on host archs without
> ldacq/strel)?

Well, yes.  But then we get to enable mttcg too.

> I feel like there ought to be an alternate approach
> involving using some kind of exclusion to ensure that we don't run
> the iothreads in parallel with the vCPU thread if we're using the
> non-MTTCG setup where all the vCPUs are on a single thread, and that
> that's probably less of a perf hit.

I don't know where to put such a block, do you?

The memory barriers are a perf hit with -smp 1, but I would think that all that
and more are recoverable by not having to run -smp 2 serially.

r~