From: xinlei.lee <xinlei.lee@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, <chunkuang.hu@kernel.org>,
<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
<matthias.bgg@gmail.com>
Cc: <jitao.shi@mediatek.com>, <linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<linux-mediatek@lists.infradead.org>, <rex-bc.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3, 1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 14:16:29 +0800 [thread overview]
Message-ID: <5318b54772ed03744cd6265d3b65679b86ec0532.camel@mediatek.com> (raw)
In-Reply-To: <0e4344e084e3306cd265580883c0093c7cb40d45.camel@mediatek.com>
On Mon, 2022-03-21 at 17:36 +0800, CK Hu wrote:
> Hi, Xinlei:
>
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> >
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
>
> I think there would be one patch in 5.9 make the wrong sequence, so
> add
> 'Fixes' tag to indicate which patch make the wrong sequence. Use the
> term correct/wrong instead old/new sequence.
>
> I still do not understand what is the sequence after apply this
> patch?
>
> Does the sequence is this after apply this patch?
> 1. Set the dsi timing register
> 2. Pull the MIPI signal high
> 3. Delay & Dsi_reset
> 4. dsi clk & lanes leave ulp mode and enter hs mode
>
> Regards,
> CK
>
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> > mtk_dsi_reset_engine(dsi);
> > mtk_dsi_phy_timconfig(dsi);
> >
> > - mtk_dsi_rxtx_control(dsi);
> > - usleep_range(30, 100);
> > - mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_ps_control_vact(dsi);
> > mtk_dsi_set_vm_cmd(dsi);
> > mtk_dsi_config_vdo_timing(dsi);
> > mtk_dsi_set_interrupt_enable(dsi);
> >
> > + mtk_dsi_rxtx_control(dsi);
> > + usleep_range(30, 100);
> > + mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > mtk_dsi_clk_hs_mode(dsi, 0);
>
>
Hi CK:
Thanks for your review!
You are right, the sequence after patching is:
1. Set the dsi timing register
2. Pull the MIPI signal high
3. Delay & Dsi_reset
4. dsi clk & lanes leave ulp mode and enter hs mode
This modification will not affect the dsi function, just to put the
operation of pulling up the mipi signal in poweron together to
facilitate the separation from the poweron function later.
I will add the "Fixes" tag here as well.
BR!
xinlei
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: xinlei.lee <xinlei.lee@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, <chunkuang.hu@kernel.org>,
<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
<matthias.bgg@gmail.com>
Cc: jitao.shi@mediatek.com, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
linux-mediatek@lists.infradead.org, rex-bc.chen@mediatek.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3, 1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 14:16:29 +0800 [thread overview]
Message-ID: <5318b54772ed03744cd6265d3b65679b86ec0532.camel@mediatek.com> (raw)
In-Reply-To: <0e4344e084e3306cd265580883c0093c7cb40d45.camel@mediatek.com>
On Mon, 2022-03-21 at 17:36 +0800, CK Hu wrote:
> Hi, Xinlei:
>
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> >
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
>
> I think there would be one patch in 5.9 make the wrong sequence, so
> add
> 'Fixes' tag to indicate which patch make the wrong sequence. Use the
> term correct/wrong instead old/new sequence.
>
> I still do not understand what is the sequence after apply this
> patch?
>
> Does the sequence is this after apply this patch?
> 1. Set the dsi timing register
> 2. Pull the MIPI signal high
> 3. Delay & Dsi_reset
> 4. dsi clk & lanes leave ulp mode and enter hs mode
>
> Regards,
> CK
>
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> > mtk_dsi_reset_engine(dsi);
> > mtk_dsi_phy_timconfig(dsi);
> >
> > - mtk_dsi_rxtx_control(dsi);
> > - usleep_range(30, 100);
> > - mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_ps_control_vact(dsi);
> > mtk_dsi_set_vm_cmd(dsi);
> > mtk_dsi_config_vdo_timing(dsi);
> > mtk_dsi_set_interrupt_enable(dsi);
> >
> > + mtk_dsi_rxtx_control(dsi);
> > + usleep_range(30, 100);
> > + mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > mtk_dsi_clk_hs_mode(dsi, 0);
>
>
Hi CK:
Thanks for your review!
You are right, the sequence after patching is:
1. Set the dsi timing register
2. Pull the MIPI signal high
3. Delay & Dsi_reset
4. dsi clk & lanes leave ulp mode and enter hs mode
This modification will not affect the dsi function, just to put the
operation of pulling up the mipi signal in poweron together to
facilitate the separation from the poweron function later.
I will add the "Fixes" tag here as well.
BR!
xinlei
WARNING: multiple messages have this Message-ID (diff)
From: xinlei.lee <xinlei.lee@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, <chunkuang.hu@kernel.org>,
<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
<matthias.bgg@gmail.com>
Cc: <jitao.shi@mediatek.com>, <linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<linux-mediatek@lists.infradead.org>, <rex-bc.chen@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3, 1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 14:16:29 +0800 [thread overview]
Message-ID: <5318b54772ed03744cd6265d3b65679b86ec0532.camel@mediatek.com> (raw)
In-Reply-To: <0e4344e084e3306cd265580883c0093c7cb40d45.camel@mediatek.com>
On Mon, 2022-03-21 at 17:36 +0800, CK Hu wrote:
> Hi, Xinlei:
>
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> >
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> >
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
>
> I think there would be one patch in 5.9 make the wrong sequence, so
> add
> 'Fixes' tag to indicate which patch make the wrong sequence. Use the
> term correct/wrong instead old/new sequence.
>
> I still do not understand what is the sequence after apply this
> patch?
>
> Does the sequence is this after apply this patch?
> 1. Set the dsi timing register
> 2. Pull the MIPI signal high
> 3. Delay & Dsi_reset
> 4. dsi clk & lanes leave ulp mode and enter hs mode
>
> Regards,
> CK
>
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> > mtk_dsi_reset_engine(dsi);
> > mtk_dsi_phy_timconfig(dsi);
> >
> > - mtk_dsi_rxtx_control(dsi);
> > - usleep_range(30, 100);
> > - mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_ps_control_vact(dsi);
> > mtk_dsi_set_vm_cmd(dsi);
> > mtk_dsi_config_vdo_timing(dsi);
> > mtk_dsi_set_interrupt_enable(dsi);
> >
> > + mtk_dsi_rxtx_control(dsi);
> > + usleep_range(30, 100);
> > + mtk_dsi_reset_dphy(dsi);
> > mtk_dsi_clk_ulp_mode_leave(dsi);
> > mtk_dsi_lane0_ulp_mode_leave(dsi);
> > mtk_dsi_clk_hs_mode(dsi, 0);
>
>
Hi CK:
Thanks for your review!
You are right, the sequence after patching is:
1. Set the dsi timing register
2. Pull the MIPI signal high
3. Delay & Dsi_reset
4. dsi clk & lanes leave ulp mode and enter hs mode
This modification will not affect the dsi function, just to put the
operation of pulling up the mipi signal in poweron together to
facilitate the separation from the poweron function later.
I will add the "Fixes" tag here as well.
BR!
xinlei
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-03-22 6:16 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-17 7:53 [PATCH v3,0/4] Cooperate with DSI RX devices to modify dsi funcs and delay mipi high to cooperate with panel sequence xinlei.lee
2022-03-17 7:53 ` [PATCH v3, 0/4] " xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` [PATCH v3,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 xinlei.lee
2022-03-17 7:53 ` [PATCH v3, 1/4] " xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 11:13 ` [PATCH v3,1/4] " Rex-BC Chen
2022-03-17 11:13 ` Rex-BC Chen
2022-03-17 11:13 ` Rex-BC Chen
2022-03-17 11:13 ` Rex-BC Chen
2022-03-22 5:59 ` xinlei.lee
2022-03-22 5:59 ` xinlei.lee
2022-03-22 5:59 ` xinlei.lee
2022-03-21 9:36 ` [PATCH v3, 1/4] " CK Hu
2022-03-21 9:36 ` CK Hu
2022-03-21 9:36 ` CK Hu
2022-03-21 9:36 ` CK Hu
2022-03-22 6:16 ` xinlei.lee [this message]
2022-03-22 6:16 ` xinlei.lee
2022-03-22 6:16 ` xinlei.lee
2022-03-17 7:53 ` [PATCH v3,2/4] drm/mediatek: Separate poweron/poweroff from enable/disable and define new funcs xinlei.lee
2022-03-17 7:53 ` [PATCH v3, 2/4] " xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 12:02 ` [PATCH v3,2/4] " Rex-BC Chen
2022-03-17 12:02 ` Rex-BC Chen
2022-03-17 12:02 ` Rex-BC Chen
2022-03-17 12:02 ` Rex-BC Chen
2022-03-22 9:23 ` xinlei.lee
2022-03-22 9:23 ` xinlei.lee
2022-03-22 9:23 ` xinlei.lee
2022-03-23 11:46 ` Rex-BC Chen
2022-03-23 11:46 ` Rex-BC Chen
2022-03-23 11:46 ` Rex-BC Chen
2022-04-07 3:50 ` xinlei.lee
2022-04-07 3:50 ` xinlei.lee
2022-04-07 3:50 ` xinlei.lee
2022-03-17 7:53 ` [PATCH v3,3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer xinlei.lee
2022-03-17 7:53 ` [PATCH v3, 3/4] " xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 12:06 ` [PATCH v3,3/4] " Rex-BC Chen
2022-03-17 12:06 ` Rex-BC Chen
2022-03-17 12:06 ` Rex-BC Chen
2022-03-17 12:06 ` Rex-BC Chen
2022-03-22 9:46 ` xinlei.lee
2022-03-22 9:46 ` xinlei.lee
2022-03-22 9:46 ` xinlei.lee
2022-03-17 7:53 ` [PATCH v3,4/4] drm/mediatek: Add pull-down MIPI operation in mtk_dsi_poweroff function xinlei.lee
2022-03-17 7:53 ` [PATCH v3, 4/4] " xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 7:53 ` xinlei.lee
2022-03-17 12:20 ` [PATCH v3,4/4] " Rex-BC Chen
2022-03-17 12:20 ` Rex-BC Chen
2022-03-17 12:20 ` Rex-BC Chen
2022-03-17 12:20 ` Rex-BC Chen
2022-03-22 10:00 ` xinlei.lee
2022-03-22 10:00 ` xinlei.lee
2022-03-22 10:00 ` xinlei.lee
2022-03-23 11:54 ` Rex-BC Chen
2022-03-23 11:54 ` Rex-BC Chen
2022-03-23 11:54 ` Rex-BC Chen
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