All of lore.kernel.org
 help / color / mirror / Atom feed
From: xinlei.lee <xinlei.lee@mediatek.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>, <chunkuang.hu@kernel.org>,
	<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
	<matthias.bgg@gmail.com>
Cc: jitao.shi@mediatek.com, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com,
	linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 13:59:56 +0800	[thread overview]
Message-ID: <ca8c83e15808b7c6a54ebd28cead59c18f814023.camel@mediatek.com> (raw)
In-Reply-To: <235c5bca8da7118bad6bb5cb3c8cba6e022e4411.camel@mediatek.com>

On Thu, 2022-03-17 at 19:13 +0800, Rex-BC Chen wrote:
> Hello Xinlei,
> 
> Thanks for your patch, and there are something I want to know:
> 
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> > 
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> 
> Could you explain why you want to change original power on sequence?
> From this commit message, I don't know why you want to do this.
> If the reason is in cover letter, I think you should move them here.
> 
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
> 
> I think this is no need to describe here.
> 
> BRs,
> Rex
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> >  	mtk_dsi_reset_engine(dsi);
> >  	mtk_dsi_phy_timconfig(dsi);
> >  
> > -	mtk_dsi_rxtx_control(dsi);
> > -	usleep_range(30, 100);
> > -	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_ps_control_vact(dsi);
> >  	mtk_dsi_set_vm_cmd(dsi);
> >  	mtk_dsi_config_vdo_timing(dsi);
> >  	mtk_dsi_set_interrupt_enable(dsi);
> >  
> > +	mtk_dsi_rxtx_control(dsi);
> > +	usleep_range(30, 100);
> > +	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_clk_ulp_mode_leave(dsi);
> >  	mtk_dsi_lane0_ulp_mode_leave(dsi);
> >  	mtk_dsi_clk_hs_mode(dsi, 0);
> 
> 
Hi Rex:

Thanks for your review!
Explain to you that this change does not actually affect the function
of dsi. We have verified this.
After this modification, it is convenient to move them into the if
(!dsi->lanes_ready) condition, which is just an adjustment action.
If you still have questions about my later explanation, please give
another suggestion.

Thanks!
xinlei



WARNING: multiple messages have this Message-ID (diff)
From: xinlei.lee <xinlei.lee@mediatek.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>, <chunkuang.hu@kernel.org>,
	<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
	<matthias.bgg@gmail.com>
Cc: <dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<jitao.shi@mediatek.com>
Subject: Re: [PATCH v3,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 13:59:56 +0800	[thread overview]
Message-ID: <ca8c83e15808b7c6a54ebd28cead59c18f814023.camel@mediatek.com> (raw)
In-Reply-To: <235c5bca8da7118bad6bb5cb3c8cba6e022e4411.camel@mediatek.com>

On Thu, 2022-03-17 at 19:13 +0800, Rex-BC Chen wrote:
> Hello Xinlei,
> 
> Thanks for your patch, and there are something I want to know:
> 
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> > 
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> 
> Could you explain why you want to change original power on sequence?
> From this commit message, I don't know why you want to do this.
> If the reason is in cover letter, I think you should move them here.
> 
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
> 
> I think this is no need to describe here.
> 
> BRs,
> Rex
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> >  	mtk_dsi_reset_engine(dsi);
> >  	mtk_dsi_phy_timconfig(dsi);
> >  
> > -	mtk_dsi_rxtx_control(dsi);
> > -	usleep_range(30, 100);
> > -	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_ps_control_vact(dsi);
> >  	mtk_dsi_set_vm_cmd(dsi);
> >  	mtk_dsi_config_vdo_timing(dsi);
> >  	mtk_dsi_set_interrupt_enable(dsi);
> >  
> > +	mtk_dsi_rxtx_control(dsi);
> > +	usleep_range(30, 100);
> > +	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_clk_ulp_mode_leave(dsi);
> >  	mtk_dsi_lane0_ulp_mode_leave(dsi);
> >  	mtk_dsi_clk_hs_mode(dsi, 0);
> 
> 
Hi Rex:

Thanks for your review!
Explain to you that this change does not actually affect the function
of dsi. We have verified this.
After this modification, it is convenient to move them into the if
(!dsi->lanes_ready) condition, which is just an adjustment action.
If you still have questions about my later explanation, please give
another suggestion.

Thanks!
xinlei

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: xinlei.lee <xinlei.lee@mediatek.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>, <chunkuang.hu@kernel.org>,
	<p.zabel@pengutronix.de>, <airlied@linux.ie>, <daniel@ffwll.ch>,
	<matthias.bgg@gmail.com>
Cc: <dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<jitao.shi@mediatek.com>
Subject: Re: [PATCH v3,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Date: Tue, 22 Mar 2022 13:59:56 +0800	[thread overview]
Message-ID: <ca8c83e15808b7c6a54ebd28cead59c18f814023.camel@mediatek.com> (raw)
In-Reply-To: <235c5bca8da7118bad6bb5cb3c8cba6e022e4411.camel@mediatek.com>

On Thu, 2022-03-17 at 19:13 +0800, Rex-BC Chen wrote:
> Hello Xinlei,
> 
> Thanks for your patch, and there are something I want to know:
> 
> On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote:
> > From: Jitao Shi <jitao.shi@mediatek.com>
> > 
> > Old sequence:
> > 1. Pull the MIPI signal high
> > 2. Delay & Dsi_reset
> > 3. Set the dsi timing register
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> > New sequence:
> > 1. Set the dsi timing register
> > 2. Pull the MIPI signal high
> > 3. Delay & Dsi_reset
> > 4. dsi clk & lanes leave ulp mode and enter hs mode
> > 
> 
> Could you explain why you want to change original power on sequence?
> From this commit message, I don't know why you want to do this.
> If the reason is in cover letter, I think you should move them here.
> 
> > In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later
> > patch.
> 
> I think this is no need to describe here.
> 
> BRs,
> Rex
> > 
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index ccb0511b9cd5..262c027d8c2f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi
> > *dsi)
> >  	mtk_dsi_reset_engine(dsi);
> >  	mtk_dsi_phy_timconfig(dsi);
> >  
> > -	mtk_dsi_rxtx_control(dsi);
> > -	usleep_range(30, 100);
> > -	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_ps_control_vact(dsi);
> >  	mtk_dsi_set_vm_cmd(dsi);
> >  	mtk_dsi_config_vdo_timing(dsi);
> >  	mtk_dsi_set_interrupt_enable(dsi);
> >  
> > +	mtk_dsi_rxtx_control(dsi);
> > +	usleep_range(30, 100);
> > +	mtk_dsi_reset_dphy(dsi);
> >  	mtk_dsi_clk_ulp_mode_leave(dsi);
> >  	mtk_dsi_lane0_ulp_mode_leave(dsi);
> >  	mtk_dsi_clk_hs_mode(dsi, 0);
> 
> 
Hi Rex:

Thanks for your review!
Explain to you that this change does not actually affect the function
of dsi. We have verified this.
After this modification, it is convenient to move them into the if
(!dsi->lanes_ready) condition, which is just an adjustment action.
If you still have questions about my later explanation, please give
another suggestion.

Thanks!
xinlei

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-03-22  5:59 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-17  7:53 [PATCH v3,0/4] Cooperate with DSI RX devices to modify dsi funcs and delay mipi high to cooperate with panel sequence xinlei.lee
2022-03-17  7:53 ` [PATCH v3, 0/4] " xinlei.lee
2022-03-17  7:53 ` xinlei.lee
2022-03-17  7:53 ` xinlei.lee
2022-03-17  7:53 ` [PATCH v3,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 xinlei.lee
2022-03-17  7:53   ` [PATCH v3, 1/4] " xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17 11:13   ` [PATCH v3,1/4] " Rex-BC Chen
2022-03-17 11:13     ` Rex-BC Chen
2022-03-17 11:13     ` Rex-BC Chen
2022-03-17 11:13     ` Rex-BC Chen
2022-03-22  5:59     ` xinlei.lee [this message]
2022-03-22  5:59       ` xinlei.lee
2022-03-22  5:59       ` xinlei.lee
2022-03-21  9:36   ` [PATCH v3, 1/4] " CK Hu
2022-03-21  9:36     ` CK Hu
2022-03-21  9:36     ` CK Hu
2022-03-21  9:36     ` CK Hu
2022-03-22  6:16     ` xinlei.lee
2022-03-22  6:16       ` xinlei.lee
2022-03-22  6:16       ` xinlei.lee
2022-03-17  7:53 ` [PATCH v3,2/4] drm/mediatek: Separate poweron/poweroff from enable/disable and define new funcs xinlei.lee
2022-03-17  7:53   ` [PATCH v3, 2/4] " xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17 12:02   ` [PATCH v3,2/4] " Rex-BC Chen
2022-03-17 12:02     ` Rex-BC Chen
2022-03-17 12:02     ` Rex-BC Chen
2022-03-17 12:02     ` Rex-BC Chen
2022-03-22  9:23     ` xinlei.lee
2022-03-22  9:23       ` xinlei.lee
2022-03-22  9:23       ` xinlei.lee
2022-03-23 11:46       ` Rex-BC Chen
2022-03-23 11:46         ` Rex-BC Chen
2022-03-23 11:46         ` Rex-BC Chen
2022-04-07  3:50         ` xinlei.lee
2022-04-07  3:50           ` xinlei.lee
2022-04-07  3:50           ` xinlei.lee
2022-03-17  7:53 ` [PATCH v3,3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer xinlei.lee
2022-03-17  7:53   ` [PATCH v3, 3/4] " xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17 12:06   ` [PATCH v3,3/4] " Rex-BC Chen
2022-03-17 12:06     ` Rex-BC Chen
2022-03-17 12:06     ` Rex-BC Chen
2022-03-17 12:06     ` Rex-BC Chen
2022-03-22  9:46     ` xinlei.lee
2022-03-22  9:46       ` xinlei.lee
2022-03-22  9:46       ` xinlei.lee
2022-03-17  7:53 ` [PATCH v3,4/4] drm/mediatek: Add pull-down MIPI operation in mtk_dsi_poweroff function xinlei.lee
2022-03-17  7:53   ` [PATCH v3, 4/4] " xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17  7:53   ` xinlei.lee
2022-03-17 12:20   ` [PATCH v3,4/4] " Rex-BC Chen
2022-03-17 12:20     ` Rex-BC Chen
2022-03-17 12:20     ` Rex-BC Chen
2022-03-17 12:20     ` Rex-BC Chen
2022-03-22 10:00     ` xinlei.lee
2022-03-22 10:00       ` xinlei.lee
2022-03-22 10:00       ` xinlei.lee
2022-03-23 11:54       ` Rex-BC Chen
2022-03-23 11:54         ` Rex-BC Chen
2022-03-23 11:54         ` Rex-BC Chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ca8c83e15808b7c6a54ebd28cead59c18f814023.camel@mediatek.com \
    --to=xinlei.lee@mediatek.com \
    --cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
    --cc=airlied@linux.ie \
    --cc=chunkuang.hu@kernel.org \
    --cc=daniel@ffwll.ch \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=jitao.shi@mediatek.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=matthias.bgg@gmail.com \
    --cc=p.zabel@pengutronix.de \
    --cc=rex-bc.chen@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.