* [PATCH 0/5] phy: miphy28lp: Introduce support for MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez Hi Kishon, The goal of this series is to add the support of MiPHY28lp Generic PHY. I tried to be as close as possible to the MiPHY365x Lee Jones proposal. Best Regards Gabriel. Gabriel Fernandez (5): phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY ARM: DT: STi: STiH407: Add DT node for MiPHY28lp ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 ++++ arch/arm/boot/dts/stih407-b2120.dts | 11 + arch/arm/boot/dts/stih407.dtsi | 65 ++ arch/arm/configs/multi_v7_defconfig | 1 + drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy28lp.c | 736 +++++++++++++++++++++ include/dt-bindings/phy/phy-miphy28lp.h | 12 + 8 files changed, 960 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt create mode 100644 drivers/phy/phy-miphy28lp.c create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h -- 1.9.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 0/5] phy: miphy28lp: Introduce support for MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel Hi Kishon, The goal of this series is to add the support of MiPHY28lp Generic PHY. I tried to be as close as possible to the MiPHY365x Lee Jones proposal. Best Regards Gabriel. Gabriel Fernandez (5): phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY ARM: DT: STi: STiH407: Add DT node for MiPHY28lp ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 ++++ arch/arm/boot/dts/stih407-b2120.dts | 11 + arch/arm/boot/dts/stih407.dtsi | 65 ++ arch/arm/configs/multi_v7_defconfig | 1 + drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy28lp.c | 736 +++++++++++++++++++++ include/dt-bindings/phy/phy-miphy28lp.h | 12 + 8 files changed, 960 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt create mode 100644 drivers/phy/phy-miphy28lp.c create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h -- 1.9.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 0/5] phy: miphy28lp: Introduce support for MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, Gabriel Fernandez, linux-kernel, linux-arm-kernel, kernel Hi Kishon, The goal of this series is to add the support of MiPHY28lp Generic PHY. I tried to be as close as possible to the MiPHY365x Lee Jones proposal. Best Regards Gabriel. Gabriel Fernandez (5): phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY ARM: DT: STi: STiH407: Add DT node for MiPHY28lp ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 ++++ arch/arm/boot/dts/stih407-b2120.dts | 11 + arch/arm/boot/dts/stih407.dtsi | 65 ++ arch/arm/configs/multi_v7_defconfig | 1 + drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy28lp.c | 736 +++++++++++++++++++++ include/dt-bindings/phy/phy-miphy28lp.h | 12 + 8 files changed, 960 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt create mode 100644 drivers/phy/phy-miphy28lp.c create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h -- 1.9.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp 2014-08-13 15:34 ` Gabriel FERNANDEZ @ 2014-08-13 15:34 ` Gabriel FERNANDEZ -1 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt new file mode 100644 index 0000000..6e57bd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt @@ -0,0 +1,126 @@ +STMicroelectronics STi MIPHY28LP PHY binding +============================================ + +This binding describes a miphy device that is used to control PHY hardware +for SATA, PCIe or USB3. + +Required properties (controller (parent) node): +- compatible : Should be "st,miphy28lp-phy" +- st,syscfg : Should be a phandle of the system configuration register group + which contain the SATA, PCIe or USB3 mode setting bits + +Required nodes : A sub-node is required for each channel the controller + provides. Address range information including the usual + 'reg' and 'reg-names' properties are used inside these + nodes to describe the controller's topology. These nodes + are translated by the driver's .xlate() function. + +Required properties (port (child) node): +- #phy-cells : Should be 1 (See second example) + Cell after port phandle is device type from: + - MIPHY_TYPE_SATA + - MIPHY_TYPE_PCI + - MIPHY_TYPE_USB3 +- reg : Address and length of the register set for the device +- reg-names : The names of the register addresses corresponding to the registers + filled in "reg". Is can also contain the offset of the system configuration + registers used as glue-logic to setup the device for SATA/PCIe or USB3 + devices. +- resets : phandle to the parent reset controller. +- reset-names : Associated name must be "miphy-sw-rst". + +Optional properties (port (child) node): +- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This + is not available in all the MiPHY. For example, for STiH407, only the + MiPHY0 has this bit. +- st,osc-force-ext : to select the external oscillator. This can change from + different MiPHY inside the same SoC. +- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config + register. +- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive + line). + +example: + + miphy28lp_phy: miphy28lp@9b22000 { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>, + <0x114 0x4>, /* sysctrl MiPHY cntrl */ + <0x818 0x4>, /* sysctrl MiPHY status*/ + <0xe0 0x4>, /* sysctrl PCIe */ + <0xec 0x4>; /* sysctrl SATA */ + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + st,osc-rdy; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>, + <0x118 0x4>, + <0x81c 0x4>, + <0xe4 0x4>, + <0xf0 0x4>; + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + st,osc-force-ext; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>, + <0x11c 0x4>, + <0x820 0x4>; + reg-names = "pipew", + "usb3-up", + "miphy-ctrl-glue", + "miphy-status-glue"; + #phy-cells = <1>; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; + + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the miphy device node and an index +specifying which configuration to use, as described in phy-bindings.txt. + +example: + sata0: sata@9b20000 { + ... + phys = <&phy_port0 MIPHY_TYPE_SATA>; + ... + }; + +Macro definitions for the supported miphy configuration can be found in: + +include/dt-bindings/phy/phy-miphy28lp.h -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt new file mode 100644 index 0000000..6e57bd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt @@ -0,0 +1,126 @@ +STMicroelectronics STi MIPHY28LP PHY binding +============================================ + +This binding describes a miphy device that is used to control PHY hardware +for SATA, PCIe or USB3. + +Required properties (controller (parent) node): +- compatible : Should be "st,miphy28lp-phy" +- st,syscfg : Should be a phandle of the system configuration register group + which contain the SATA, PCIe or USB3 mode setting bits + +Required nodes : A sub-node is required for each channel the controller + provides. Address range information including the usual + 'reg' and 'reg-names' properties are used inside these + nodes to describe the controller's topology. These nodes + are translated by the driver's .xlate() function. + +Required properties (port (child) node): +- #phy-cells : Should be 1 (See second example) + Cell after port phandle is device type from: + - MIPHY_TYPE_SATA + - MIPHY_TYPE_PCI + - MIPHY_TYPE_USB3 +- reg : Address and length of the register set for the device +- reg-names : The names of the register addresses corresponding to the registers + filled in "reg". Is can also contain the offset of the system configuration + registers used as glue-logic to setup the device for SATA/PCIe or USB3 + devices. +- resets : phandle to the parent reset controller. +- reset-names : Associated name must be "miphy-sw-rst". + +Optional properties (port (child) node): +- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This + is not available in all the MiPHY. For example, for STiH407, only the + MiPHY0 has this bit. +- st,osc-force-ext : to select the external oscillator. This can change from + different MiPHY inside the same SoC. +- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config + register. +- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive + line). + +example: + + miphy28lp_phy: miphy28lp at 9b22000 { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port at 9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>, + <0x114 0x4>, /* sysctrl MiPHY cntrl */ + <0x818 0x4>, /* sysctrl MiPHY status*/ + <0xe0 0x4>, /* sysctrl PCIe */ + <0xec 0x4>; /* sysctrl SATA */ + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + st,osc-rdy; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port at 9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>, + <0x118 0x4>, + <0x81c 0x4>, + <0xe4 0x4>, + <0xf0 0x4>; + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + st,osc-force-ext; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port at 8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>, + <0x11c 0x4>, + <0x820 0x4>; + reg-names = "pipew", + "usb3-up", + "miphy-ctrl-glue", + "miphy-status-glue"; + #phy-cells = <1>; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; + + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the miphy device node and an index +specifying which configuration to use, as described in phy-bindings.txt. + +example: + sata0: sata at 9b20000 { + ... + phys = <&phy_port0 MIPHY_TYPE_SATA>; + ... + }; + +Macro definitions for the supported miphy configuration can be found in: + +include/dt-bindings/phy/phy-miphy28lp.h -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp 2014-08-13 15:34 ` Gabriel FERNANDEZ (?) @ 2014-08-20 14:56 ` Kishon Vijay Abraham I -1 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:56 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > new file mode 100644 > index 0000000..6e57bd5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > @@ -0,0 +1,126 @@ > +STMicroelectronics STi MIPHY28LP PHY binding > +============================================ > + > +This binding describes a miphy device that is used to control PHY hardware > +for SATA, PCIe or USB3. > + > +Required properties (controller (parent) node): > +- compatible : Should be "st,miphy28lp-phy" > +- st,syscfg : Should be a phandle of the system configuration register group ^^^ I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp @ 2014-08-20 14:56 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:56 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > new file mode 100644 > index 0000000..6e57bd5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > @@ -0,0 +1,126 @@ > +STMicroelectronics STi MIPHY28LP PHY binding > +============================================ > + > +This binding describes a miphy device that is used to control PHY hardware > +for SATA, PCIe or USB3. > + > +Required properties (controller (parent) node): > +- compatible : Should be "st,miphy28lp-phy" > +- st,syscfg : Should be a phandle of the system configuration register group ^^^ I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp @ 2014-08-20 14:56 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:56 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Giuseppe Cavallaro, Gabriel Fernandez, kernel On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ > 1 file changed, 126 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > new file mode 100644 > index 0000000..6e57bd5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt > @@ -0,0 +1,126 @@ > +STMicroelectronics STi MIPHY28LP PHY binding > +============================================ > + > +This binding describes a miphy device that is used to control PHY hardware > +for SATA, PCIe or USB3. > + > +Required properties (controller (parent) node): > +- compatible : Should be "st,miphy28lp-phy" > +- st,syscfg : Should be a phandle of the system configuration register group ^^^ I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp 2014-08-20 14:56 ` Kishon Vijay Abraham I (?) @ 2014-08-21 7:12 ` Gabriel Fernandez -1 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, kernel, alexandre torgue, Giuseppe Cavallaro Thanks Kishon, i will fix. BR Gabriel. On 20 August 2014 16:56, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ >> 1 file changed, 126 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> new file mode 100644 >> index 0000000..6e57bd5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> @@ -0,0 +1,126 @@ >> +STMicroelectronics STi MIPHY28LP PHY binding >> +============================================ >> + >> +This binding describes a miphy device that is used to control PHY hardware >> +for SATA, PCIe or USB3. >> + >> +Required properties (controller (parent) node): >> +- compatible : Should be "st,miphy28lp-phy" >> +- st,syscfg : Should be a phandle of the system configuration register group > > ^^^ > I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: linux-arm-kernel Thanks Kishon, i will fix. BR Gabriel. On 20 August 2014 16:56, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ >> 1 file changed, 126 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> new file mode 100644 >> index 0000000..6e57bd5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> @@ -0,0 +1,126 @@ >> +STMicroelectronics STi MIPHY28LP PHY binding >> +============================================ >> + >> +This binding describes a miphy device that is used to control PHY hardware >> +for SATA, PCIe or USB3. >> + >> +Required properties (controller (parent) node): >> +- compatible : Should be "st,miphy28lp-phy" >> +- st,syscfg : Should be a phandle of the system configuration register group > > ^^^ > I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, kernel, alexandre torgue, Giuseppe Cavallaro Thanks Kishon, i will fix. BR Gabriel. On 20 August 2014 16:56, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++ >> 1 file changed, 126 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> new file mode 100644 >> index 0000000..6e57bd5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt >> @@ -0,0 +1,126 @@ >> +STMicroelectronics STi MIPHY28LP PHY binding >> +============================================ >> + >> +This binding describes a miphy device that is used to control PHY hardware >> +for SATA, PCIe or USB3. >> + >> +Required properties (controller (parent) node): >> +- compatible : Should be "st,miphy28lp-phy" >> +- st,syscfg : Should be a phandle of the system configuration register group > > ^^^ > I think here you used space and in the rest of places used tabs. ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines 2014-08-13 15:34 ` Gabriel FERNANDEZ (?) @ 2014-08-13 15:34 ` Gabriel FERNANDEZ -1 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue This provides the shared header file which will be reference from both the MiPHY28lp driver and its associated Device Tree node(s). Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h new file mode 100644 index 0000000..7cf9bce --- /dev/null +++ b/include/dt-bindings/phy/phy-miphy28lp.h @@ -0,0 +1,12 @@ +/* + * This header provides constants for the phy framework + * based on the STMicroelectronics miph28lp. + */ +#ifndef _DT_BINDINGS_PHY_MIPHY28LP +#define _DT_BINDINGS_PHY_MIPHY28LP + +#define MIPHY_TYPE_SATA 1 +#define MIPHY_TYPE_PCIE 2 +#define MIPHY_TYPE_USB 3 + +#endif /* _DT_BINDINGS_PHY_MIPHY28LP */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel This provides the shared header file which will be reference from both the MiPHY28lp driver and its associated Device Tree node(s). Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h new file mode 100644 index 0000000..7cf9bce --- /dev/null +++ b/include/dt-bindings/phy/phy-miphy28lp.h @@ -0,0 +1,12 @@ +/* + * This header provides constants for the phy framework + * based on the STMicroelectronics miph28lp. + */ +#ifndef _DT_BINDINGS_PHY_MIPHY28LP +#define _DT_BINDINGS_PHY_MIPHY28LP + +#define MIPHY_TYPE_SATA 1 +#define MIPHY_TYPE_PCIE 2 +#define MIPHY_TYPE_USB 3 + +#endif /* _DT_BINDINGS_PHY_MIPHY28LP */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Gabriel Fernandez, kernel This provides the shared header file which will be reference from both the MiPHY28lp driver and its associated Device Tree node(s). Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h new file mode 100644 index 0000000..7cf9bce --- /dev/null +++ b/include/dt-bindings/phy/phy-miphy28lp.h @@ -0,0 +1,12 @@ +/* + * This header provides constants for the phy framework + * based on the STMicroelectronics miph28lp. + */ +#ifndef _DT_BINDINGS_PHY_MIPHY28LP +#define _DT_BINDINGS_PHY_MIPHY28LP + +#define MIPHY_TYPE_SATA 1 +#define MIPHY_TYPE_PCIE 2 +#define MIPHY_TYPE_USB 3 + +#endif /* _DT_BINDINGS_PHY_MIPHY28LP */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines 2014-08-13 15:34 ` Gabriel FERNANDEZ (?) @ 2014-08-20 14:53 ` Kishon Vijay Abraham I -1 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:53 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > This provides the shared header file which will be reference from both > the MiPHY28lp driver and its associated Device Tree node(s). > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h > > diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h > new file mode 100644 > index 0000000..7cf9bce > --- /dev/null > +++ b/include/dt-bindings/phy/phy-miphy28lp.h > @@ -0,0 +1,12 @@ > +/* > + * This header provides constants for the phy framework > + * based on the STMicroelectronics miph28lp. > + */ > +#ifndef _DT_BINDINGS_PHY_MIPHY28LP > +#define _DT_BINDINGS_PHY_MIPHY28LP > + > +#define MIPHY_TYPE_SATA 1 > +#define MIPHY_TYPE_PCIE 2 > +#define MIPHY_TYPE_USB 3 I think we should create a common file for phy so that all user's need not create a separate copy of the same thing. Thanks Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-20 14:53 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:53 UTC (permalink / raw) To: linux-arm-kernel Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > This provides the shared header file which will be reference from both > the MiPHY28lp driver and its associated Device Tree node(s). > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h > > diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h > new file mode 100644 > index 0000000..7cf9bce > --- /dev/null > +++ b/include/dt-bindings/phy/phy-miphy28lp.h > @@ -0,0 +1,12 @@ > +/* > + * This header provides constants for the phy framework > + * based on the STMicroelectronics miph28lp. > + */ > +#ifndef _DT_BINDINGS_PHY_MIPHY28LP > +#define _DT_BINDINGS_PHY_MIPHY28LP > + > +#define MIPHY_TYPE_SATA 1 > +#define MIPHY_TYPE_PCIE 2 > +#define MIPHY_TYPE_USB 3 I think we should create a common file for phy so that all user's need not create a separate copy of the same thing. Thanks Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-20 14:53 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:53 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Gabriel Fernandez, kernel Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > This provides the shared header file which will be reference from both > the MiPHY28lp driver and its associated Device Tree node(s). > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h > > diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h > new file mode 100644 > index 0000000..7cf9bce > --- /dev/null > +++ b/include/dt-bindings/phy/phy-miphy28lp.h > @@ -0,0 +1,12 @@ > +/* > + * This header provides constants for the phy framework > + * based on the STMicroelectronics miph28lp. > + */ > +#ifndef _DT_BINDINGS_PHY_MIPHY28LP > +#define _DT_BINDINGS_PHY_MIPHY28LP > + > +#define MIPHY_TYPE_SATA 1 > +#define MIPHY_TYPE_PCIE 2 > +#define MIPHY_TYPE_USB 3 I think we should create a common file for phy so that all user's need not create a separate copy of the same thing. Thanks Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, kernel, alexandre torgue Hi Kishon, Okay, good. BR Gabriel On 20 August 2014 16:53, Kishon Vijay Abraham I <kishon@ti.com> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> This provides the shared header file which will be reference from both >> the MiPHY28lp driver and its associated Device Tree node(s). >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h >> >> diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h >> new file mode 100644 >> index 0000000..7cf9bce >> --- /dev/null >> +++ b/include/dt-bindings/phy/phy-miphy28lp.h >> @@ -0,0 +1,12 @@ >> +/* >> + * This header provides constants for the phy framework >> + * based on the STMicroelectronics miph28lp. >> + */ >> +#ifndef _DT_BINDINGS_PHY_MIPHY28LP >> +#define _DT_BINDINGS_PHY_MIPHY28LP >> + >> +#define MIPHY_TYPE_SATA 1 >> +#define MIPHY_TYPE_PCIE 2 >> +#define MIPHY_TYPE_USB 3 > > I think we should create a common file for phy so that all user's need not > create a separate copy of the same thing. > > Thanks > Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: linux-arm-kernel Hi Kishon, Okay, good. BR Gabriel On 20 August 2014 16:53, Kishon Vijay Abraham I <kishon@ti.com> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> This provides the shared header file which will be reference from both >> the MiPHY28lp driver and its associated Device Tree node(s). >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h >> >> diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h >> new file mode 100644 >> index 0000000..7cf9bce >> --- /dev/null >> +++ b/include/dt-bindings/phy/phy-miphy28lp.h >> @@ -0,0 +1,12 @@ >> +/* >> + * This header provides constants for the phy framework >> + * based on the STMicroelectronics miph28lp. >> + */ >> +#ifndef _DT_BINDINGS_PHY_MIPHY28LP >> +#define _DT_BINDINGS_PHY_MIPHY28LP >> + >> +#define MIPHY_TYPE_SATA 1 >> +#define MIPHY_TYPE_PCIE 2 >> +#define MIPHY_TYPE_USB 3 > > I think we should create a common file for phy so that all user's need not > create a separate copy of the same thing. > > Thanks > Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-F5mvAk5X5gdBDgjK7y7TUQ, alexandre torgue Hi Kishon, Okay, good. BR Gabriel On 20 August 2014 16:53, Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> This provides the shared header file which will be reference from both >> the MiPHY28lp driver and its associated Device Tree node(s). >> >> Signed-off-by: alexandre torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> >> --- >> include/dt-bindings/phy/phy-miphy28lp.h | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> create mode 100644 include/dt-bindings/phy/phy-miphy28lp.h >> >> diff --git a/include/dt-bindings/phy/phy-miphy28lp.h b/include/dt-bindings/phy/phy-miphy28lp.h >> new file mode 100644 >> index 0000000..7cf9bce >> --- /dev/null >> +++ b/include/dt-bindings/phy/phy-miphy28lp.h >> @@ -0,0 +1,12 @@ >> +/* >> + * This header provides constants for the phy framework >> + * based on the STMicroelectronics miph28lp. >> + */ >> +#ifndef _DT_BINDINGS_PHY_MIPHY28LP >> +#define _DT_BINDINGS_PHY_MIPHY28LP >> + >> +#define MIPHY_TYPE_SATA 1 >> +#define MIPHY_TYPE_PCIE 2 >> +#define MIPHY_TYPE_USB 3 > > I think we should create a common file for phy so that all user's need not > create a separate copy of the same thing. > > Thanks > Kishon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY 2014-08-13 15:34 ` Gabriel FERNANDEZ @ 2014-08-13 15:34 ` Gabriel FERNANDEZ -1 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 745 insertions(+) create mode 100644 drivers/phy/phy-miphy28lp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0dd7427..2053f72 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -230,4 +230,12 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_MIPHY28LP + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" + depends on ARCH_STI + depends on GENERIC_PHY + help + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) + that is part of STMicroelectronics STiH407 SoC. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 95c69ed..f7e7c59 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c new file mode 100644 index 0000000..767614c --- /dev/null +++ b/drivers/phy/phy-miphy28lp.c @@ -0,0 +1,736 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). + * + * Author: Alexandre Torgue <alexandre.torgue@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/clk.h> +#include <linux/phy/phy.h> +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +#include <dt-bindings/phy/phy-miphy28lp.h> + +/* MiPHY registers */ +#define MIPHY_STATUS_1 0x02 +#define MIPHY_PHY_RDY 0x01 +#define MIPHY_PLL_HFC_RDY 0x06 +#define MIPHY_COMP_FSM_6 0x3f +#define MIPHY_COMP_DONE 0x80 + +#define MIPHY_CTRL_REG 0x04 +#define MIPHY_PX_RX_POL BIT(5) + +/* + * On STiH407 the glue logic can be different among MiPHY devices; for example: + * MiPHY0: OSC_FORCE_EXT means: + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 + * MiPHY1: OSC_FORCE_EXT means: + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 + * Some devices have not the possibility to check if the osc is ready. + */ +#define MIPHY_OSC_FORCE_EXT BIT(3) +#define MIPHY_OSC_RDY BIT(5) + +#define MIPHY_CTRL_MASK 0xf +#define MIPHY_CTRL_DEFAULT 0 +#define MIPHY_CTRL_SYNC_D_EN BIT(2) + +/* SATA / PCIe defines */ +#define SATA_CTRL_MASK 0x7 +#define PCIE_CTRL_MASK 0xff +#define SATA_CTRL_SELECT_SATA 1 +#define SATA_CTRL_SELECT_PCIE 0 +#define SYSCFG_PCIE_PCIE_VAL 0x80 +#define SATA_SPDMODE 1 + +struct miphy28lp_phy { + struct phy *phy; + struct miphy28lp_dev *phydev; + void __iomem *base; + void __iomem *pipebase; + + bool osc_force_ext; + bool osc_rdy; + bool px_rx_pol_inv; + + struct reset_control *miphy_rst; + + u32 sata_gen; + + /* Sysconfig registers offsets needed to configure the device */ + u32 syscfg_miphy_ctrl; + u32 syscfg_miphy_status; + u32 syscfg_pci; + u32 syscfg_sata; + u8 type; +}; + +struct miphy28lp_dev { + struct device *dev; + struct regmap *regmap; + struct mutex miphy_mutex; + struct miphy28lp_phy **phys; +}; + +struct miphy_initval { + u16 reg; + u16 val; +}; + +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; + +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; + +static const struct miphy_initval miphylp28_initvals_sata[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x1c}, + /* PLL calibration */ + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, + /* Writing The PLL Ratio */ + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, + {0x4e, 0xd1}, + /* Rx Calibration */ + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, + {0x0f, 0x02}, {0x0f, 0x00}, +}; + +static const struct miphy_initval miphylp28_initvals0_pcie[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x14}, {0xeb, 0x1d}, {0x0d, 0x1e}, + {0xd4, 0xa6}, {0xd5, 0xaa}, {0xd6, 0xaa}, {0xd7, 0x00}, + {0xd3, 0x00}, {0x0a, 0x40}, {0x4e, 0xd1}, {0x99, 0x5f}, + {0x0f, 0x00}, {0x0e, 0x05}, {0x63, 0x00}, {0x64, 0xa5}, + {0x49, 0x07}, {0x4a, 0x71}, {0x4b, 0x60}, {0x78, 0x98}, + {0x7a, 0x0d}, {0x7b, 0x00}, {0x7f, 0x79}, {0x80, 0x53}, + {0x0f, 0x01}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xa5}, + {0x49, 0x07}, {0x4a, 0x70}, {0x4b, 0x60}, {0x78, 0x9c}, + {0x7a, 0x0d}, {0x7b, 0x00}, {0x7f, 0x79}, {0x80, 0x6a}, + {0xcd, 0x21}, {0x00, 0x00}, {0x01, 0x05}, {0xe9, 0x00}, + {0x0d, 0x1e}, {0x3a, 0x40}, +}; + +static const struct miphy_initval miphylp28_initvals1_pcie[] = { + {0x01, 0x01}, {0x01, 0x00}, + {0xe9, 0x40}, {0xe3, 0x02}, +}; + +static const struct miphy_initval miphylp28_initvals_usb3[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x1c}, + /* PLL calibration */ + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, {0xc4, 0x70}, + {0xc9, 0x02}, {0xca, 0x02}, {0xcb, 0x02}, {0xcc, 0x0a}, + /* Writing The PLL Ratio */ + {0xd4, 0xa6}, {0xd5, 0xaa}, {0xd6, 0xaa}, {0xd7, 0x04}, + {0xd3, 0x00}, + /* Writing The Speed Rate */ + {0x0f, 0x00}, {0x0e, 0x0a}, + /* RX Channel compensation and calibration */ + {0xc2, 0x1c}, {0x97, 0x51}, {0x98, 0x70}, {0x99, 0x5f}, + {0x9a, 0x22}, {0x9f, 0x0e}, + + {0x7a, 0x05}, {0x7f, 0x78}, {0x30, 0x1b}, + /* Enable GENSEL_SEL and SSC */ + /* TX_SEL=0 swing preemp forced by pipe registres */ + {0x0a, 0x11}, + /* MIPHY Bias boost */ + {0x63, 0x00}, {0x64, 0xa7}, + /* TX compensation offset to re-center TX impedance */ + {0x42, 0x02}, + /* SSC modulation */ + {0x0C, 0x04}, + /* MIPHY TX control */ + {0x0f, 0x00}, {0xe5, 0x5a}, {0xe6, 0xA0}, {0xe4, 0x3c}, + {0xe6, 0xa1}, {0xe3, 0x00}, {0xe3, 0x02}, {0xe3, 0x00}, + /* Rx PI controller settings */ + {0x78, 0xca}, + /* MIPHY RX input bridge control */ + /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */ + {0xcd, 0x21}, {0xcd, 0x29}, {0xce, 0x1a}, + /* MIPHY Reset */ + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, + {0x01, 0x00}, {0xe9, 0x40}, {0x0f, 0x00}, {0x0b, 0x00}, + {0x62, 0x00}, {0x0f, 0x00}, {0xe3, 0x02}, {0x26, 0xa5}, + {0x0f, 0x00}, +}; + +static void miphy_write_initvals(struct miphy28lp_phy *miphy_phy, + const struct miphy_initval *initvals, + int count) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int i; + + for (i = 0; i < count; i++) { + dev_dbg(miphy_dev->dev, "MiPHY28LP reg: 0x%x=0x%x\n", + initvals[i].reg, initvals[i].val); + if (i == 2) + usleep_range(10, 20); /* extra delay after resetting */ + writeb_relaxed(initvals[i].val, + miphy_phy->base + initvals[i].reg); + } +} + +static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) +{ + unsigned long finish = jiffies + 5 * HZ; + u8 mask = MIPHY_PLL_HFC_RDY; + u8 val; + + /* + * For PCIe and USB3 check only that PLL and HFC are ready + * For SATA check also that phy is ready! + */ + if (miphy_phy->type == MIPHY_TYPE_SATA) + mask |= MIPHY_PHY_RDY; + + do { + val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); + if ((val & mask) != mask) + cpu_relax(); + else + return 0; + } while (!time_after_eq(jiffies, finish)); + + return -EBUSY; +} + +static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + unsigned long finish = jiffies + 5 * HZ; + u32 val; + + if (!miphy_phy->osc_rdy) + return 0; + + if (!miphy_phy->syscfg_miphy_status) + return -EINVAL; + + do { + regmap_read(miphy_dev->regmap, miphy_phy->syscfg_miphy_status, + &val); + + if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) + cpu_relax(); + else + return 0; + } while (!time_after_eq(jiffies, finish)); + + return -EBUSY; +} + +static int miphy28lp_get_ressource_byname(struct device_node *child, + char *name, struct resource *res) +{ + int index, ret = 0, count = 0; + int reg_tuple_size; + const __be32 *p; + + reg_tuple_size = (of_n_addr_cells(child) + + of_n_size_cells(child)) * sizeof(u32); + + p = of_get_property(child, "reg", &count); + if (count % reg_tuple_size != 0) + ret = -EINVAL; + + count /= reg_tuple_size; + + for (index = 0; index < count; index++) { + const char *rname = NULL; + + ret = of_property_read_string_index(child, "reg-names", + index, &rname); + if (!strcmp(name, rname)) + return of_address_to_resource(child, index, res); + } + + return 1; +} + +static int miphy28lp_get_one_addr(struct device *dev, + struct device_node *child, char *rname, + void __iomem **base) +{ + struct resource res; + int ret; + + ret = miphy28lp_get_ressource_byname(child, rname, &res); + if (!ret) { + *base = devm_ioremap(dev, res.start, resource_size(&res)); + if (!*base) { + dev_err(dev, "failed to ioremap %s address region\n" + , rname); + return -ENOENT; + } + } + + return 0; +} + +/* MiPHY reset and sysconf setup */ +static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val) +{ + int err; + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + + if (!miphy_phy->syscfg_miphy_ctrl) + return -EINVAL; + + err = reset_control_assert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + if (miphy_phy->osc_force_ext) + miphy_val |= MIPHY_OSC_FORCE_EXT; + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_miphy_ctrl, + MIPHY_CTRL_MASK, miphy_val); + + err = reset_control_deassert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + return miphy_osc_is_ready(miphy_phy); +} + +static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int count, err, sata_conf = SATA_CTRL_SELECT_SATA; + u8 val; + + if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci) + || (!miphy_phy->base)) + return -EINVAL; + + dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); + + /* Configure the glue-logic */ + sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata, + SATA_CTRL_MASK, sata_conf); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci, + PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); + + if (err) { + dev_err(miphy_dev->dev, "SATA phy setup failed\n"); + return err; + } + + /* initialize miphy */ + count = ARRAY_SIZE(miphylp28_initvals_sata); + miphy_write_initvals(miphy_phy, miphylp28_initvals_sata, count); + + if (miphy_phy->px_rx_pol_inv) { + /* Invert Rx polarity */ + val = readb_relaxed(miphy_phy->base + MIPHY_CTRL_REG); + val |= MIPHY_PX_RX_POL; + writeb_relaxed(val, miphy_phy->base + MIPHY_CTRL_REG); + } + + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + unsigned long finish = jiffies + 5 * HZ; + int count, err; + u8 val; + + if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci) + || (!miphy_phy->base) || (!miphy_phy->pipebase)) + return -EINVAL; + + dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); + + /* Configure the glue-logic */ + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata, + SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci, + PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); + + if (err) { + dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); + return err; + } + + count = ARRAY_SIZE(miphylp28_initvals0_pcie); + miphy_write_initvals(miphy_phy, miphylp28_initvals0_pcie, count); + + /* extra delay to wait pll lock */ + usleep_range(100, 120); + + count = ARRAY_SIZE(miphylp28_initvals1_pcie); + miphy_write_initvals(miphy_phy, miphylp28_initvals1_pcie, count); + + /* Waiting for Compensation to complete */ + do { + val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); + if (time_after_eq(jiffies, finish)) + return -EBUSY; + cpu_relax(); + } while (!(val & MIPHY_COMP_DONE)); + + /* PIPE Wrapper Configuration */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ + writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ + writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshhold_0 */ + writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ + + /* Wait for phy_ready */ + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int count, err; + + if ((!miphy_phy->base) || (!miphy_phy->pipebase)) + return -EINVAL; + + dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN); + + if (err) { + dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); + return err; + } + + count = ARRAY_SIZE(miphylp28_initvals_usb3); + miphy_write_initvals(miphy_phy, miphylp28_initvals_usb3, count); + + /* PIPE Wrapper Configuration */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); + writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); + writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); + writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); + writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); + writeb_relaxed(0x60, miphy_phy->pipebase + 0x2a); + + /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ + writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); + writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); + + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init(struct phy *phy) +{ + struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy); + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int ret; + + mutex_lock(&miphy_dev->miphy_mutex); + + switch (miphy_phy->type) { + + case MIPHY_TYPE_SATA: + ret = miphy28lp_init_sata(miphy_phy); + break; + case MIPHY_TYPE_PCIE: + ret = miphy28lp_init_pcie(miphy_phy); + break; + case MIPHY_TYPE_USB: + ret = miphy28lp_init_usb3(miphy_phy); + break; + default: + return -EINVAL; + } + + mutex_unlock(&miphy_dev->miphy_mutex); + + return ret; +} + + +static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + struct device_node *phynode = miphy_phy->phy->dev.of_node; + int err; + + if (!miphy_phy->type || (miphy_phy->type > MIPHY_TYPE_USB)) + return -EINVAL; + + err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, + miphy_type_name[miphy_phy->type - MIPHY_TYPE_SATA], + &miphy_phy->base); + if (err) + return err; + + if ((miphy_phy->type == MIPHY_TYPE_PCIE) || + (miphy_phy->type == MIPHY_TYPE_USB)) { + err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", + &miphy_phy->pipebase); + if (err) + return err; + } + + return 0; +} + +static struct phy *miphy28lp_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev); + struct miphy28lp_phy *miphy_phy = NULL; + struct device_node *phynode = args->np; + int ret, index = 0; + + if (!of_device_is_available(phynode)) { + dev_warn(dev, "Requested PHY is disabled\n"); + return ERR_PTR(-ENODEV); + } + + if (args->args_count != 1) { + dev_err(dev, "Invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + for (index = 0; index < of_get_child_count(dev->of_node); index++) + if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { + miphy_phy = miphy_dev->phys[index]; + break; + } + + if (!miphy_phy) { + dev_err(dev, "Failed to find appropriate phy\n"); + return ERR_PTR(-EINVAL); + } + + miphy_phy->type = args->args[0]; + + ret = miphy28lp_get_addr(miphy_phy); + if (ret < 0) + return ERR_PTR(ret); + + return miphy_phy->phy; +} + +static struct phy_ops miphy28lp_ops = { + .init = miphy28lp_init, + .owner = THIS_MODULE, +}; + +static int miphy28lp_probe_resets(struct device_node *node, + struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int err; + + miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst"); + + if (IS_ERR(miphy_phy->miphy_rst)) { + dev_err(miphy_dev->dev, + "miphy soft reset control not defined\n"); + return PTR_ERR(miphy_phy->miphy_rst); + } + + err = reset_control_deassert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + return 0; +} + +static int miphy28lp_of_probe(struct device_node *np, + struct miphy28lp_phy *miphy_phy) +{ + struct resource res; + + miphy_phy->osc_force_ext = + of_property_read_bool(np, "st,osc-force-ext"); + + miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); + + miphy_phy->px_rx_pol_inv = + of_property_read_bool(np, "st,px_rx_pol_inv"); + + of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); + if (!miphy_phy->sata_gen) + miphy_phy->sata_gen = SATA_GEN1; + + if (!miphy28lp_get_ressource_byname(np, "miphy-ctrl-glue", &res)) + miphy_phy->syscfg_miphy_ctrl = res.start; + + if (!miphy28lp_get_ressource_byname(np, "miphy-status-glue", &res)) + miphy_phy->syscfg_miphy_status = res.start; + + if (!miphy28lp_get_ressource_byname(np, "pcie-glue", &res)) + miphy_phy->syscfg_pci = res.start; + + if (!miphy28lp_get_ressource_byname(np, "sata-glue", &res)) + miphy_phy->syscfg_sata = res.start; + + + return 0; +} + +static int miphy28lp_probe(struct platform_device *pdev) +{ + struct device_node *child, *np = pdev->dev.of_node; + struct miphy28lp_dev *miphy_dev; + struct phy_provider *provider; + struct phy *phy; + int chancount, port = 0; + int ret; + + miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); + if (!miphy_dev) + return -ENOMEM; + + chancount = of_get_child_count(np); + miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount, + GFP_KERNEL); + if (!miphy_dev->phys) + return -ENOMEM; + + miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(miphy_dev->regmap)) { + dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); + return PTR_ERR(miphy_dev->regmap); + } + + miphy_dev->dev = &pdev->dev; + + dev_set_drvdata(&pdev->dev, miphy_dev); + + mutex_init(&miphy_dev->miphy_mutex); + + for_each_child_of_node(np, child) { + struct miphy28lp_phy *miphy_phy; + + miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), + GFP_KERNEL); + if (!miphy_phy) + return -ENOMEM; + + miphy_dev->phys[port] = miphy_phy; + + phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops, NULL); + if (IS_ERR(phy)) { + dev_err(&pdev->dev, "failed to create PHY\n"); + return PTR_ERR(phy); + } + + miphy_dev->phys[port]->phy = phy; + miphy_dev->phys[port]->phydev = miphy_dev; + + ret = miphy28lp_of_probe(child, miphy_phy); + if (ret) + return ret; + + ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); + if (ret) + return ret; + + phy_set_drvdata(phy, miphy_dev->phys[port]); + port++; + + } + + provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + return 0; +} + +static const struct of_device_id miphy28lp_of_match[] = { + {.compatible = "st,miphy28lp-phy", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, miphy28lp_of_match); + +static struct platform_driver miphy28lp_driver = { + .probe = miphy28lp_probe, + .driver = { + .name = "miphy28lp-phy", + .owner = THIS_MODULE, + .of_match_table = miphy28lp_of_match, + } +}; + +module_platform_driver(miphy28lp_driver); + +MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>"); +MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 745 insertions(+) create mode 100644 drivers/phy/phy-miphy28lp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0dd7427..2053f72 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -230,4 +230,12 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_MIPHY28LP + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" + depends on ARCH_STI + depends on GENERIC_PHY + help + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) + that is part of STMicroelectronics STiH407 SoC. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 95c69ed..f7e7c59 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c new file mode 100644 index 0000000..767614c --- /dev/null +++ b/drivers/phy/phy-miphy28lp.c @@ -0,0 +1,736 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). + * + * Author: Alexandre Torgue <alexandre.torgue@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/clk.h> +#include <linux/phy/phy.h> +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +#include <dt-bindings/phy/phy-miphy28lp.h> + +/* MiPHY registers */ +#define MIPHY_STATUS_1 0x02 +#define MIPHY_PHY_RDY 0x01 +#define MIPHY_PLL_HFC_RDY 0x06 +#define MIPHY_COMP_FSM_6 0x3f +#define MIPHY_COMP_DONE 0x80 + +#define MIPHY_CTRL_REG 0x04 +#define MIPHY_PX_RX_POL BIT(5) + +/* + * On STiH407 the glue logic can be different among MiPHY devices; for example: + * MiPHY0: OSC_FORCE_EXT means: + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 + * MiPHY1: OSC_FORCE_EXT means: + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 + * Some devices have not the possibility to check if the osc is ready. + */ +#define MIPHY_OSC_FORCE_EXT BIT(3) +#define MIPHY_OSC_RDY BIT(5) + +#define MIPHY_CTRL_MASK 0xf +#define MIPHY_CTRL_DEFAULT 0 +#define MIPHY_CTRL_SYNC_D_EN BIT(2) + +/* SATA / PCIe defines */ +#define SATA_CTRL_MASK 0x7 +#define PCIE_CTRL_MASK 0xff +#define SATA_CTRL_SELECT_SATA 1 +#define SATA_CTRL_SELECT_PCIE 0 +#define SYSCFG_PCIE_PCIE_VAL 0x80 +#define SATA_SPDMODE 1 + +struct miphy28lp_phy { + struct phy *phy; + struct miphy28lp_dev *phydev; + void __iomem *base; + void __iomem *pipebase; + + bool osc_force_ext; + bool osc_rdy; + bool px_rx_pol_inv; + + struct reset_control *miphy_rst; + + u32 sata_gen; + + /* Sysconfig registers offsets needed to configure the device */ + u32 syscfg_miphy_ctrl; + u32 syscfg_miphy_status; + u32 syscfg_pci; + u32 syscfg_sata; + u8 type; +}; + +struct miphy28lp_dev { + struct device *dev; + struct regmap *regmap; + struct mutex miphy_mutex; + struct miphy28lp_phy **phys; +}; + +struct miphy_initval { + u16 reg; + u16 val; +}; + +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; + +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; + +static const struct miphy_initval miphylp28_initvals_sata[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x1c}, + /* PLL calibration */ + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, + /* Writing The PLL Ratio */ + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, + {0x4e, 0xd1}, + /* Rx Calibration */ + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, + {0x0f, 0x02}, {0x0f, 0x00}, +}; + +static const struct miphy_initval miphylp28_initvals0_pcie[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x14}, {0xeb, 0x1d}, {0x0d, 0x1e}, + {0xd4, 0xa6}, {0xd5, 0xaa}, {0xd6, 0xaa}, {0xd7, 0x00}, + {0xd3, 0x00}, {0x0a, 0x40}, {0x4e, 0xd1}, {0x99, 0x5f}, + {0x0f, 0x00}, {0x0e, 0x05}, {0x63, 0x00}, {0x64, 0xa5}, + {0x49, 0x07}, {0x4a, 0x71}, {0x4b, 0x60}, {0x78, 0x98}, + {0x7a, 0x0d}, {0x7b, 0x00}, {0x7f, 0x79}, {0x80, 0x53}, + {0x0f, 0x01}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xa5}, + {0x49, 0x07}, {0x4a, 0x70}, {0x4b, 0x60}, {0x78, 0x9c}, + {0x7a, 0x0d}, {0x7b, 0x00}, {0x7f, 0x79}, {0x80, 0x6a}, + {0xcd, 0x21}, {0x00, 0x00}, {0x01, 0x05}, {0xe9, 0x00}, + {0x0d, 0x1e}, {0x3a, 0x40}, +}; + +static const struct miphy_initval miphylp28_initvals1_pcie[] = { + {0x01, 0x01}, {0x01, 0x00}, + {0xe9, 0x40}, {0xe3, 0x02}, +}; + +static const struct miphy_initval miphylp28_initvals_usb3[] = { + /* Putting Macro in reset */ + {0x00, 0x01}, {0x00, 0x03}, + /* Wait for a while */ + {0x00, 0x01}, {0x04, 0x1c}, + /* PLL calibration */ + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, {0xc4, 0x70}, + {0xc9, 0x02}, {0xca, 0x02}, {0xcb, 0x02}, {0xcc, 0x0a}, + /* Writing The PLL Ratio */ + {0xd4, 0xa6}, {0xd5, 0xaa}, {0xd6, 0xaa}, {0xd7, 0x04}, + {0xd3, 0x00}, + /* Writing The Speed Rate */ + {0x0f, 0x00}, {0x0e, 0x0a}, + /* RX Channel compensation and calibration */ + {0xc2, 0x1c}, {0x97, 0x51}, {0x98, 0x70}, {0x99, 0x5f}, + {0x9a, 0x22}, {0x9f, 0x0e}, + + {0x7a, 0x05}, {0x7f, 0x78}, {0x30, 0x1b}, + /* Enable GENSEL_SEL and SSC */ + /* TX_SEL=0 swing preemp forced by pipe registres */ + {0x0a, 0x11}, + /* MIPHY Bias boost */ + {0x63, 0x00}, {0x64, 0xa7}, + /* TX compensation offset to re-center TX impedance */ + {0x42, 0x02}, + /* SSC modulation */ + {0x0C, 0x04}, + /* MIPHY TX control */ + {0x0f, 0x00}, {0xe5, 0x5a}, {0xe6, 0xA0}, {0xe4, 0x3c}, + {0xe6, 0xa1}, {0xe3, 0x00}, {0xe3, 0x02}, {0xe3, 0x00}, + /* Rx PI controller settings */ + {0x78, 0xca}, + /* MIPHY RX input bridge control */ + /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */ + {0xcd, 0x21}, {0xcd, 0x29}, {0xce, 0x1a}, + /* MIPHY Reset */ + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, + {0x01, 0x00}, {0xe9, 0x40}, {0x0f, 0x00}, {0x0b, 0x00}, + {0x62, 0x00}, {0x0f, 0x00}, {0xe3, 0x02}, {0x26, 0xa5}, + {0x0f, 0x00}, +}; + +static void miphy_write_initvals(struct miphy28lp_phy *miphy_phy, + const struct miphy_initval *initvals, + int count) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int i; + + for (i = 0; i < count; i++) { + dev_dbg(miphy_dev->dev, "MiPHY28LP reg: 0x%x=0x%x\n", + initvals[i].reg, initvals[i].val); + if (i == 2) + usleep_range(10, 20); /* extra delay after resetting */ + writeb_relaxed(initvals[i].val, + miphy_phy->base + initvals[i].reg); + } +} + +static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) +{ + unsigned long finish = jiffies + 5 * HZ; + u8 mask = MIPHY_PLL_HFC_RDY; + u8 val; + + /* + * For PCIe and USB3 check only that PLL and HFC are ready + * For SATA check also that phy is ready! + */ + if (miphy_phy->type == MIPHY_TYPE_SATA) + mask |= MIPHY_PHY_RDY; + + do { + val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); + if ((val & mask) != mask) + cpu_relax(); + else + return 0; + } while (!time_after_eq(jiffies, finish)); + + return -EBUSY; +} + +static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + unsigned long finish = jiffies + 5 * HZ; + u32 val; + + if (!miphy_phy->osc_rdy) + return 0; + + if (!miphy_phy->syscfg_miphy_status) + return -EINVAL; + + do { + regmap_read(miphy_dev->regmap, miphy_phy->syscfg_miphy_status, + &val); + + if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) + cpu_relax(); + else + return 0; + } while (!time_after_eq(jiffies, finish)); + + return -EBUSY; +} + +static int miphy28lp_get_ressource_byname(struct device_node *child, + char *name, struct resource *res) +{ + int index, ret = 0, count = 0; + int reg_tuple_size; + const __be32 *p; + + reg_tuple_size = (of_n_addr_cells(child) + + of_n_size_cells(child)) * sizeof(u32); + + p = of_get_property(child, "reg", &count); + if (count % reg_tuple_size != 0) + ret = -EINVAL; + + count /= reg_tuple_size; + + for (index = 0; index < count; index++) { + const char *rname = NULL; + + ret = of_property_read_string_index(child, "reg-names", + index, &rname); + if (!strcmp(name, rname)) + return of_address_to_resource(child, index, res); + } + + return 1; +} + +static int miphy28lp_get_one_addr(struct device *dev, + struct device_node *child, char *rname, + void __iomem **base) +{ + struct resource res; + int ret; + + ret = miphy28lp_get_ressource_byname(child, rname, &res); + if (!ret) { + *base = devm_ioremap(dev, res.start, resource_size(&res)); + if (!*base) { + dev_err(dev, "failed to ioremap %s address region\n" + , rname); + return -ENOENT; + } + } + + return 0; +} + +/* MiPHY reset and sysconf setup */ +static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val) +{ + int err; + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + + if (!miphy_phy->syscfg_miphy_ctrl) + return -EINVAL; + + err = reset_control_assert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + if (miphy_phy->osc_force_ext) + miphy_val |= MIPHY_OSC_FORCE_EXT; + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_miphy_ctrl, + MIPHY_CTRL_MASK, miphy_val); + + err = reset_control_deassert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + return miphy_osc_is_ready(miphy_phy); +} + +static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int count, err, sata_conf = SATA_CTRL_SELECT_SATA; + u8 val; + + if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci) + || (!miphy_phy->base)) + return -EINVAL; + + dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); + + /* Configure the glue-logic */ + sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata, + SATA_CTRL_MASK, sata_conf); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci, + PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); + + if (err) { + dev_err(miphy_dev->dev, "SATA phy setup failed\n"); + return err; + } + + /* initialize miphy */ + count = ARRAY_SIZE(miphylp28_initvals_sata); + miphy_write_initvals(miphy_phy, miphylp28_initvals_sata, count); + + if (miphy_phy->px_rx_pol_inv) { + /* Invert Rx polarity */ + val = readb_relaxed(miphy_phy->base + MIPHY_CTRL_REG); + val |= MIPHY_PX_RX_POL; + writeb_relaxed(val, miphy_phy->base + MIPHY_CTRL_REG); + } + + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + unsigned long finish = jiffies + 5 * HZ; + int count, err; + u8 val; + + if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci) + || (!miphy_phy->base) || (!miphy_phy->pipebase)) + return -EINVAL; + + dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); + + /* Configure the glue-logic */ + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata, + SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE); + + regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci, + PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); + + if (err) { + dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); + return err; + } + + count = ARRAY_SIZE(miphylp28_initvals0_pcie); + miphy_write_initvals(miphy_phy, miphylp28_initvals0_pcie, count); + + /* extra delay to wait pll lock */ + usleep_range(100, 120); + + count = ARRAY_SIZE(miphylp28_initvals1_pcie); + miphy_write_initvals(miphy_phy, miphylp28_initvals1_pcie, count); + + /* Waiting for Compensation to complete */ + do { + val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); + if (time_after_eq(jiffies, finish)) + return -EBUSY; + cpu_relax(); + } while (!(val & MIPHY_COMP_DONE)); + + /* PIPE Wrapper Configuration */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ + writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ + writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshhold_0 */ + writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ + + /* Wait for phy_ready */ + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int count, err; + + if ((!miphy_phy->base) || (!miphy_phy->pipebase)) + return -EINVAL; + + dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); + + /* MiPHY path and clocking init */ + err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN); + + if (err) { + dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); + return err; + } + + count = ARRAY_SIZE(miphylp28_initvals_usb3); + miphy_write_initvals(miphy_phy, miphylp28_initvals_usb3, count); + + /* PIPE Wrapper Configuration */ + writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); + writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); + writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); + writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); + writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); + writeb_relaxed(0x60, miphy_phy->pipebase + 0x2a); + + /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ + writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); + writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); + writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); + writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); + + return miphy_is_ready(miphy_phy); +} + +static int miphy28lp_init(struct phy *phy) +{ + struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy); + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int ret; + + mutex_lock(&miphy_dev->miphy_mutex); + + switch (miphy_phy->type) { + + case MIPHY_TYPE_SATA: + ret = miphy28lp_init_sata(miphy_phy); + break; + case MIPHY_TYPE_PCIE: + ret = miphy28lp_init_pcie(miphy_phy); + break; + case MIPHY_TYPE_USB: + ret = miphy28lp_init_usb3(miphy_phy); + break; + default: + return -EINVAL; + } + + mutex_unlock(&miphy_dev->miphy_mutex); + + return ret; +} + + +static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + struct device_node *phynode = miphy_phy->phy->dev.of_node; + int err; + + if (!miphy_phy->type || (miphy_phy->type > MIPHY_TYPE_USB)) + return -EINVAL; + + err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, + miphy_type_name[miphy_phy->type - MIPHY_TYPE_SATA], + &miphy_phy->base); + if (err) + return err; + + if ((miphy_phy->type == MIPHY_TYPE_PCIE) || + (miphy_phy->type == MIPHY_TYPE_USB)) { + err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", + &miphy_phy->pipebase); + if (err) + return err; + } + + return 0; +} + +static struct phy *miphy28lp_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev); + struct miphy28lp_phy *miphy_phy = NULL; + struct device_node *phynode = args->np; + int ret, index = 0; + + if (!of_device_is_available(phynode)) { + dev_warn(dev, "Requested PHY is disabled\n"); + return ERR_PTR(-ENODEV); + } + + if (args->args_count != 1) { + dev_err(dev, "Invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + for (index = 0; index < of_get_child_count(dev->of_node); index++) + if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { + miphy_phy = miphy_dev->phys[index]; + break; + } + + if (!miphy_phy) { + dev_err(dev, "Failed to find appropriate phy\n"); + return ERR_PTR(-EINVAL); + } + + miphy_phy->type = args->args[0]; + + ret = miphy28lp_get_addr(miphy_phy); + if (ret < 0) + return ERR_PTR(ret); + + return miphy_phy->phy; +} + +static struct phy_ops miphy28lp_ops = { + .init = miphy28lp_init, + .owner = THIS_MODULE, +}; + +static int miphy28lp_probe_resets(struct device_node *node, + struct miphy28lp_phy *miphy_phy) +{ + struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; + int err; + + miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst"); + + if (IS_ERR(miphy_phy->miphy_rst)) { + dev_err(miphy_dev->dev, + "miphy soft reset control not defined\n"); + return PTR_ERR(miphy_phy->miphy_rst); + } + + err = reset_control_deassert(miphy_phy->miphy_rst); + if (err) { + dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); + return err; + } + + return 0; +} + +static int miphy28lp_of_probe(struct device_node *np, + struct miphy28lp_phy *miphy_phy) +{ + struct resource res; + + miphy_phy->osc_force_ext = + of_property_read_bool(np, "st,osc-force-ext"); + + miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); + + miphy_phy->px_rx_pol_inv = + of_property_read_bool(np, "st,px_rx_pol_inv"); + + of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); + if (!miphy_phy->sata_gen) + miphy_phy->sata_gen = SATA_GEN1; + + if (!miphy28lp_get_ressource_byname(np, "miphy-ctrl-glue", &res)) + miphy_phy->syscfg_miphy_ctrl = res.start; + + if (!miphy28lp_get_ressource_byname(np, "miphy-status-glue", &res)) + miphy_phy->syscfg_miphy_status = res.start; + + if (!miphy28lp_get_ressource_byname(np, "pcie-glue", &res)) + miphy_phy->syscfg_pci = res.start; + + if (!miphy28lp_get_ressource_byname(np, "sata-glue", &res)) + miphy_phy->syscfg_sata = res.start; + + + return 0; +} + +static int miphy28lp_probe(struct platform_device *pdev) +{ + struct device_node *child, *np = pdev->dev.of_node; + struct miphy28lp_dev *miphy_dev; + struct phy_provider *provider; + struct phy *phy; + int chancount, port = 0; + int ret; + + miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); + if (!miphy_dev) + return -ENOMEM; + + chancount = of_get_child_count(np); + miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount, + GFP_KERNEL); + if (!miphy_dev->phys) + return -ENOMEM; + + miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(miphy_dev->regmap)) { + dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); + return PTR_ERR(miphy_dev->regmap); + } + + miphy_dev->dev = &pdev->dev; + + dev_set_drvdata(&pdev->dev, miphy_dev); + + mutex_init(&miphy_dev->miphy_mutex); + + for_each_child_of_node(np, child) { + struct miphy28lp_phy *miphy_phy; + + miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), + GFP_KERNEL); + if (!miphy_phy) + return -ENOMEM; + + miphy_dev->phys[port] = miphy_phy; + + phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops, NULL); + if (IS_ERR(phy)) { + dev_err(&pdev->dev, "failed to create PHY\n"); + return PTR_ERR(phy); + } + + miphy_dev->phys[port]->phy = phy; + miphy_dev->phys[port]->phydev = miphy_dev; + + ret = miphy28lp_of_probe(child, miphy_phy); + if (ret) + return ret; + + ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); + if (ret) + return ret; + + phy_set_drvdata(phy, miphy_dev->phys[port]); + port++; + + } + + provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + return 0; +} + +static const struct of_device_id miphy28lp_of_match[] = { + {.compatible = "st,miphy28lp-phy", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, miphy28lp_of_match); + +static struct platform_driver miphy28lp_driver = { + .probe = miphy28lp_probe, + .driver = { + .name = "miphy28lp-phy", + .owner = THIS_MODULE, + .of_match_table = miphy28lp_of_match, + } +}; + +module_platform_driver(miphy28lp_driver); + +MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>"); +MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY 2014-08-13 15:34 ` Gabriel FERNANDEZ @ 2014-08-14 12:15 ` Srinivas Kandagatla -1 siblings, 0 replies; 39+ messages in thread From: Srinivas Kandagatla @ 2014-08-14 12:15 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Giuseppe Cavallaro, Gabriel Fernandez, kernel Hi Gabi, I did not review the full patchset but this function caught my attention.. > +}; > + > +static int miphy28lp_get_ressource_byname(struct device_node *child, > + char *name, struct resource *res) > +{ s/miphy28lp_get_ressource_byname/miphy28lp_get_resource_byname > + int index, ret = 0, count = 0; > + int reg_tuple_size; > + const __be32 *p; > + > + reg_tuple_size = (of_n_addr_cells(child) + > + of_n_size_cells(child)) * sizeof(u32); > + > + p = of_get_property(child, "reg", &count); > + if (count % reg_tuple_size != 0) > + ret = -EINVAL; > + > + count /= reg_tuple_size; > + > + for (index = 0; index < count; index++) { > + const char *rname = NULL; > + > + ret = of_property_read_string_index(child, "reg-names", > + index, &rname); > + if (!strcmp(name, rname)) > + return of_address_to_resource(child, index, res); > + } > + > + return 1; This function looks bit complicated, can't we just use: index = of_property_match_string(np, "reg-names", rname); if (index < 0) return -ENODEV; return of_address_to_resource(child, index, res); --srini ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-14 12:15 ` Srinivas Kandagatla 0 siblings, 0 replies; 39+ messages in thread From: Srinivas Kandagatla @ 2014-08-14 12:15 UTC (permalink / raw) To: linux-arm-kernel Hi Gabi, I did not review the full patchset but this function caught my attention.. > +}; > + > +static int miphy28lp_get_ressource_byname(struct device_node *child, > + char *name, struct resource *res) > +{ s/miphy28lp_get_ressource_byname/miphy28lp_get_resource_byname > + int index, ret = 0, count = 0; > + int reg_tuple_size; > + const __be32 *p; > + > + reg_tuple_size = (of_n_addr_cells(child) + > + of_n_size_cells(child)) * sizeof(u32); > + > + p = of_get_property(child, "reg", &count); > + if (count % reg_tuple_size != 0) > + ret = -EINVAL; > + > + count /= reg_tuple_size; > + > + for (index = 0; index < count; index++) { > + const char *rname = NULL; > + > + ret = of_property_read_string_index(child, "reg-names", > + index, &rname); > + if (!strcmp(name, rname)) > + return of_address_to_resource(child, index, res); > + } > + > + return 1; This function looks bit complicated, can't we just use: index = of_property_match_string(np, "reg-names", rname); if (index < 0) return -ENODEV; return of_address_to_resource(child, index, res); --srini ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY 2014-08-14 12:15 ` Srinivas Kandagatla (?) @ 2014-08-14 12:37 ` Gabriel Fernandez -1 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-14 12:37 UTC (permalink / raw) To: Srinivas Kandagatla Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely, devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Giuseppe Cavallaro, kernel Hi Srini, On 14 August 2014 14:15, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote: > Hi Gabi, > > I did not review the full patchset but this function caught my attention.. > > >> +}; >> + >> +static int miphy28lp_get_ressource_byname(struct device_node *child, >> + char *name, struct resource >> *res) >> +{ > > > s/miphy28lp_get_ressource_byname/miphy28lp_get_resource_byname ok > > >> + int index, ret = 0, count = 0; >> + int reg_tuple_size; >> + const __be32 *p; >> + >> + reg_tuple_size = (of_n_addr_cells(child) + >> + of_n_size_cells(child)) * sizeof(u32); >> + >> + p = of_get_property(child, "reg", &count); >> + if (count % reg_tuple_size != 0) >> + ret = -EINVAL; >> + >> + count /= reg_tuple_size; >> + >> + for (index = 0; index < count; index++) { >> + const char *rname = NULL; >> + >> + ret = of_property_read_string_index(child, "reg-names", >> + index, &rname); >> + if (!strcmp(name, rname)) >> + return of_address_to_resource(child, index, res); >> + } >> + >> + return 1; > > This function looks bit complicated, can't we just use: > > index = of_property_match_string(np, "reg-names", rname); > if (index < 0) > return -ENODEV; > > return of_address_to_resource(child, index, res); Indeed it's a little bit simpler... :) > > > > --srini Thanks a lot Srini Best Regards Gabriel ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-14 12:37 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-14 12:37 UTC (permalink / raw) To: linux-arm-kernel Hi Srini, On 14 August 2014 14:15, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote: > Hi Gabi, > > I did not review the full patchset but this function caught my attention.. > > >> +}; >> + >> +static int miphy28lp_get_ressource_byname(struct device_node *child, >> + char *name, struct resource >> *res) >> +{ > > > s/miphy28lp_get_ressource_byname/miphy28lp_get_resource_byname ok > > >> + int index, ret = 0, count = 0; >> + int reg_tuple_size; >> + const __be32 *p; >> + >> + reg_tuple_size = (of_n_addr_cells(child) + >> + of_n_size_cells(child)) * sizeof(u32); >> + >> + p = of_get_property(child, "reg", &count); >> + if (count % reg_tuple_size != 0) >> + ret = -EINVAL; >> + >> + count /= reg_tuple_size; >> + >> + for (index = 0; index < count; index++) { >> + const char *rname = NULL; >> + >> + ret = of_property_read_string_index(child, "reg-names", >> + index, &rname); >> + if (!strcmp(name, rname)) >> + return of_address_to_resource(child, index, res); >> + } >> + >> + return 1; > > This function looks bit complicated, can't we just use: > > index = of_property_match_string(np, "reg-names", rname); > if (index < 0) > return -ENODEV; > > return of_address_to_resource(child, index, res); Indeed it's a little bit simpler... :) > > > > --srini Thanks a lot Srini Best Regards Gabriel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-14 12:37 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-14 12:37 UTC (permalink / raw) To: Srinivas Kandagatla Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely, devicetree, alexandre torgue, linux-kernel, linux-arm-kernel, Giuseppe Cavallaro, kernel Hi Srini, On 14 August 2014 14:15, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> wrote: > Hi Gabi, > > I did not review the full patchset but this function caught my attention.. > > >> +}; >> + >> +static int miphy28lp_get_ressource_byname(struct device_node *child, >> + char *name, struct resource >> *res) >> +{ > > > s/miphy28lp_get_ressource_byname/miphy28lp_get_resource_byname ok > > >> + int index, ret = 0, count = 0; >> + int reg_tuple_size; >> + const __be32 *p; >> + >> + reg_tuple_size = (of_n_addr_cells(child) + >> + of_n_size_cells(child)) * sizeof(u32); >> + >> + p = of_get_property(child, "reg", &count); >> + if (count % reg_tuple_size != 0) >> + ret = -EINVAL; >> + >> + count /= reg_tuple_size; >> + >> + for (index = 0; index < count; index++) { >> + const char *rname = NULL; >> + >> + ret = of_property_read_string_index(child, "reg-names", >> + index, &rname); >> + if (!strcmp(name, rname)) >> + return of_address_to_resource(child, index, res); >> + } >> + >> + return 1; > > This function looks bit complicated, can't we just use: > > index = of_property_match_string(np, "reg-names", rname); > if (index < 0) > return -ENODEV; > > return of_address_to_resource(child, index, res); Indeed it's a little bit simpler... :) > > > > --srini Thanks a lot Srini Best Regards Gabriel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-20 14:58 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:58 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > drivers/phy/Kconfig | 8 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 745 insertions(+) > create mode 100644 drivers/phy/phy-miphy28lp.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 0dd7427..2053f72 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -230,4 +230,12 @@ config PHY_XGENE > help > This option enables support for APM X-Gene SoC multi-purpose PHY. > > +config PHY_MIPHY28LP > + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" > + depends on ARCH_STI > + depends on GENERIC_PHY > + help > + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) > + that is part of STMicroelectronics STiH407 SoC. > + > endmenu > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 95c69ed..f7e7c59 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o > obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o > obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o > obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o > diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c > new file mode 100644 > index 0000000..767614c > --- /dev/null > +++ b/drivers/phy/phy-miphy28lp.c > @@ -0,0 +1,736 @@ > +/* > + * Copyright (C) 2014 STMicroelectronics > + * > + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). > + * > + * Author: Alexandre Torgue <alexandre.torgue@st.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2, as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/platform_device.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/of_address.h> > +#include <linux/clk.h> > +#include <linux/phy/phy.h> > +#include <linux/delay.h> > +#include <linux/mfd/syscon.h> > +#include <linux/regmap.h> > +#include <linux/reset.h> > + > +#include <dt-bindings/phy/phy-miphy28lp.h> > + > +/* MiPHY registers */ > +#define MIPHY_STATUS_1 0x02 > +#define MIPHY_PHY_RDY 0x01 > +#define MIPHY_PLL_HFC_RDY 0x06 > +#define MIPHY_COMP_FSM_6 0x3f > +#define MIPHY_COMP_DONE 0x80 > + > +#define MIPHY_CTRL_REG 0x04 > +#define MIPHY_PX_RX_POL BIT(5) > + > +/* > + * On STiH407 the glue logic can be different among MiPHY devices; for example: > + * MiPHY0: OSC_FORCE_EXT means: > + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 > + * MiPHY1: OSC_FORCE_EXT means: > + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 > + * Some devices have not the possibility to check if the osc is ready. > + */ > +#define MIPHY_OSC_FORCE_EXT BIT(3) > +#define MIPHY_OSC_RDY BIT(5) > + > +#define MIPHY_CTRL_MASK 0xf > +#define MIPHY_CTRL_DEFAULT 0 > +#define MIPHY_CTRL_SYNC_D_EN BIT(2) > + > +/* SATA / PCIe defines */ > +#define SATA_CTRL_MASK 0x7 > +#define PCIE_CTRL_MASK 0xff > +#define SATA_CTRL_SELECT_SATA 1 > +#define SATA_CTRL_SELECT_PCIE 0 > +#define SYSCFG_PCIE_PCIE_VAL 0x80 > +#define SATA_SPDMODE 1 > + > +struct miphy28lp_phy { > + struct phy *phy; > + struct miphy28lp_dev *phydev; > + void __iomem *base; > + void __iomem *pipebase; > + > + bool osc_force_ext; > + bool osc_rdy; > + bool px_rx_pol_inv; > + > + struct reset_control *miphy_rst; > + > + u32 sata_gen; > + > + /* Sysconfig registers offsets needed to configure the device */ > + u32 syscfg_miphy_ctrl; > + u32 syscfg_miphy_status; > + u32 syscfg_pci; > + u32 syscfg_sata; > + u8 type; > +}; > + > +struct miphy28lp_dev { > + struct device *dev; > + struct regmap *regmap; > + struct mutex miphy_mutex; > + struct miphy28lp_phy **phys; > +}; > + > +struct miphy_initval { > + u16 reg; > + u16 val; > +}; > + > +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; > + > +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; > + > +static const struct miphy_initval miphylp28_initvals_sata[] = { > + /* Putting Macro in reset */ > + {0x00, 0x01}, {0x00, 0x03}, > + /* Wait for a while */ > + {0x00, 0x01}, {0x04, 0x1c}, > + /* PLL calibration */ > + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, > + /* Writing The PLL Ratio */ > + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, > + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, > + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, > + {0x4e, 0xd1}, > + /* Rx Calibration */ > + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, > + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, > + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, > + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, > + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, > + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, > + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, > + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, > + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, > + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, > + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, > + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, > + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, > + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, > + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, > + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, > + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, > + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, > + {0x0f, 0x02}, {0x0f, 0x00}, I'm not in for doing this sort of initialization. Sorry. Thanks Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-20 14:58 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:58 UTC (permalink / raw) To: linux-arm-kernel Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> > --- > drivers/phy/Kconfig | 8 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 745 insertions(+) > create mode 100644 drivers/phy/phy-miphy28lp.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 0dd7427..2053f72 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -230,4 +230,12 @@ config PHY_XGENE > help > This option enables support for APM X-Gene SoC multi-purpose PHY. > > +config PHY_MIPHY28LP > + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" > + depends on ARCH_STI > + depends on GENERIC_PHY > + help > + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) > + that is part of STMicroelectronics STiH407 SoC. > + > endmenu > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 95c69ed..f7e7c59 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o > obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o > obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o > obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o > diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c > new file mode 100644 > index 0000000..767614c > --- /dev/null > +++ b/drivers/phy/phy-miphy28lp.c > @@ -0,0 +1,736 @@ > +/* > + * Copyright (C) 2014 STMicroelectronics > + * > + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). > + * > + * Author: Alexandre Torgue <alexandre.torgue@st.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2, as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/platform_device.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/of_address.h> > +#include <linux/clk.h> > +#include <linux/phy/phy.h> > +#include <linux/delay.h> > +#include <linux/mfd/syscon.h> > +#include <linux/regmap.h> > +#include <linux/reset.h> > + > +#include <dt-bindings/phy/phy-miphy28lp.h> > + > +/* MiPHY registers */ > +#define MIPHY_STATUS_1 0x02 > +#define MIPHY_PHY_RDY 0x01 > +#define MIPHY_PLL_HFC_RDY 0x06 > +#define MIPHY_COMP_FSM_6 0x3f > +#define MIPHY_COMP_DONE 0x80 > + > +#define MIPHY_CTRL_REG 0x04 > +#define MIPHY_PX_RX_POL BIT(5) > + > +/* > + * On STiH407 the glue logic can be different among MiPHY devices; for example: > + * MiPHY0: OSC_FORCE_EXT means: > + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 > + * MiPHY1: OSC_FORCE_EXT means: > + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 > + * Some devices have not the possibility to check if the osc is ready. > + */ > +#define MIPHY_OSC_FORCE_EXT BIT(3) > +#define MIPHY_OSC_RDY BIT(5) > + > +#define MIPHY_CTRL_MASK 0xf > +#define MIPHY_CTRL_DEFAULT 0 > +#define MIPHY_CTRL_SYNC_D_EN BIT(2) > + > +/* SATA / PCIe defines */ > +#define SATA_CTRL_MASK 0x7 > +#define PCIE_CTRL_MASK 0xff > +#define SATA_CTRL_SELECT_SATA 1 > +#define SATA_CTRL_SELECT_PCIE 0 > +#define SYSCFG_PCIE_PCIE_VAL 0x80 > +#define SATA_SPDMODE 1 > + > +struct miphy28lp_phy { > + struct phy *phy; > + struct miphy28lp_dev *phydev; > + void __iomem *base; > + void __iomem *pipebase; > + > + bool osc_force_ext; > + bool osc_rdy; > + bool px_rx_pol_inv; > + > + struct reset_control *miphy_rst; > + > + u32 sata_gen; > + > + /* Sysconfig registers offsets needed to configure the device */ > + u32 syscfg_miphy_ctrl; > + u32 syscfg_miphy_status; > + u32 syscfg_pci; > + u32 syscfg_sata; > + u8 type; > +}; > + > +struct miphy28lp_dev { > + struct device *dev; > + struct regmap *regmap; > + struct mutex miphy_mutex; > + struct miphy28lp_phy **phys; > +}; > + > +struct miphy_initval { > + u16 reg; > + u16 val; > +}; > + > +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; > + > +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; > + > +static const struct miphy_initval miphylp28_initvals_sata[] = { > + /* Putting Macro in reset */ > + {0x00, 0x01}, {0x00, 0x03}, > + /* Wait for a while */ > + {0x00, 0x01}, {0x04, 0x1c}, > + /* PLL calibration */ > + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, > + /* Writing The PLL Ratio */ > + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, > + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, > + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, > + {0x4e, 0xd1}, > + /* Rx Calibration */ > + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, > + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, > + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, > + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, > + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, > + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, > + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, > + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, > + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, > + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, > + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, > + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, > + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, > + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, > + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, > + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, > + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, > + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, > + {0x0f, 0x02}, {0x0f, 0x00}, I'm not in for doing this sort of initialization. Sorry. Thanks Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-20 14:58 ` Kishon Vijay Abraham I 0 siblings, 0 replies; 39+ messages in thread From: Kishon Vijay Abraham I @ 2014-08-20 14:58 UTC (permalink / raw) To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-F5mvAk5X5gdBDgjK7y7TUQ, Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro Hi, On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: > The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe > or USB3 devices. > > Signed-off-by: alexandre torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org> > Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro-qxv4g6HH51o@public.gmane.org> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> > --- > drivers/phy/Kconfig | 8 + > drivers/phy/Makefile | 1 + > drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 745 insertions(+) > create mode 100644 drivers/phy/phy-miphy28lp.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 0dd7427..2053f72 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -230,4 +230,12 @@ config PHY_XGENE > help > This option enables support for APM X-Gene SoC multi-purpose PHY. > > +config PHY_MIPHY28LP > + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" > + depends on ARCH_STI > + depends on GENERIC_PHY > + help > + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) > + that is part of STMicroelectronics STiH407 SoC. > + > endmenu > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 95c69ed..f7e7c59 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o > obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o > obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o > obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o > obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o > diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c > new file mode 100644 > index 0000000..767614c > --- /dev/null > +++ b/drivers/phy/phy-miphy28lp.c > @@ -0,0 +1,736 @@ > +/* > + * Copyright (C) 2014 STMicroelectronics > + * > + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). > + * > + * Author: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2, as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/platform_device.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/of_address.h> > +#include <linux/clk.h> > +#include <linux/phy/phy.h> > +#include <linux/delay.h> > +#include <linux/mfd/syscon.h> > +#include <linux/regmap.h> > +#include <linux/reset.h> > + > +#include <dt-bindings/phy/phy-miphy28lp.h> > + > +/* MiPHY registers */ > +#define MIPHY_STATUS_1 0x02 > +#define MIPHY_PHY_RDY 0x01 > +#define MIPHY_PLL_HFC_RDY 0x06 > +#define MIPHY_COMP_FSM_6 0x3f > +#define MIPHY_COMP_DONE 0x80 > + > +#define MIPHY_CTRL_REG 0x04 > +#define MIPHY_PX_RX_POL BIT(5) > + > +/* > + * On STiH407 the glue logic can be different among MiPHY devices; for example: > + * MiPHY0: OSC_FORCE_EXT means: > + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 > + * MiPHY1: OSC_FORCE_EXT means: > + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 > + * Some devices have not the possibility to check if the osc is ready. > + */ > +#define MIPHY_OSC_FORCE_EXT BIT(3) > +#define MIPHY_OSC_RDY BIT(5) > + > +#define MIPHY_CTRL_MASK 0xf > +#define MIPHY_CTRL_DEFAULT 0 > +#define MIPHY_CTRL_SYNC_D_EN BIT(2) > + > +/* SATA / PCIe defines */ > +#define SATA_CTRL_MASK 0x7 > +#define PCIE_CTRL_MASK 0xff > +#define SATA_CTRL_SELECT_SATA 1 > +#define SATA_CTRL_SELECT_PCIE 0 > +#define SYSCFG_PCIE_PCIE_VAL 0x80 > +#define SATA_SPDMODE 1 > + > +struct miphy28lp_phy { > + struct phy *phy; > + struct miphy28lp_dev *phydev; > + void __iomem *base; > + void __iomem *pipebase; > + > + bool osc_force_ext; > + bool osc_rdy; > + bool px_rx_pol_inv; > + > + struct reset_control *miphy_rst; > + > + u32 sata_gen; > + > + /* Sysconfig registers offsets needed to configure the device */ > + u32 syscfg_miphy_ctrl; > + u32 syscfg_miphy_status; > + u32 syscfg_pci; > + u32 syscfg_sata; > + u8 type; > +}; > + > +struct miphy28lp_dev { > + struct device *dev; > + struct regmap *regmap; > + struct mutex miphy_mutex; > + struct miphy28lp_phy **phys; > +}; > + > +struct miphy_initval { > + u16 reg; > + u16 val; > +}; > + > +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; > + > +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; > + > +static const struct miphy_initval miphylp28_initvals_sata[] = { > + /* Putting Macro in reset */ > + {0x00, 0x01}, {0x00, 0x03}, > + /* Wait for a while */ > + {0x00, 0x01}, {0x04, 0x1c}, > + /* PLL calibration */ > + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, > + /* Writing The PLL Ratio */ > + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, > + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, > + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, > + {0x4e, 0xd1}, > + /* Rx Calibration */ > + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, > + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, > + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, > + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, > + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, > + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, > + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, > + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, > + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, > + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, > + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, > + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, > + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, > + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, > + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, > + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, > + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, > + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, > + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, > + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, > + {0x0f, 0x02}, {0x0f, 0x00}, I'm not in for doing this sort of initialization. Sorry. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY 2014-08-20 14:58 ` Kishon Vijay Abraham I (?) @ 2014-08-21 7:12 ` Gabriel Fernandez -1 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, kernel, alexandre torgue, Giuseppe Cavallaro Hi Kishon, ok i'll split into specific procedures. BR Gabriel. On 20 August 2014 16:58, Kishon Vijay Abraham I <kishon@ti.com> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> drivers/phy/Kconfig | 8 + >> drivers/phy/Makefile | 1 + >> drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 745 insertions(+) >> create mode 100644 drivers/phy/phy-miphy28lp.c >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 0dd7427..2053f72 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -230,4 +230,12 @@ config PHY_XGENE >> help >> This option enables support for APM X-Gene SoC multi-purpose PHY. >> >> +config PHY_MIPHY28LP >> + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" >> + depends on ARCH_STI >> + depends on GENERIC_PHY >> + help >> + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) >> + that is part of STMicroelectronics STiH407 SoC. >> + >> endmenu >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> index 95c69ed..f7e7c59 100644 >> --- a/drivers/phy/Makefile >> +++ b/drivers/phy/Makefile >> @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o >> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o >> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o >> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o >> +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o >> obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o >> obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o >> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o >> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c >> new file mode 100644 >> index 0000000..767614c >> --- /dev/null >> +++ b/drivers/phy/phy-miphy28lp.c >> @@ -0,0 +1,736 @@ >> +/* >> + * Copyright (C) 2014 STMicroelectronics >> + * >> + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). >> + * >> + * Author: Alexandre Torgue <alexandre.torgue@st.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2, as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#include <linux/platform_device.h> >> +#include <linux/io.h> >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_platform.h> >> +#include <linux/of_address.h> >> +#include <linux/clk.h> >> +#include <linux/phy/phy.h> >> +#include <linux/delay.h> >> +#include <linux/mfd/syscon.h> >> +#include <linux/regmap.h> >> +#include <linux/reset.h> >> + >> +#include <dt-bindings/phy/phy-miphy28lp.h> >> + >> +/* MiPHY registers */ >> +#define MIPHY_STATUS_1 0x02 >> +#define MIPHY_PHY_RDY 0x01 >> +#define MIPHY_PLL_HFC_RDY 0x06 >> +#define MIPHY_COMP_FSM_6 0x3f >> +#define MIPHY_COMP_DONE 0x80 >> + >> +#define MIPHY_CTRL_REG 0x04 >> +#define MIPHY_PX_RX_POL BIT(5) >> + >> +/* >> + * On STiH407 the glue logic can be different among MiPHY devices; for example: >> + * MiPHY0: OSC_FORCE_EXT means: >> + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 >> + * MiPHY1: OSC_FORCE_EXT means: >> + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 >> + * Some devices have not the possibility to check if the osc is ready. >> + */ >> +#define MIPHY_OSC_FORCE_EXT BIT(3) >> +#define MIPHY_OSC_RDY BIT(5) >> + >> +#define MIPHY_CTRL_MASK 0xf >> +#define MIPHY_CTRL_DEFAULT 0 >> +#define MIPHY_CTRL_SYNC_D_EN BIT(2) >> + >> +/* SATA / PCIe defines */ >> +#define SATA_CTRL_MASK 0x7 >> +#define PCIE_CTRL_MASK 0xff >> +#define SATA_CTRL_SELECT_SATA 1 >> +#define SATA_CTRL_SELECT_PCIE 0 >> +#define SYSCFG_PCIE_PCIE_VAL 0x80 >> +#define SATA_SPDMODE 1 >> + >> +struct miphy28lp_phy { >> + struct phy *phy; >> + struct miphy28lp_dev *phydev; >> + void __iomem *base; >> + void __iomem *pipebase; >> + >> + bool osc_force_ext; >> + bool osc_rdy; >> + bool px_rx_pol_inv; >> + >> + struct reset_control *miphy_rst; >> + >> + u32 sata_gen; >> + >> + /* Sysconfig registers offsets needed to configure the device */ >> + u32 syscfg_miphy_ctrl; >> + u32 syscfg_miphy_status; >> + u32 syscfg_pci; >> + u32 syscfg_sata; >> + u8 type; >> +}; >> + >> +struct miphy28lp_dev { >> + struct device *dev; >> + struct regmap *regmap; >> + struct mutex miphy_mutex; >> + struct miphy28lp_phy **phys; >> +}; >> + >> +struct miphy_initval { >> + u16 reg; >> + u16 val; >> +}; >> + >> +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; >> + >> +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; >> + >> +static const struct miphy_initval miphylp28_initvals_sata[] = { >> + /* Putting Macro in reset */ >> + {0x00, 0x01}, {0x00, 0x03}, >> + /* Wait for a while */ >> + {0x00, 0x01}, {0x04, 0x1c}, >> + /* PLL calibration */ >> + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, >> + /* Writing The PLL Ratio */ >> + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, >> + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, >> + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, >> + {0x4e, 0xd1}, >> + /* Rx Calibration */ >> + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, >> + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, >> + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, >> + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, >> + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, >> + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, >> + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, >> + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, >> + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, >> + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, >> + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, >> + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, >> + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, >> + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, >> + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, >> + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, >> + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, >> + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, >> + {0x0f, 0x02}, {0x0f, 0x00}, > > I'm not in for doing this sort of initialization. Sorry. > > Thanks > Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: linux-arm-kernel Hi Kishon, ok i'll split into specific procedures. BR Gabriel. On 20 August 2014 16:58, Kishon Vijay Abraham I <kishon@ti.com> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> drivers/phy/Kconfig | 8 + >> drivers/phy/Makefile | 1 + >> drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 745 insertions(+) >> create mode 100644 drivers/phy/phy-miphy28lp.c >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 0dd7427..2053f72 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -230,4 +230,12 @@ config PHY_XGENE >> help >> This option enables support for APM X-Gene SoC multi-purpose PHY. >> >> +config PHY_MIPHY28LP >> + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" >> + depends on ARCH_STI >> + depends on GENERIC_PHY >> + help >> + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) >> + that is part of STMicroelectronics STiH407 SoC. >> + >> endmenu >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> index 95c69ed..f7e7c59 100644 >> --- a/drivers/phy/Makefile >> +++ b/drivers/phy/Makefile >> @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o >> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o >> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o >> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o >> +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o >> obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o >> obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o >> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o >> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c >> new file mode 100644 >> index 0000000..767614c >> --- /dev/null >> +++ b/drivers/phy/phy-miphy28lp.c >> @@ -0,0 +1,736 @@ >> +/* >> + * Copyright (C) 2014 STMicroelectronics >> + * >> + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). >> + * >> + * Author: Alexandre Torgue <alexandre.torgue@st.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2, as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#include <linux/platform_device.h> >> +#include <linux/io.h> >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_platform.h> >> +#include <linux/of_address.h> >> +#include <linux/clk.h> >> +#include <linux/phy/phy.h> >> +#include <linux/delay.h> >> +#include <linux/mfd/syscon.h> >> +#include <linux/regmap.h> >> +#include <linux/reset.h> >> + >> +#include <dt-bindings/phy/phy-miphy28lp.h> >> + >> +/* MiPHY registers */ >> +#define MIPHY_STATUS_1 0x02 >> +#define MIPHY_PHY_RDY 0x01 >> +#define MIPHY_PLL_HFC_RDY 0x06 >> +#define MIPHY_COMP_FSM_6 0x3f >> +#define MIPHY_COMP_DONE 0x80 >> + >> +#define MIPHY_CTRL_REG 0x04 >> +#define MIPHY_PX_RX_POL BIT(5) >> + >> +/* >> + * On STiH407 the glue logic can be different among MiPHY devices; for example: >> + * MiPHY0: OSC_FORCE_EXT means: >> + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 >> + * MiPHY1: OSC_FORCE_EXT means: >> + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 >> + * Some devices have not the possibility to check if the osc is ready. >> + */ >> +#define MIPHY_OSC_FORCE_EXT BIT(3) >> +#define MIPHY_OSC_RDY BIT(5) >> + >> +#define MIPHY_CTRL_MASK 0xf >> +#define MIPHY_CTRL_DEFAULT 0 >> +#define MIPHY_CTRL_SYNC_D_EN BIT(2) >> + >> +/* SATA / PCIe defines */ >> +#define SATA_CTRL_MASK 0x7 >> +#define PCIE_CTRL_MASK 0xff >> +#define SATA_CTRL_SELECT_SATA 1 >> +#define SATA_CTRL_SELECT_PCIE 0 >> +#define SYSCFG_PCIE_PCIE_VAL 0x80 >> +#define SATA_SPDMODE 1 >> + >> +struct miphy28lp_phy { >> + struct phy *phy; >> + struct miphy28lp_dev *phydev; >> + void __iomem *base; >> + void __iomem *pipebase; >> + >> + bool osc_force_ext; >> + bool osc_rdy; >> + bool px_rx_pol_inv; >> + >> + struct reset_control *miphy_rst; >> + >> + u32 sata_gen; >> + >> + /* Sysconfig registers offsets needed to configure the device */ >> + u32 syscfg_miphy_ctrl; >> + u32 syscfg_miphy_status; >> + u32 syscfg_pci; >> + u32 syscfg_sata; >> + u8 type; >> +}; >> + >> +struct miphy28lp_dev { >> + struct device *dev; >> + struct regmap *regmap; >> + struct mutex miphy_mutex; >> + struct miphy28lp_phy **phys; >> +}; >> + >> +struct miphy_initval { >> + u16 reg; >> + u16 val; >> +}; >> + >> +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; >> + >> +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; >> + >> +static const struct miphy_initval miphylp28_initvals_sata[] = { >> + /* Putting Macro in reset */ >> + {0x00, 0x01}, {0x00, 0x03}, >> + /* Wait for a while */ >> + {0x00, 0x01}, {0x04, 0x1c}, >> + /* PLL calibration */ >> + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, >> + /* Writing The PLL Ratio */ >> + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, >> + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, >> + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, >> + {0x4e, 0xd1}, >> + /* Rx Calibration */ >> + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, >> + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, >> + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, >> + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, >> + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, >> + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, >> + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, >> + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, >> + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, >> + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, >> + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, >> + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, >> + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, >> + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, >> + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, >> + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, >> + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, >> + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, >> + {0x0f, 0x02}, {0x0f, 0x00}, > > I'm not in for doing this sort of initialization. Sorry. > > Thanks > Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY @ 2014-08-21 7:12 ` Gabriel Fernandez 0 siblings, 0 replies; 39+ messages in thread From: Gabriel Fernandez @ 2014-08-21 7:12 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Grant Likely, devicetree, linux-kernel, linux-arm-kernel, kernel, alexandre torgue, Giuseppe Cavallaro Hi Kishon, ok i'll split into specific procedures. BR Gabriel. On 20 August 2014 16:58, Kishon Vijay Abraham I <kishon@ti.com> wrote: > Hi, > > On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote: >> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe >> or USB3 devices. >> >> Signed-off-by: alexandre torgue <alexandre.torgue@st.com> >> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> >> --- >> drivers/phy/Kconfig | 8 + >> drivers/phy/Makefile | 1 + >> drivers/phy/phy-miphy28lp.c | 736 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 745 insertions(+) >> create mode 100644 drivers/phy/phy-miphy28lp.c >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 0dd7427..2053f72 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -230,4 +230,12 @@ config PHY_XGENE >> help >> This option enables support for APM X-Gene SoC multi-purpose PHY. >> >> +config PHY_MIPHY28LP >> + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" >> + depends on ARCH_STI >> + depends on GENERIC_PHY >> + help >> + Enable this to support the miphy transceiver (for SATA/PCIE/USB3) >> + that is part of STMicroelectronics STiH407 SoC. >> + >> endmenu >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> index 95c69ed..f7e7c59 100644 >> --- a/drivers/phy/Makefile >> +++ b/drivers/phy/Makefile >> @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o >> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o >> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o >> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o >> +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o >> obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o >> obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o >> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o >> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c >> new file mode 100644 >> index 0000000..767614c >> --- /dev/null >> +++ b/drivers/phy/phy-miphy28lp.c >> @@ -0,0 +1,736 @@ >> +/* >> + * Copyright (C) 2014 STMicroelectronics >> + * >> + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). >> + * >> + * Author: Alexandre Torgue <alexandre.torgue@st.com> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2, as >> + * published by the Free Software Foundation. >> + * >> + */ >> + >> +#include <linux/platform_device.h> >> +#include <linux/io.h> >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_platform.h> >> +#include <linux/of_address.h> >> +#include <linux/clk.h> >> +#include <linux/phy/phy.h> >> +#include <linux/delay.h> >> +#include <linux/mfd/syscon.h> >> +#include <linux/regmap.h> >> +#include <linux/reset.h> >> + >> +#include <dt-bindings/phy/phy-miphy28lp.h> >> + >> +/* MiPHY registers */ >> +#define MIPHY_STATUS_1 0x02 >> +#define MIPHY_PHY_RDY 0x01 >> +#define MIPHY_PLL_HFC_RDY 0x06 >> +#define MIPHY_COMP_FSM_6 0x3f >> +#define MIPHY_COMP_DONE 0x80 >> + >> +#define MIPHY_CTRL_REG 0x04 >> +#define MIPHY_PX_RX_POL BIT(5) >> + >> +/* >> + * On STiH407 the glue logic can be different among MiPHY devices; for example: >> + * MiPHY0: OSC_FORCE_EXT means: >> + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 >> + * MiPHY1: OSC_FORCE_EXT means: >> + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 >> + * Some devices have not the possibility to check if the osc is ready. >> + */ >> +#define MIPHY_OSC_FORCE_EXT BIT(3) >> +#define MIPHY_OSC_RDY BIT(5) >> + >> +#define MIPHY_CTRL_MASK 0xf >> +#define MIPHY_CTRL_DEFAULT 0 >> +#define MIPHY_CTRL_SYNC_D_EN BIT(2) >> + >> +/* SATA / PCIe defines */ >> +#define SATA_CTRL_MASK 0x7 >> +#define PCIE_CTRL_MASK 0xff >> +#define SATA_CTRL_SELECT_SATA 1 >> +#define SATA_CTRL_SELECT_PCIE 0 >> +#define SYSCFG_PCIE_PCIE_VAL 0x80 >> +#define SATA_SPDMODE 1 >> + >> +struct miphy28lp_phy { >> + struct phy *phy; >> + struct miphy28lp_dev *phydev; >> + void __iomem *base; >> + void __iomem *pipebase; >> + >> + bool osc_force_ext; >> + bool osc_rdy; >> + bool px_rx_pol_inv; >> + >> + struct reset_control *miphy_rst; >> + >> + u32 sata_gen; >> + >> + /* Sysconfig registers offsets needed to configure the device */ >> + u32 syscfg_miphy_ctrl; >> + u32 syscfg_miphy_status; >> + u32 syscfg_pci; >> + u32 syscfg_sata; >> + u8 type; >> +}; >> + >> +struct miphy28lp_dev { >> + struct device *dev; >> + struct regmap *regmap; >> + struct mutex miphy_mutex; >> + struct miphy28lp_phy **phys; >> +}; >> + >> +struct miphy_initval { >> + u16 reg; >> + u16 val; >> +}; >> + >> +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; >> + >> +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" }; >> + >> +static const struct miphy_initval miphylp28_initvals_sata[] = { >> + /* Putting Macro in reset */ >> + {0x00, 0x01}, {0x00, 0x03}, >> + /* Wait for a while */ >> + {0x00, 0x01}, {0x04, 0x1c}, >> + /* PLL calibration */ >> + {0xeb, 0x1d}, {0x0d, 0x1e}, {0x0f, 0x00}, >> + /* Writing The PLL Ratio */ >> + {0xd4, 0xc8}, {0xd5, 0x00}, {0xd6, 0x00}, {0xd7, 0x00}, >> + {0xd3, 0x00}, {0x0f, 0x02}, {0x0e, 0x0a}, {0x0f, 0x01}, >> + {0x0e, 0x0a}, {0x0f, 0x00}, {0x0e, 0x0a}, {0x4e, 0xd1}, >> + {0x4e, 0xd1}, >> + /* Rx Calibration */ >> + {0x99, 0x1f}, {0x0a, 0x41}, {0x7a, 0x0d}, {0x7f, 0x7d}, >> + {0x80, 0x56}, {0x81, 0x00}, {0x7b, 0x00}, {0xc1, 0x01}, >> + {0xc2, 0x01}, {0x97, 0xf3}, {0xc9, 0x02}, {0xca, 0x02}, >> + {0xcb, 0x02}, {0xcc, 0x0a}, {0x9d, 0xe5}, {0x0f, 0x00}, >> + {0x0e, 0x02}, {0x0e, 0x00}, {0x63, 0x00}, {0x64, 0xaf}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x00}, {0x4a, 0x50}, {0x4a, 0x53}, {0x4b, 0x00}, >> + {0x4b, 0x00}, {0x0f, 0x01}, {0x0e, 0x04}, {0x0e, 0x05}, >> + {0x63, 0x00}, {0x64, 0xae}, {0x0f, 0x00}, {0x49, 0x07}, >> + {0x0f, 0x01}, {0x49, 0x07}, {0x0f, 0x02}, {0x49, 0x07}, >> + {0x0f, 0x03}, {0x49, 0x07}, {0x0f, 0x01}, {0x4a, 0x73}, >> + {0x4a, 0x72}, {0x4b, 0x20}, {0x4b, 0x20}, {0x0f, 0x02}, >> + {0x0e, 0x09}, {0x0e, 0x0a}, {0x63, 0x00}, {0x64, 0xae}, >> + {0x0f, 0x00}, {0x49, 0x07}, {0x0f, 0x01}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x49, 0x07}, {0x0f, 0x03}, {0x49, 0x07}, >> + {0x0f, 0x02}, {0x4a, 0xc2}, {0x4a, 0xc0}, {0x4b, 0x20}, >> + {0x4b, 0x20}, {0xcd, 0x21}, {0xcd, 0x21}, {0x00, 0x00}, >> + {0x00, 0x01}, {0x00, 0x00}, {0x01, 0x04}, {0x01, 0x05}, >> + {0xe9, 0x00}, {0x0d, 0x1e}, {0x3a, 0x40}, {0x01, 0x01}, >> + {0x01, 0x00}, {0xe9, 0x40}, {0x0a, 0x41}, {0x0f, 0X00}, >> + {0x0b, 0x00}, {0x0b, 0x00}, {0x62, 0x00}, {0x0f, 0x00}, >> + {0xe3, 0x02}, {0xe3, 0x02}, {0x26, 0x27}, {0x26, 0x00}, >> + {0x26, 0x62}, {0x26, 0x00}, {0x0f, 0x00}, {0x0f, 0x01}, >> + {0x0f, 0x02}, {0x0f, 0x00}, > > I'm not in for doing this sort of initialization. Sorry. > > Thanks > Kishon ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 4/5] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp 2014-08-13 15:34 ` Gabriel FERNANDEZ (?) @ 2014-08-13 15:34 ` Gabriel FERNANDEZ -1 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih407-b2120.dts | 11 +++++++ arch/arm/boot/dts/stih407.dtsi | 65 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index fe69f92..d0837fb 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -74,5 +74,16 @@ st,i2c-min-scl-pulse-width-us = <0>; st,i2c-min-sda-pulse-width-us = <5>; }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index d2f1aaa..5ad8b33 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -275,5 +275,70 @@ status = "disabled"; }; + + miphy28lp_phy: miphy28lp@9b22000 { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>, + <0x114 0x4>, /* sysctrl MiPHY cntrl */ + <0x818 0x4>, /* sysctrl MiPHY status*/ + <0xe0 0x4>, /* sysctrl PCIe */ + <0xec 0x4>; /* sysctrl SATA */ + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>, + <0x118 0x4>, + <0x81c 0x4>, + <0xe4 0x4>, + <0xf0 0x4>; + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>, + <0x11c 0x4>, + <0x820 0x4>; + reg-names = "pipew", + "usb3-up", + "miphy-ctrl-glue", + "miphy-status-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; }; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 4/5] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih407-b2120.dts | 11 +++++++ arch/arm/boot/dts/stih407.dtsi | 65 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index fe69f92..d0837fb 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -74,5 +74,16 @@ st,i2c-min-scl-pulse-width-us = <0>; st,i2c-min-sda-pulse-width-us = <5>; }; + + miphy28lp_phy: miphy28lp at 9b22000 { + + phy_port0: port at 9b22000 { + st,osc-rdy; + }; + + phy_port1: port at 9b2a000 { + st,osc-force-ext; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index d2f1aaa..5ad8b33 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -275,5 +275,70 @@ status = "disabled"; }; + + miphy28lp_phy: miphy28lp at 9b22000 { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port at 9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>, + <0x114 0x4>, /* sysctrl MiPHY cntrl */ + <0x818 0x4>, /* sysctrl MiPHY status*/ + <0xe0 0x4>, /* sysctrl PCIe */ + <0xec 0x4>; /* sysctrl SATA */ + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port at 9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>, + <0x118 0x4>, + <0x81c 0x4>, + <0xe4 0x4>, + <0xf0 0x4>; + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port at 8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>, + <0x11c 0x4>, + <0x820 0x4>; + reg-names = "pipew", + "usb3-up", + "miphy-ctrl-glue", + "miphy-status-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; }; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 4/5] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, Gabriel Fernandez, linux-kernel, linux-arm-kernel, kernel The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/boot/dts/stih407-b2120.dts | 11 +++++++ arch/arm/boot/dts/stih407.dtsi | 65 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index fe69f92..d0837fb 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -74,5 +74,16 @@ st,i2c-min-scl-pulse-width-us = <0>; st,i2c-min-sda-pulse-width-us = <5>; }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index d2f1aaa..5ad8b33 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -275,5 +275,70 @@ status = "disabled"; }; + + miphy28lp_phy: miphy28lp@9b22000 { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>, + <0x114 0x4>, /* sysctrl MiPHY cntrl */ + <0x818 0x4>, /* sysctrl MiPHY status*/ + <0xe0 0x4>, /* sysctrl PCIe */ + <0xec 0x4>; /* sysctrl SATA */ + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>, + <0x118 0x4>, + <0x81c 0x4>, + <0xe4 0x4>, + <0xf0 0x4>; + reg-names = "sata-up", + "pcie-up", + "pipew", + "miphy-ctrl-glue", + "miphy-status-glue", + "pcie-glue", + "sata-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>, + <0x11c 0x4>, + <0x820 0x4>; + reg-names = "pipew", + "usb3-up", + "miphy-ctrl-glue", + "miphy-status-glue"; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; }; }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 5/5] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5fb95fb..641e367 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -386,6 +386,7 @@ CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_SUN4I_USB=y CONFIG_EXT4_FS=y -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 5/5] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5fb95fb..641e367 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -386,6 +386,7 @@ CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_SUN4I_USB=y CONFIG_EXT4_FS=y -- 1.9.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 5/5] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY @ 2014-08-13 15:34 ` Gabriel FERNANDEZ 0 siblings, 0 replies; 39+ messages in thread From: Gabriel FERNANDEZ @ 2014-08-13 15:34 UTC (permalink / raw) To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard, Russell King, Kishon Vijay Abraham I, Grant Likely Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-F5mvAk5X5gdBDgjK7y7TUQ, Gabriel Fernandez Signed-off-by: Gabriel Fernandez <gabriel.fernandez-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5fb95fb..641e367 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -386,6 +386,7 @@ CONFIG_PWM_TEGRA=y CONFIG_PWM_VT8500=y CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_SUN4I_USB=y CONFIG_EXT4_FS=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 39+ messages in thread
end of thread, other threads:[~2014-08-21 7:12 UTC | newest] Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-08-13 15:34 [PATCH 0/5] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` [PATCH 1/5] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-20 14:56 ` Kishon Vijay Abraham I 2014-08-20 14:56 ` Kishon Vijay Abraham I 2014-08-20 14:56 ` Kishon Vijay Abraham I 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-13 15:34 ` [PATCH 2/5] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-20 14:53 ` Kishon Vijay Abraham I 2014-08-20 14:53 ` Kishon Vijay Abraham I 2014-08-20 14:53 ` Kishon Vijay Abraham I 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-13 15:34 ` [PATCH 3/5] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-14 12:15 ` Srinivas Kandagatla 2014-08-14 12:15 ` Srinivas Kandagatla 2014-08-14 12:37 ` Gabriel Fernandez 2014-08-14 12:37 ` Gabriel Fernandez 2014-08-14 12:37 ` Gabriel Fernandez 2014-08-20 14:58 ` Kishon Vijay Abraham I 2014-08-20 14:58 ` Kishon Vijay Abraham I 2014-08-20 14:58 ` Kishon Vijay Abraham I 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-21 7:12 ` Gabriel Fernandez 2014-08-13 15:34 ` [PATCH 4/5] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` [PATCH 5/5] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ 2014-08-13 15:34 ` Gabriel FERNANDEZ
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.