From: Daniel Lezcano <daniel.lezcano@linaro.org> To: "Shilimkar, Santosh" <santosh.shilimkar@ti.com>, "Menon, Nishanth" <nm@ti.com>, Tony Lindgren <tony@atomide.com>, "Kristo, Tero" <t-kristo@ti.com>, Paul Walmsley <paul@pwsan.com> Cc: "Kevin Hilman" <khilman@deeprootsystems.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "J, KEERTHY" <j-keerthy@ti.com>, "Benoît Cousson" <bcousson@baylibre.com> Subject: Re: [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support Date: Wed, 17 Sep 2014 17:22:50 -0700 [thread overview] Message-ID: <541A25DA.8030101@linaro.org> (raw) In-Reply-To: <448912EABC71F84BBCADFD3C67C4BE52CAC748@DBDE04.ent.ti.com> On 09/17/2014 04:20 PM, Shilimkar, Santosh wrote: > Sorry for the format. Emailing from webmail. > ________________________________________ [ ... ] >> +static int omap_enter_idle_smp(struct cpuidle_device *dev, >> + struct cpuidle_driver *drv, >> + int index) >> +{ >> + struct idle_statedata *cx = state_ptr + index; >> + unsigned long flag; >> + >> + raw_spin_lock_irqsave(&mpu_lock, flag); > > Why do you need this spin_lock_irqsave ? Aren't the local irqs already > disabled ? > > [Santosh] Actually at one point of time before the idle consolidation the local > irq disable was inside the idle drivers. Now with that moved to core layer, > I think plain spin_lock/unlock() should work. ok. >> + cx->mpu_state_vote++; >> + if (cx->mpu_state_vote == num_online_cpus()) { >> + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); >> + omap_set_pwrdm_state(mpu_pd, cx->mpu_state); >> + } >> + raw_spin_unlock_irqrestore(&mpu_lock, flag); >> + >> + omap4_enter_lowpower(dev->cpu, cx->cpu_state); >> + >> + raw_spin_lock_irqsave(&mpu_lock, flag); >> + if (cx->mpu_state_vote == num_online_cpus()) >> + omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); >> + cx->mpu_state_vote--; >> + raw_spin_unlock_irqrestore(&mpu_lock, flag); > > I am not sure that will work. What happens if a cpu exits idle and then > re-enter idle immediately ? > > [Santosh] It works and that case is already taken care. CPU exist the idle and then votes > out for cluster state and if it reenters with the right targeted state, the cluster state would > be picked. It isn't possible to have one cpu disabling the coherency, while the other one is looking for a lock ? Or eg. cpu0 is on WFI then cpu1 is the last entering idle. While cpu1 is entering 'lowpower', cpu0 exits the wfi check the state vote and set the power domain on. In the meantime cpu1 disables the coherency and cpu0 decrease the vote and release the lock. Could be possible there is a very small racy window here ? > Could you try a long run of this little program: > > https://git.linaro.org/power/pm-qa.git/blob/HEAD:/cpuidle/cpuidle_killer.c > > [Santosh] I am sure there will not be any issue with the long run test case here. > Lets see if Nishant sees anything otherwise Ok. Make sure the cpu is effectively entering your C2 state with the sleep duration in the test program. -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
WARNING: multiple messages have this Message-ID (diff)
From: daniel.lezcano@linaro.org (Daniel Lezcano) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support Date: Wed, 17 Sep 2014 17:22:50 -0700 [thread overview] Message-ID: <541A25DA.8030101@linaro.org> (raw) In-Reply-To: <448912EABC71F84BBCADFD3C67C4BE52CAC748@DBDE04.ent.ti.com> On 09/17/2014 04:20 PM, Shilimkar, Santosh wrote: > Sorry for the format. Emailing from webmail. > ________________________________________ [ ... ] >> +static int omap_enter_idle_smp(struct cpuidle_device *dev, >> + struct cpuidle_driver *drv, >> + int index) >> +{ >> + struct idle_statedata *cx = state_ptr + index; >> + unsigned long flag; >> + >> + raw_spin_lock_irqsave(&mpu_lock, flag); > > Why do you need this spin_lock_irqsave ? Aren't the local irqs already > disabled ? > > [Santosh] Actually at one point of time before the idle consolidation the local > irq disable was inside the idle drivers. Now with that moved to core layer, > I think plain spin_lock/unlock() should work. ok. >> + cx->mpu_state_vote++; >> + if (cx->mpu_state_vote == num_online_cpus()) { >> + pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); >> + omap_set_pwrdm_state(mpu_pd, cx->mpu_state); >> + } >> + raw_spin_unlock_irqrestore(&mpu_lock, flag); >> + >> + omap4_enter_lowpower(dev->cpu, cx->cpu_state); >> + >> + raw_spin_lock_irqsave(&mpu_lock, flag); >> + if (cx->mpu_state_vote == num_online_cpus()) >> + omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); >> + cx->mpu_state_vote--; >> + raw_spin_unlock_irqrestore(&mpu_lock, flag); > > I am not sure that will work. What happens if a cpu exits idle and then > re-enter idle immediately ? > > [Santosh] It works and that case is already taken care. CPU exist the idle and then votes > out for cluster state and if it reenters with the right targeted state, the cluster state would > be picked. It isn't possible to have one cpu disabling the coherency, while the other one is looking for a lock ? Or eg. cpu0 is on WFI then cpu1 is the last entering idle. While cpu1 is entering 'lowpower', cpu0 exits the wfi check the state vote and set the power domain on. In the meantime cpu1 disables the coherency and cpu0 decrease the vote and release the lock. Could be possible there is a very small racy window here ? > Could you try a long run of this little program: > > https://git.linaro.org/power/pm-qa.git/blob/HEAD:/cpuidle/cpuidle_killer.c > > [Santosh] I am sure there will not be any issue with the long run test case here. > Lets see if Nishant sees anything otherwise Ok. Make sure the cpu is effectively entering your C2 state with the sleep duration in the test program. -- <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
next prev parent reply other threads:[~2014-09-18 0:22 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-08-22 14:02 [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 01/10] ARM: OMAP5 / DRA7: PM: Update CPU context register offset Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 02/10] ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-27 18:44 ` Kevin Hilman 2014-08-27 18:44 ` Kevin Hilman 2014-08-22 14:02 ` [PATCH 03/10] ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 04/10] ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 05/10] ARM: OMAP5 / DRA7: PM: Avoid all SAR saves Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 06/10] ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 07/10] ARM: OMAP5 / DRA7: Enable CPU RET on suspend Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-27 18:58 ` Kevin Hilman 2014-08-27 18:58 ` Kevin Hilman 2014-08-27 19:05 ` Nishanth Menon 2014-08-27 19:05 ` Nishanth Menon 2014-08-27 19:41 ` Tony Lindgren 2014-08-27 19:41 ` Tony Lindgren 2014-08-27 19:43 ` Santosh Shilimkar 2014-08-27 19:43 ` Santosh Shilimkar 2014-08-27 19:45 ` Nishanth Menon 2014-08-27 19:45 ` Nishanth Menon 2014-09-05 21:15 ` Nishanth Menon 2014-09-05 21:15 ` Nishanth Menon 2014-09-05 21:30 ` Tony Lindgren 2014-09-05 21:30 ` Tony Lindgren 2014-09-08 17:23 ` Grazvydas Ignotas 2014-09-08 17:23 ` Grazvydas Ignotas 2014-09-08 18:34 ` Nishanth Menon 2014-09-08 18:34 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-27 19:13 ` Kevin Hilman 2014-08-27 19:13 ` Kevin Hilman 2014-08-27 19:35 ` Nishanth Menon 2014-08-27 19:35 ` Nishanth Menon 2014-08-27 19:41 ` Santosh Shilimkar 2014-08-27 19:41 ` Santosh Shilimkar 2014-08-27 20:22 ` Kevin Hilman 2014-08-27 20:22 ` Kevin Hilman 2014-09-05 21:18 ` Nishanth Menon 2014-09-05 21:18 ` Nishanth Menon 2014-09-05 21:18 ` Nishanth Menon 2014-09-16 16:34 ` Nishanth Menon 2014-09-16 16:34 ` Nishanth Menon 2014-09-16 16:34 ` Nishanth Menon 2014-09-17 18:49 ` Daniel Lezcano 2014-09-17 18:49 ` Daniel Lezcano 2014-09-17 18:49 ` Daniel Lezcano 2014-09-17 23:20 ` Shilimkar, Santosh 2014-09-17 23:20 ` Shilimkar, Santosh 2014-09-17 23:20 ` Shilimkar, Santosh 2014-09-18 0:22 ` Daniel Lezcano [this message] 2014-09-18 0:22 ` Daniel Lezcano 2014-09-18 0:42 ` Shilimkar, Santosh 2014-09-18 0:42 ` Shilimkar, Santosh 2014-09-18 0:42 ` Shilimkar, Santosh 2014-09-18 13:41 ` Nishanth Menon 2014-09-18 13:41 ` Nishanth Menon 2014-09-18 13:50 ` Nishanth Menon 2014-09-18 13:50 ` Nishanth Menon 2014-09-22 13:02 ` Nishanth Menon 2014-09-22 13:02 ` Nishanth Menon 2014-09-22 13:17 ` Nishanth Menon 2014-09-22 13:17 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 09/10] ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` [PATCH 10/10] ARM: DRA7: " Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-22 14:02 ` Nishanth Menon 2014-08-25 16:36 ` [PATCH 00/10] ARM: OMAP5 / DRA7: Add framework for suspend and cpuidle Nishanth Menon 2014-08-25 16:36 ` Nishanth Menon 2014-08-27 19:15 ` Kevin Hilman 2014-08-27 19:15 ` Kevin Hilman 2014-09-08 16:29 ` Nishanth Menon 2014-09-08 16:29 ` Nishanth Menon
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