[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas Manocha]

This patchset adds support to get controller sram size from device tree
& fix to support different FIFO widths.

Vikas Manocha (3):
  spi: cadence_qspi: move the sram partition in init
  spi: cadence_qspi: get sram size from device tree
  spi: cadence_qspi: support FIFO width other than 4 bytes

 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |   63 +++++++++++++++++-----------------------
 5 files changed, 31 insertions(+), 36 deletions(-)

-- 
1.7.9.5

[U-Boot] [PATCH 1/3] spi: cadence_qspi: move the sram partition in init

[Vikas Manocha]

There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |   16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 855e5c7..1924f3b 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -38,10 +38,7 @@
 
 /* Controller sram size in word */
 #define CQSPI_REG_SRAM_SIZE_WORD		(128)
-#define CQSPI_REG_SRAM_RESV_WORDS		(2)
-#define CQSPI_REG_SRAM_PARTITION_WR		(1)
-#define CQSPI_REG_SRAM_PARTITION_RD		\
-	(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
+#define CQSPI_REG_SRAM_PARTITION_RD		(CQSPI_REG_SRAM_SIZE_WORD/2)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
 
 /* Transfer mode */
@@ -537,6 +534,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 	/* Configure the remap address register, no remap */
 	writel(0, plat->regbase + CQSPI_REG_REMAP);
 
+	/* Indirect mode configurations */
+	writel(CQSPI_REG_SRAM_PARTITION_RD,
+		plat->regbase + CQSPI_REG_SRAMPARTITION);
+
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 
@@ -698,10 +699,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 	/* Setup the indirect trigger address */
 	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-	/* Configure SRAM partition for read. */
-	writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
-	       CQSPI_REG_SRAMPARTITION);
-
 	/* Configure the opcode */
 	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
@@ -798,9 +795,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 	/* Setup the indirect trigger address */
 	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-	writel(CQSPI_REG_SRAM_PARTITION_WR,
-	       plat->regbase + CQSPI_REG_SRAMPARTITION);
-
 	/* Configure the opcode */
 	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
-- 
1.7.9.5

[U-Boot] [PATCH 2/3] spi: cadence_qspi: get sram size from device tree

[Vikas Manocha]

sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |    6 +-----
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index bf791c5..9b12420 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,7 @@
 			ext-decoder = <0>;  /* external decoder */
 			num-cs = <4>;
 			fifo-depth = <128>;
+			sram-size = <128>;
 			bus-num = <2>;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index 3b1efca..556df82 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -35,6 +35,7 @@
 			ext-decoder = <0>; /* external decoder */
 			num-cs = <4>;
 			fifo-depth = <256>;
+			sram-size = <256>;
 			bus-num = <0>;
 			status = "okay";
 
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a75fc46..34a0f46 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
 	plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
 	plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+	plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
 	debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 	      __func__, plat->regbase, plat->ahbbase, plat->max_hz,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index c9a6142..98e57aa 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -25,6 +25,7 @@ struct cadence_spi_platdata {
 	u32		tsd2d_ns;
 	u32		tchsh_ns;
 	u32		tslch_ns;
+	u32		sram_size;
 };
 
 struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 1924f3b..5831905 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -36,9 +36,6 @@
 
 #define CQSPI_FIFO_WIDTH			(4)
 
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD		(128)
-#define CQSPI_REG_SRAM_PARTITION_RD		(CQSPI_REG_SRAM_SIZE_WORD/2)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
 
 /* Transfer mode */
@@ -535,8 +532,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 	writel(0, plat->regbase + CQSPI_REG_REMAP);
 
 	/* Indirect mode configurations */
-	writel(CQSPI_REG_SRAM_PARTITION_RD,
-		plat->regbase + CQSPI_REG_SRAMPARTITION);
+	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
-- 
1.7.9.5

[U-Boot] [PATCH 3/3] spi: cadence_qspi: support FIFO width other than 4 bytes

[Vikas Manocha]

This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |   47 ++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 5831905..a168912 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -199,18 +199,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 	unsigned int *dest_ptr = (unsigned int *)dest;
 	unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 
-	while (remaining > 0) {
-		if (remaining >= CQSPI_FIFO_WIDTH) {
-			*dest_ptr = readl(src_ptr);
-			remaining -= CQSPI_FIFO_WIDTH;
-		} else {
-			/* dangling bytes */
-			temp = readl(src_ptr);
-			memcpy(dest_ptr, &temp, remaining);
-			break;
-		}
+	while (remaining >= sizeof(dest_ptr)) {
+		*dest_ptr = readl(src_ptr);
+		remaining -= sizeof(src_ptr);
 		dest_ptr++;
 	}
+	if (remaining) {
+		/* dangling bytes */
+		temp = readl(src_ptr);
+		memcpy(dest_ptr, &temp, remaining);
+	}
 
 	return;
 }
@@ -218,24 +216,27 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 	const void *src, unsigned int bytes)
 {
-	unsigned int temp;
+	unsigned int temp=0;
+	int i;
 	int remaining = bytes;
 	unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
 	unsigned int *src_ptr = (unsigned int *)src;
 
-	while (remaining > 0) {
-		if (remaining >= CQSPI_FIFO_WIDTH) {
-			writel(*src_ptr, dest_ptr);
-			remaining -= sizeof(unsigned int);
-		} else {
-			/* dangling bytes */
-			memcpy(&temp, src_ptr, remaining);
-			writel(temp, dest_ptr);
-			break;
-		}
-		src_ptr++;
+	while (remaining >= CQSPI_FIFO_WIDTH) {
+		for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
+			writel(*(src_ptr+i), dest_ptr+i);
+		src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
+		remaining -= CQSPI_FIFO_WIDTH;
+	}
+	if (remaining)
+	{
+		/* dangling bytes */
+		i = remaining/sizeof(dest_ptr);
+		memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
+		writel(temp, dest_ptr+i);
+		for (--i; i >= 0; i--)
+			writel(*(src_ptr+i), dest_ptr+i);
 	}
-
 	return;
 }
 
-- 
1.7.9.5

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas MANOCHA]

Hi Stephen,
Any comments on the patchset.
Rgds,
Vikas

> -----Original Message-----
> From: Vikas MANOCHA
> Sent: Tuesday, June 09, 2015 6:25 PM
> To: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com;
> dinguyen at opensource.altera.com
> Cc: Vikas MANOCHA
> Subject: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO
> width
> 
> This patchset adds support to get controller sram size from device tree & fix
> to support different FIFO widths.
> 
> Vikas Manocha (3):
>   spi: cadence_qspi: move the sram partition in init
>   spi: cadence_qspi: get sram size from device tree
>   spi: cadence_qspi: support FIFO width other than 4 bytes
> 
>  arch/arm/dts/socfpga.dtsi      |    1 +
>  arch/arm/dts/stv0991.dts       |    1 +
>  drivers/spi/cadence_qspi.c     |    1 +
>  drivers/spi/cadence_qspi.h     |    1 +
>  drivers/spi/cadence_qspi_apb.c |   63 +++++++++++++++++-------------------
> ----
>  5 files changed, 31 insertions(+), 36 deletions(-)
> 
> --
> 1.7.9.5

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Stefan Roese]

Hi Vikas,

On 11.06.2015 21:16, Vikas MANOCHA wrote:
> Any comments on the patchset.

I'll test them next week on a SoCFPGA based board and will comment then 
again.

Thanks,
Stefan

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas MANOCHA]

Hi Stefan,

> -----Original Message-----
> From: Stefan Roese [mailto:sr at denx.de]
> Sent: Friday, June 12, 2015 5:10 AM
> To: Vikas MANOCHA; u-boot at lists.denx.de;
> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for
> FIFO width
> 
> Hi Vikas,
> 
> On 11.06.2015 21:16, Vikas MANOCHA wrote:
> > Any comments on the patchset.
> 
> I'll test them next week on a SoCFPGA based board and will comment then
> again.

Can you please test this patchset also.

Rgds,
Vikas

> 
> Thanks,
> Stefan

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Stefan Roese]

Hi Vikas,

On 23.06.2015 16:48, Vikas MANOCHA wrote:
>> -----Original Message-----
>> From: Stefan Roese [mailto:sr at denx.de]
>> Sent: Friday, June 12, 2015 5:10 AM
>> To: Vikas MANOCHA; u-boot at lists.denx.de;
>> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
>> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for
>> FIFO width
>>
>> Hi Vikas,
>>
>> On 11.06.2015 21:16, Vikas MANOCHA wrote:
>>> Any comments on the patchset.
>>
>> I'll test them next week on a SoCFPGA based board and will comment then
>> again.
>
> Can you please test this patchset also.

Okay. I've now tested this 3 patch series as well on top of mainline. 
And SPI NOR seems to work just fine with this one applied. Not errors 
and the write/read/compare test also works okay.

HTP.

Thanks,
Stefan

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas MANOCHA]

Thanks Stefan,
Adding Jagan to apply the patchset.
Rgds,
Vikas

> -----Original Message-----
> From: Stefan Roese [mailto:sr at denx.de]
> Sent: Wednesday, June 24, 2015 3:09 AM
> To: Vikas MANOCHA
> Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com;
> dinguyen at opensource.altera.com
> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for
> FIFO width
> 
> Hi Vikas,
> 
> On 23.06.2015 16:48, Vikas MANOCHA wrote:
> >> -----Original Message-----
> >> From: Stefan Roese [mailto:sr at denx.de]
> >> Sent: Friday, June 12, 2015 5:10 AM
> >> To: Vikas MANOCHA; u-boot at lists.denx.de;
> >> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix
> >> for FIFO width
> >>
> >> Hi Vikas,
> >>
> >> On 11.06.2015 21:16, Vikas MANOCHA wrote:
> >>> Any comments on the patchset.
> >>
> >> I'll test them next week on a SoCFPGA based board and will comment
> >> then again.
> >
> > Can you please test this patchset also.
> 
> Okay. I've now tested this 3 patch series as well on top of mainline.
> And SPI NOR seems to work just fine with this one applied. Not errors and
> the write/read/compare test also works okay.
> 
> HTP.
> 
> Thanks,
> Stefan

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Jagan Teki]

On 24 June 2015 at 23:43, Vikas MANOCHA <vikas.manocha@st.com> wrote:
> Thanks Stefan,
> Adding Jagan to apply the patchset.

I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check
it those and resend.
Anyway I will apply these on master-next for next releases, is that fine?

>
>> -----Original Message-----
>> From: Stefan Roese [mailto:sr at denx.de]
>> Sent: Wednesday, June 24, 2015 3:09 AM
>> To: Vikas MANOCHA
>> Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com;
>> dinguyen at opensource.altera.com
>> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for
>> FIFO width
>>
>> Hi Vikas,
>>
>> On 23.06.2015 16:48, Vikas MANOCHA wrote:
>> >> -----Original Message-----
>> >> From: Stefan Roese [mailto:sr at denx.de]
>> >> Sent: Friday, June 12, 2015 5:10 AM
>> >> To: Vikas MANOCHA; u-boot at lists.denx.de;
>> >> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
>> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix
>> >> for FIFO width
>> >>
>> >> Hi Vikas,
>> >>
>> >> On 11.06.2015 21:16, Vikas MANOCHA wrote:
>> >>> Any comments on the patchset.
>> >>
>> >> I'll test them next week on a SoCFPGA based board and will comment
>> >> then again.
>> >
>> > Can you please test this patchset also.
>>
>> Okay. I've now tested this 3 patch series as well on top of mainline.
>> And SPI NOR seems to work just fine with this one applied. Not errors and
>> the write/read/compare test also works okay.

thanks!
-- 
Jagan | openedev.

[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas MANOCHA]

Thanks Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Wednesday, June 24, 2015 11:54 AM
> To: Vikas MANOCHA
> Cc: Stefan Roese; u-boot at lists.denx.de; grmoore at opensource.altera.com
> Subject: Re: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT &
> fix for FIFO width
> 
> On 24 June 2015 at 23:43, Vikas MANOCHA <vikas.manocha@st.com> wrote:
> > Thanks Stefan,
> > Adding Jagan to apply the patchset.
> 
> I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check it
> those and resend.

Yes for Patch3, I will fix it & send the v2. 
Patch1 has one check info (Alignment should match open parenthesis)  I think it should be ignored..

Rgds,
Vikas

> Anyway I will apply these on master-next for next releases, is that fine?
> 
> >
> >> -----Original Message-----
> >> From: Stefan Roese [mailto:sr at denx.de]
> >> Sent: Wednesday, June 24, 2015 3:09 AM
> >> To: Vikas MANOCHA
> >> Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com;
> >> dinguyen at opensource.altera.com
> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix
> >> for FIFO width
> >>
> >> Hi Vikas,
> >>
> >> On 23.06.2015 16:48, Vikas MANOCHA wrote:
> >> >> -----Original Message-----
> >> >> From: Stefan Roese [mailto:sr at denx.de]
> >> >> Sent: Friday, June 12, 2015 5:10 AM
> >> >> To: Vikas MANOCHA; u-boot at lists.denx.de;
> >> >> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
> >> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT &
> >> >> fix for FIFO width
> >> >>
> >> >> Hi Vikas,
> >> >>
> >> >> On 11.06.2015 21:16, Vikas MANOCHA wrote:
> >> >>> Any comments on the patchset.
> >> >>
> >> >> I'll test them next week on a SoCFPGA based board and will comment
> >> >> then again.
> >> >
> >> > Can you please test this patchset also.
> >>
> >> Okay. I've now tested this 3 patch series as well on top of mainline.
> >> And SPI NOR seems to work just fine with this one applied. Not errors
> >> and the write/read/compare test also works okay.
> 
> thanks!
> --
> Jagan | openedev.