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From: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
To: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>,
	Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
	Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
	Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
	Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
	Roland Stigge <stigge-uj/7R2tJ6VmzQB+pC5nmwQ@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
Date: Fri, 20 Nov 2015 18:02:09 +0000	[thread overview]
Message-ID: <564F6021.7090000@arm.com> (raw)
In-Reply-To: <564F5DF8.7040908-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>

On 20/11/15 17:52, Vladimir Zapolskiy wrote:
> Hi Rob,
> 
> On 20.11.2015 18:58, Rob Herring wrote:
>> On Fri, Nov 20, 2015 at 03:28:38AM +0200, Vladimir Zapolskiy wrote:
>>> NXP LPC32xx has three interrupt controllers, namely root Main
>>> Interrupt Controller (MIC) and two supplementary Sub Interrupt
>>> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
>>> are connected to MIC.
>>>
>>> Also the change describes two additional optional properties:
>>> * interrupt-controller-name - human readable name of an interrupt
>>>   controller,
>>
>> Why? compatible is human readable. If you don't like that, then put the 
>> string in the driver.
> 
> in runtime I'd like to differentiate various IRQ chips by name. Here for
> example I have one compatible "*-sic" and two actual IRQ chips SIC1 and
> SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping
> I would prefer to visualize interrupts from SIC1 and SIC2.
> 
> I understand that this property is not hardware specific, but there are
> plenty of similar properties like "label" etc. Probably renaming of the
> property may help?

You can always generate the name based on the probing order or the address.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
Date: Fri, 20 Nov 2015 18:02:09 +0000	[thread overview]
Message-ID: <564F6021.7090000@arm.com> (raw)
In-Reply-To: <564F5DF8.7040908@mleia.com>

On 20/11/15 17:52, Vladimir Zapolskiy wrote:
> Hi Rob,
> 
> On 20.11.2015 18:58, Rob Herring wrote:
>> On Fri, Nov 20, 2015 at 03:28:38AM +0200, Vladimir Zapolskiy wrote:
>>> NXP LPC32xx has three interrupt controllers, namely root Main
>>> Interrupt Controller (MIC) and two supplementary Sub Interrupt
>>> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
>>> are connected to MIC.
>>>
>>> Also the change describes two additional optional properties:
>>> * interrupt-controller-name - human readable name of an interrupt
>>>   controller,
>>
>> Why? compatible is human readable. If you don't like that, then put the 
>> string in the driver.
> 
> in runtime I'd like to differentiate various IRQ chips by name. Here for
> example I have one compatible "*-sic" and two actual IRQ chips SIC1 and
> SIC2. If I read /proc/interrupts or /sys/kernel/debug/irq_domain_mapping
> I would prefer to visualize interrupts from SIC1 and SIC2.
> 
> I understand that this property is not hardware specific, but there are
> plenty of similar properties like "label" etc. Probably renaming of the
> property may help?

You can always generate the name based on the probing order or the address.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  parent reply	other threads:[~2015-11-20 18:02 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-20  1:28 [PATCH 00/10] irqchip: lpc32xx: add LPC32xx irqchip driver Vladimir Zapolskiy
2015-11-20  1:28 ` Vladimir Zapolskiy
     [not found] ` <1447982925-30138-1-git-send-email-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20  1:28   ` [PATCH 01/10] dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
     [not found]     ` <1447982925-30138-2-git-send-email-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20 16:43       ` Rob Herring
2015-11-20 16:43         ` Rob Herring
2015-11-20  1:28   ` [PATCH 02/10] dt-bindings: nxp: add description of wakeup controller on LPC32xx Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
     [not found]     ` <1447982925-30138-3-git-send-email-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20 16:55       ` Rob Herring
2015-11-20 16:55         ` Rob Herring
2015-11-20  1:28   ` [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2 Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
     [not found]     ` <1447982925-30138-4-git-send-email-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20 16:58       ` Rob Herring
2015-11-20 16:58         ` Rob Herring
2015-11-20 17:52         ` Vladimir Zapolskiy
2015-11-20 17:52           ` Vladimir Zapolskiy
     [not found]           ` <564F5DF8.7040908-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20 18:02             ` Marc Zyngier [this message]
2015-11-20 18:02               ` Marc Zyngier
     [not found]               ` <564F6021.7090000-5wv7dgnIgG8@public.gmane.org>
2015-11-20 18:16                 ` Vladimir Zapolskiy
2015-11-20 18:16                   ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 04/10] arm: lpc32xx: add wakeup platform driver Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 05/10] arm: dts: lpc32xx: assign interrupt types Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 06/10] arm: dts: lpc32xx: add description of IC wakeup controllers Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 07/10] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 08/10] irqchip: add LPC32xx interrupt controller driver Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
     [not found]     ` <1447982925-30138-9-git-send-email-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
2015-11-20 10:56       ` Marc Zyngier
2015-11-20 10:56         ` Marc Zyngier
2015-11-20  1:28   ` [PATCH 09/10] irqchip: lpc32xx: add option to wakeup from an interrupt Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2015-11-20  1:28   ` [PATCH 10/10] arm: dts: lpc32xx: enable SIC1 and SIC2 by default Vladimir Zapolskiy
2015-11-20  1:28     ` Vladimir Zapolskiy
2016-02-10 19:45 ` [PATCH 00/10] irqchip: lpc32xx: add LPC32xx irqchip driver Sylvain Lemieux
     [not found]   ` <loom.20160210T204046-649-eS7Uydv5nfjZ+VzJOa5vwg@public.gmane.org>
2016-04-04 17:37     ` Sylvain Lemieux
2016-04-04 17:37       ` Sylvain Lemieux
2016-04-05  1:24       ` Vladimir Zapolskiy
2016-04-05  1:24         ` Vladimir Zapolskiy

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