[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, or completes the existing
nodes, and links the CPU nodes to them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Changes compared to v2:
  - Dropped "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
    r8a7795: Add L2 cache-controller nodes",
  - Changed one-line summary prefix to match current arm-soc practices.

This series is against renesas-devel-20160215-v4.5-rc4.
It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
r8a7795/salvator-x.

For your convenience, I've also pushed this series to
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3

Thanks for applying!

Geert Uytterhoeven (7):
  ARM: dts: r8a73a4: Add L2 cache-controller nodes
  ARM: dts: r8a7790: Add L2 cache-controller nodes
  ARM: dts: r8a7791: Add L2 cache-controller node
  ARM: dts: r8a7793: Add L2 cache-controller node
  ARM: dts: r8a7794: Add L2 cache-controller node
  arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
  arm64: dts: r8a7795: Add CA53 L2 cache-controller node

 arch/arm/boot/dts/r8a73a4.dtsi           | 17 +++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 20 ++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           |  8 ++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  7 +++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi |  8 ++++++++
 6 files changed, 68 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, or completes the existing
nodes, and links the CPU nodes to them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Changes compared to v2:
  - Dropped "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
    r8a7795: Add L2 cache-controller nodes",
  - Changed one-line summary prefix to match current arm-soc practices.

This series is against renesas-devel-20160215-v4.5-rc4.
It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
r8a7795/salvator-x.

For your convenience, I've also pushed this series to
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3

Thanks for applying!

Geert Uytterhoeven (7):
  ARM: dts: r8a73a4: Add L2 cache-controller nodes
  ARM: dts: r8a7790: Add L2 cache-controller nodes
  ARM: dts: r8a7791: Add L2 cache-controller node
  ARM: dts: r8a7793: Add L2 cache-controller node
  ARM: dts: r8a7794: Add L2 cache-controller node
  arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
  arm64: dts: r8a7795: Add CA53 L2 cache-controller node

 arch/arm/boot/dts/r8a73a4.dtsi           | 17 +++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 20 ++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           |  8 ++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  7 +++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi |  8 ++++++++
 6 files changed, 68 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[Geert Uytterhoeven]

	Hi Simon, Magnus,

This patch series adds the missing L2 cache-controller nodes to the
DTSes for various Renesas ARM-based SoCs, or completes the existing
nodes, and links the CPU nodes to them.

For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
the respective (already existing) SYSC Power Domains. Fortunately these
Power Domains were never powered down, as they are parents of the Power
Domains containing CPU cores. This may change in the future.

For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
adding SYSC Power Domain support later.

Changes compared to v2:
  - Dropped "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
    r8a7795: Add L2 cache-controller nodes",
  - Changed one-line summary prefix to match current arm-soc practices.

This series is against renesas-devel-20160215-v4.5-rc4.
It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
r8a7795/salvator-x.

For your convenience, I've also pushed this series to
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3

Thanks for applying!

Geert Uytterhoeven (7):
  ARM: dts: r8a73a4: Add L2 cache-controller nodes
  ARM: dts: r8a7790: Add L2 cache-controller nodes
  ARM: dts: r8a7791: Add L2 cache-controller node
  ARM: dts: r8a7793: Add L2 cache-controller node
  ARM: dts: r8a7794: Add L2 cache-controller node
  arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
  arm64: dts: r8a7795: Add CA53 L2 cache-controller node

 arch/arm/boot/dts/r8a73a4.dtsi           | 17 +++++++++++++++++
 arch/arm/boot/dts/r8a7790.dtsi           | 20 ++++++++++++++++++++
 arch/arm/boot/dts/r8a7791.dtsi           |  8 ++++++++
 arch/arm/boot/dts/r8a7793.dtsi           |  7 +++++++
 arch/arm/boot/dts/r8a7794.dtsi           |  8 ++++++++
 arch/arm64/boot/dts/renesas/r8a7795.dtsi |  8 ++++++++
 6 files changed, 68 insertions(+)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v3 1/7] ARM: dts: r8a73a4: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 138414a7d1703781..6583a1dfca1f64c6 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,22 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller@e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v3 1/7] ARM: dts: r8a73a4: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 138414a7d1703781..6583a1dfca1f64c6 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,22 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller@e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

[PATCH v3 1/7] ARM: dts: r8a73a4: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - New.
---
 arch/arm/boot/dts/r8a73a4.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 138414a7d1703781..6583a1dfca1f64c6 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -45,6 +46,22 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	dbsc1: memory-controller at e6790000 {
 		compatible = "renesas,dbsc-r8a73a4";
 		reg = <0 0xe6790000 0 0x10000>;
-- 
1.9.1

[PATCH v3 2/7] ARM: dts: r8a7790: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 caches into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 76ddf5c6cca79c3c..e40aa6585831c520 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu@2 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu@3 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu@4 {
@@ -88,6 +92,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu@5 {
@@ -95,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu@6 {
@@ -102,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu@7 {
@@ -109,9 +116,22 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 2/7] ARM: dts: r8a7790: Add L2 cache-controller nodes

[Geert Uytterhoeven]

Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 caches into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 76ddf5c6cca79c3c..e40aa6585831c520 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu at 2 {
@@ -74,6 +76,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu at 3 {
@@ -81,6 +84,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu at 4 {
@@ -88,6 +92,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu at 5 {
@@ -95,6 +100,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu at 6 {
@@ -102,6 +108,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu at 7 {
@@ -109,9 +116,22 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 3/7] ARM: dts: r8a7791: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8910236e64bf93ed..a65910ed5884edfd 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +67,16 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 3/7] ARM: dts: r8a7791: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8910236e64bf93ed..a65910ed5884edfd 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +67,16 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 4/7] ARM: dts: r8a7793: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 45dba1c79a43c287..9a30f650aa515b80 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -51,9 +51,16 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

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[PATCH v3 4/7] ARM: dts: r8a7793: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 45dba1c79a43c287..9a30f650aa515b80 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -51,9 +51,16 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 4/7] ARM: dts: r8a7793: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Drop "arm,data-latency" and "arm,tag-latency" properties, as they
    may not be valid when using virtualization,
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPU to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 45dba1c79a43c287..9a30f650aa515b80 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -51,9 +51,16 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	L2_CA15: cache-controller at 0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 5/7] ARM: dts: r8a7794: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b81eb..21a02df3609b24aa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu@1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 5/7] ARM: dts: r8a7794: Add L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Change one-line summary prefix to match current arm-soc practices,

v2:
  - Drop (incorrect) optional cache-{size,sets,{block,line}-size}
    properties, as this information is auto-detected,
  - Integrate linking CPUs to L2 cache into this patch,
  - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
    SYSC PM Domain DT Support".
---
 arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b81eb..21a02df3609b24aa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu at 1 {
@@ -47,9 +48,16 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller at f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
-- 
1.9.1

[PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Geert Uytterhoeven]

Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
    cache-controller nodes", after dropping the "arm,data-latency" and
    "arm,tag-latency" properties.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index b5e46e4ff72ad003..c07f4e83b988ba42 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -68,6 +68,8 @@
 
 	L2_CA57: cache-controller@0 {
 		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
 	};
 
 	extal_clk: extal {
-- 
1.9.1

[PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Geert Uytterhoeven]

Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
    cache-controller nodes", after dropping the "arm,data-latency" and
    "arm,tag-latency" properties.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index b5e46e4ff72ad003..c07f4e83b988ba42 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -68,6 +68,8 @@
 
 	L2_CA57: cache-controller at 0 {
 		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
 	};
 
 	extal_clk: extal {
-- 
1.9.1

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
    cache-controller nodes".
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index c07f4e83b988ba42..c572527afec3403a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -72,6 +72,12 @@
 		cache-level = <2>;
 	};
 
+	L2_CA53: cache-controller@1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
1.9.1

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Geert Uytterhoeven]

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
    cache-controller nodes".
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index c07f4e83b988ba42..c572527afec3403a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -72,6 +72,12 @@
 		cache-level = <2>;
 	};
 
+	L2_CA53: cache-controller at 1 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
1.9.1

Re: [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add the missing "cache-unified" and "cache-level" properties to the
> Cortex-A57 cache-controller node.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes", after dropping the "arm,data-latency" and
>      "arm,tag-latency" properties.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -68,6 +68,8 @@
>
>   	L2_CA57: cache-controller@0 {
>   		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;


As this is completely unused on ARMv8 I don't think that we want to have 
these unused entries in the DT.

Sudeep: What do you think?

Best regards

Dirk

Re: [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add the missing "cache-unified" and "cache-level" properties to the
> Cortex-A57 cache-controller node.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes", after dropping the "arm,data-latency" and
>      "arm,tag-latency" properties.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -68,6 +68,8 @@
>
>   	L2_CA57: cache-controller@0 {
>   		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;


As this is completely unused on ARMv8 I don't think that we want to have 
these unused entries in the DT.

Sudeep: What do you think?

Best regards

Dirk

[PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add the missing "cache-unified" and "cache-level" properties to the
> Cortex-A57 cache-controller node.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes", after dropping the "arm,data-latency" and
>      "arm,tag-latency" properties.
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -68,6 +68,8 @@
>
>   	L2_CA57: cache-controller at 0 {
>   		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;


As this is completely unused on ARMv8 I don't think that we want to have 
these unused entries in the DT.

Sudeep: What do you think?

Best regards

Dirk

Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add a device node for the Cortex-A53 L2 cache-controller.
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes".
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index c07f4e83b988ba42..c572527afec3403a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -72,6 +72,12 @@
>   		cache-level = <2>;
>   	};
>
> +	L2_CA53: cache-controller@1 {
> +		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +


As we don't have any CA53 in the device tree yet, and it was rejected to 
add it, I'd think that we don't want these unused entries at the moment.

I'd propose to add the CA53 entries, first. And then add their L2 cache 
entries.

Based on the outcome of the discussion for the CA57 we have to see if we 
want to add the unused cache-unified and cache-level, then, too.

Best regards

Dirk


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Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add a device node for the Cortex-A53 L2 cache-controller.
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes".
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index c07f4e83b988ba42..c572527afec3403a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -72,6 +72,12 @@
>   		cache-level = <2>;
>   	};
>
> +	L2_CA53: cache-controller@1 {
> +		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +


As we don't have any CA53 in the device tree yet, and it was rejected to 
add it, I'd think that we don't want these unused entries at the moment.

I'd propose to add the CA53 entries, first. And then add their L2 cache 
entries.

Based on the outcome of the discussion for the CA57 we have to see if we 
want to add the unused cache-unified and cache-level, then, too.

Best regards

Dirk

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

On 15.02.2016 21:38, Geert Uytterhoeven wrote:
> Add a device node for the Cortex-A53 L2 cache-controller.
>
> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
> 32 KiB x 16 ways).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>      cache-controller nodes".
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index c07f4e83b988ba42..c572527afec3403a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -72,6 +72,12 @@
>   		cache-level = <2>;
>   	};
>
> +	L2_CA53: cache-controller at 1 {
> +		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;
> +	};
> +


As we don't have any CA53 in the device tree yet, and it was rejected to 
add it, I'd think that we don't want these unused entries at the moment.

I'd propose to add the CA53 entries, first. And then add their L2 cache 
entries.

Based on the outcome of the discussion for the CA57 we have to see if we 
want to add the unused cache-unified and cache-level, then, too.

Best regards

Dirk

Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Geert Uytterhoeven]

Hi Dirk,

On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>> Add a device node for the Cortex-A53 L2 cache-controller.
>>
>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>> 32 KiB x 16 ways).
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> v3:
>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>      cache-controller nodes".
>> ---
>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index c07f4e83b988ba42..c572527afec3403a 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -72,6 +72,12 @@
>>                 cache-level = <2>;
>>         };
>>
>> +       L2_CA53: cache-controller@1 {
>> +               compatible = "cache";
>> +               cache-unified;
>> +               cache-level = <2>;
>> +       };
>> +
>
> As we don't have any CA53 in the device tree yet, and it was rejected to add
> it, I'd think that we don't want these unused entries at the moment.

This is a preparatory step for adding the SYSC PM Domains.

> I'd propose to add the CA53 entries, first. And then add their L2 cache
> entries.
>
> Based on the outcome of the discussion for the CA57 we have to see if we
> want to add the unused cache-unified and cache-level, then, too.

These are specified by ePAPR, as I said before.
Remember, DT describes the hardware, not what Linux (or any other OS) is
using.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Geert Uytterhoeven]

Hi Dirk,

On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>> Add a device node for the Cortex-A53 L2 cache-controller.
>>
>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>> 32 KiB x 16 ways).
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> v3:
>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>      cache-controller nodes".
>> ---
>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index c07f4e83b988ba42..c572527afec3403a 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -72,6 +72,12 @@
>>                 cache-level = <2>;
>>         };
>>
>> +       L2_CA53: cache-controller at 1 {
>> +               compatible = "cache";
>> +               cache-unified;
>> +               cache-level = <2>;
>> +       };
>> +
>
> As we don't have any CA53 in the device tree yet, and it was rejected to add
> it, I'd think that we don't want these unused entries at the moment.

This is a preparatory step for adding the SYSC PM Domains.

> I'd propose to add the CA53 entries, first. And then add their L2 cache
> entries.
>
> Based on the outcome of the discussion for the CA57 we have to see if we
> want to add the unused cache-unified and cache-level, then, too.

These are specified by ePAPR, as I said before.
Remember, DT describes the hardware, not what Linux (or any other OS) is
using.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller@1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk

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Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller@1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Dirk Behme]

Hi Geert,

On 16.02.2016 08:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add a device node for the Cortex-A53 L2 cache-controller.
>>>
>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>>> 32 KiB x 16 ways).
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>     - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>       cache-controller nodes".
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
>>>    1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index c07f4e83b988ba42..c572527afec3403a 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -72,6 +72,12 @@
>>>                  cache-level = <2>;
>>>          };
>>>
>>> +       L2_CA53: cache-controller at 1 {
>>> +               compatible = "cache";
>>> +               cache-unified;
>>> +               cache-level = <2>;
>>> +       };
>>> +
>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.


Yes. But what do you want to control if it's not enabled at all?

To my understanding, as long as we don't enable the CA53 cores, we don't 
enable their L2 caches, too. And then we don't have to PM control them?


>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.


Yes, this is understood :)

Your argument is the Spec/ePAPR, my point of view is the practical 
implementation. I'd think both are valid. Therefore let's see what 
Sudeep thinks ;)


Best regards

Dirk

Re: [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Sudeep Holla]

On 16/02/16 06:40, Dirk Behme wrote:
> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>> Add the missing "cache-unified" and "cache-level" properties to the
>> Cortex-A57 cache-controller node.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> v3:
>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>      cache-controller nodes", after dropping the "arm,data-latency" and
>>      "arm,tag-latency" properties.
>> ---
>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -68,6 +68,8 @@
>>
>>       L2_CA57: cache-controller@0 {
>>           compatible = "cache";
>> +        cache-unified;
>> +        cache-level = <2>;
>
>
> As this is completely unused on ARMv8 I don't think that we want to have
> these unused entries in the DT.
>
> Sudeep: What do you think?
>

I am fine with that, I don't see any issue having them as they are
static values and highly unlikely to change and hence no threat to
backward compatibility.

The main concern I had with latency values is that it's currently not
used anywhere but if we decide to use say in secure software, having the
untested/early values in DT might cause compatibility issues in future
as they were added much before the actual understanding of it's usage.
So I prefer to defer them until then.

-- 
Regards,
Sudeep

[PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Sudeep Holla]

On 16/02/16 06:40, Dirk Behme wrote:
> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>> Add the missing "cache-unified" and "cache-level" properties to the
>> Cortex-A57 cache-controller node.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> v3:
>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>      cache-controller nodes", after dropping the "arm,data-latency" and
>>      "arm,tag-latency" properties.
>> ---
>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -68,6 +68,8 @@
>>
>>       L2_CA57: cache-controller at 0 {
>>           compatible = "cache";
>> +        cache-unified;
>> +        cache-level = <2>;
>
>
> As this is completely unused on ARMv8 I don't think that we want to have
> these unused entries in the DT.
>
> Sudeep: What do you think?
>

I am fine with that, I don't see any issue having them as they are
static values and highly unlikely to change and hence no threat to
backward compatibility.

The main concern I had with latency values is that it's currently not
used anywhere but if we decide to use say in secure software, having the
untested/early values in DT might cause compatibility issues in future
as they were added much before the actual understanding of it's usage.
So I prefer to defer them until then.

-- 
Regards,
Sudeep

Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Sudeep Holla]

On 16/02/16 07:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme-V5te9oGctAVWk0Htik3J/w@public.gmane.org> wrote:

[...]

>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.
>
>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.
>

I completely agree and I mentioned the same in the other email.

-- 
Regards,
Sudeep
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Re: [PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Sudeep Holla]

On 16/02/16 07:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:

[...]

>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.
>
>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.
>

I completely agree and I mentioned the same in the other email.

-- 
Regards,
Sudeep

[PATCH v3 7/7] arm64: dts: r8a7795: Add CA53 L2 cache-controller node

[Sudeep Holla]

On 16/02/16 07:12, Geert Uytterhoeven wrote:
> Hi Dirk,
>
> On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:

[...]

>>
>> As we don't have any CA53 in the device tree yet, and it was rejected to add
>> it, I'd think that we don't want these unused entries at the moment.
>
> This is a preparatory step for adding the SYSC PM Domains.
>
>> I'd propose to add the CA53 entries, first. And then add their L2 cache
>> entries.
>>
>> Based on the outcome of the discussion for the CA57 we have to see if we
>> want to add the unused cache-unified and cache-level, then, too.
>
> These are specified by ePAPR, as I said before.
> Remember, DT describes the hardware, not what Linux (or any other OS) is
> using.
>

I completely agree and I mentioned the same in the other email.

-- 
Regards,
Sudeep

Re: [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 16.02.2016 10:43, Sudeep Holla wrote:
>
>
> On 16/02/16 06:40, Dirk Behme wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add the missing "cache-unified" and "cache-level" properties to the
>>> Cortex-A57 cache-controller node.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>      cache-controller nodes", after dropping the "arm,data-latency" and
>>>      "arm,tag-latency" properties.
>>> ---
>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -68,6 +68,8 @@
>>>
>>>       L2_CA57: cache-controller@0 {
>>>           compatible = "cache";
>>> +        cache-unified;
>>> +        cache-level = <2>;
>>
>>
>> As this is completely unused on ARMv8 I don't think that we want to have
>> these unused entries in the DT.
>>
>> Sudeep: What do you think?
>>
>
> I am fine with that, I don't see any issue having them as they are
> static values and highly unlikely to change and hence no threat to
> backward compatibility.
>
> The main concern I had with latency values is that it's currently not
> used anywhere but if we decide to use say in secure software, having the
> untested/early values in DT might cause compatibility issues in future
> as they were added much before the actual understanding of it's usage.
> So I prefer to defer them until then.


Fine with me, thanks! :)

With this clarification:

Acked-by: Dirk Behme <dirk.behme@de.bosch.com>


Thanks again and best regards

Dirk

Re: [PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 16.02.2016 10:43, Sudeep Holla wrote:
>
>
> On 16/02/16 06:40, Dirk Behme wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add the missing "cache-unified" and "cache-level" properties to the
>>> Cortex-A57 cache-controller node.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>      cache-controller nodes", after dropping the "arm,data-latency" and
>>>      "arm,tag-latency" properties.
>>> ---
>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -68,6 +68,8 @@
>>>
>>>       L2_CA57: cache-controller@0 {
>>>           compatible = "cache";
>>> +        cache-unified;
>>> +        cache-level = <2>;
>>
>>
>> As this is completely unused on ARMv8 I don't think that we want to have
>> these unused entries in the DT.
>>
>> Sudeep: What do you think?
>>
>
> I am fine with that, I don't see any issue having them as they are
> static values and highly unlikely to change and hence no threat to
> backward compatibility.
>
> The main concern I had with latency values is that it's currently not
> used anywhere but if we decide to use say in secure software, having the
> untested/early values in DT might cause compatibility issues in future
> as they were added much before the actual understanding of it's usage.
> So I prefer to defer them until then.


Fine with me, thanks! :)

With this clarification:

Acked-by: Dirk Behme <dirk.behme@de.bosch.com>


Thanks again and best regards

Dirk

[PATCH v3 6/7] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

[Dirk Behme]

On 16.02.2016 10:43, Sudeep Holla wrote:
>
>
> On 16/02/16 06:40, Dirk Behme wrote:
>> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>>> Add the missing "cache-unified" and "cache-level" properties to the
>>> Cortex-A57 cache-controller node.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v3:
>>>    - Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
>>>      cache-controller nodes", after dropping the "arm,data-latency" and
>>>      "arm,tag-latency" properties.
>>> ---
>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index b5e46e4ff72ad003..c07f4e83b988ba42 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -68,6 +68,8 @@
>>>
>>>       L2_CA57: cache-controller at 0 {
>>>           compatible = "cache";
>>> +        cache-unified;
>>> +        cache-level = <2>;
>>
>>
>> As this is completely unused on ARMv8 I don't think that we want to have
>> these unused entries in the DT.
>>
>> Sudeep: What do you think?
>>
>
> I am fine with that, I don't see any issue having them as they are
> static values and highly unlikely to change and hence no threat to
> backward compatibility.
>
> The main concern I had with latency values is that it's currently not
> used anywhere but if we decide to use say in secure software, having the
> untested/early values in DT might cause compatibility issues in future
> as they were added much before the actual understanding of it's usage.
> So I prefer to defer them until then.


Fine with me, thanks! :)

With this clarification:

Acked-by: Dirk Behme <dirk.behme@de.bosch.com>


Thanks again and best regards

Dirk

Re: [PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[Simon Horman]

On Mon, Feb 15, 2016 at 09:38:28PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds the missing L2 cache-controller nodes to the
> DTSes for various Renesas ARM-based SoCs, or completes the existing
> nodes, and links the CPU nodes to them.
> 
> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
> the respective (already existing) SYSC Power Domains. Fortunately these
> Power Domains were never powered down, as they are parents of the Power
> Domains containing CPU cores. This may change in the future.
> 
> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
> adding SYSC Power Domain support later.
> 
> Changes compared to v2:
>   - Dropped "arm,data-latency" and "arm,tag-latency" properties, as they
>     may not be valid when using virtualization,
>   - Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
>     r8a7795: Add L2 cache-controller nodes",
>   - Changed one-line summary prefix to match current arm-soc practices.
> 
> This series is against renesas-devel-20160215-v4.5-rc4.
> It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
> r8a7795/salvator-x.
> 
> For your convenience, I've also pushed this series to
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3
> 
> Thanks for applying!
> 
> Geert Uytterhoeven (7):
>   ARM: dts: r8a73a4: Add L2 cache-controller nodes
>   ARM: dts: r8a7790: Add L2 cache-controller nodes
>   ARM: dts: r8a7791: Add L2 cache-controller node
>   ARM: dts: r8a7793: Add L2 cache-controller node
>   ARM: dts: r8a7794: Add L2 cache-controller node
>   arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
>   arm64: dts: r8a7795: Add CA53 L2 cache-controller node

Thanks, I have queued these up for v4.6.

[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2 cache-controller nodes

[Simon Horman]

On Mon, Feb 15, 2016 at 09:38:28PM +0100, Geert Uytterhoeven wrote:
> 	Hi Simon, Magnus,
> 
> This patch series adds the missing L2 cache-controller nodes to the
> DTSes for various Renesas ARM-based SoCs, or completes the existing
> nodes, and links the CPU nodes to them.
> 
> For R-Mobile APE6 (r8a73a4), the L2 cache-controllers are also linked to
> the respective (already existing) SYSC Power Domains. Fortunately these
> Power Domains were never powered down, as they are parents of the Power
> Domains containing CPU cores. This may change in the future.
> 
> For R-Car Gen2 and Gen3 (r8a779x), this serves as a preparatory step for
> adding SYSC Power Domain support later.
> 
> Changes compared to v2:
>   - Dropped "arm,data-latency" and "arm,tag-latency" properties, as they
>     may not be valid when using virtualization,
>   - Dropped already applied parts of "[PATCH v2 6/6] arm64: renesas:
>     r8a7795: Add L2 cache-controller nodes",
>   - Changed one-line summary prefix to match current arm-soc practices.
> 
> This series is against renesas-devel-20160215-v4.5-rc4.
> It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
> r8a7795/salvator-x.
> 
> For your convenience, I've also pushed this series to
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/l2-cache-v3
> 
> Thanks for applying!
> 
> Geert Uytterhoeven (7):
>   ARM: dts: r8a73a4: Add L2 cache-controller nodes
>   ARM: dts: r8a7790: Add L2 cache-controller nodes
>   ARM: dts: r8a7791: Add L2 cache-controller node
>   ARM: dts: r8a7793: Add L2 cache-controller node
>   ARM: dts: r8a7794: Add L2 cache-controller node
>   arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
>   arm64: dts: r8a7795: Add CA53 L2 cache-controller node

Thanks, I have queued these up for v4.6.