From: Leon Alrae <leon.alrae@imgtec.com>
To: Aleksandar Markovic <Aleksandar.Markovic@imgtec.com>,
Aleksandar Markovic <aleksandar.markovic@rt-rk.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"ehabkost@redhat.com" <ehabkost@redhat.com>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
"rth@twiddle.net" <rth@twiddle.net>,
"mark.cave-ayland@ilande.co.uk" <mark.cave-ayland@ilande.co.uk>,
"agraf@suse.de" <agraf@suse.de>,
Petar Jovanovic <Petar.Jovanovic@imgtec.com>,
"blauwirbel@gmail.com" <blauwirbel@gmail.com>,
"jcmvbkbc@gmail.com" <jcmvbkbc@gmail.com>,
Miodrag Dinic <Miodrag.Dinic@imgtec.com>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"edgar.iglesias@gmail.com" <edgar.iglesias@gmail.com>,
"gxt@mprc.pku.edu.cn" <gxt@mprc.pku.edu.cn>,
"afaerber@suse.de" <afaerber@suse.de>,
"aurelien@aurel32.net" <aurelien@aurel32.net>,
"proljc@gmail.com" <proljc@gmail.com>
Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit
Date: Mon, 4 Apr 2016 17:10:24 +0100 [thread overview]
Message-ID: <570291F0.1010108@imgtec.com> (raw)
In-Reply-To: <EF5FA6C3467F85449672C3E735957B859168F4EA@BADAG02.ba.imgtec.org>
On 03/04/16 15:25, Aleksandar Markovic wrote:
> It just seems to me that, in similar case, 16-bit default NaN value should be 0x7E00. This value is needed for MSA operations. ("MIPS Architecture for Programmers Volume IV-j: The MIPS32® SIMD Architecture Module", Revision 1.12, (february 3, 2016), page 52, table 3.7 "Default NaN Encodings")
>
> I plan to include all three corrections in the next version of this patch set. Please, let me know if you think that I should not.
Great, thanks.
Also, the pickNaNMulAdd() for MIPS requires updating to match "3.5.3 NaN
Propagation" from the same MSA doc:
"When two or three operands are NaN, the payload of the resulting NaN is
identical to the payload of one of the input NaNs selected from left to
right as described by the instruction format".
This indicates the "c, a, b" order instead of "a, b, c" which is
currently implemented.
Regards,
Leon
next prev parent reply other threads:[~2016-04-04 16:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-25 12:50 [Qemu-devel] [PATCH 0/2] target-mips: Fix IEEE 754-2008-related issues Aleksandar Markovic
2016-03-25 12:50 ` [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit Aleksandar Markovic
2016-03-28 21:36 ` Richard Henderson
2016-04-04 13:21 ` Aleksandar Markovic
2016-04-04 13:31 ` Peter Maydell
2016-04-04 19:37 ` Eduardo Habkost
2016-04-04 19:38 ` Peter Maydell
2016-04-04 19:42 ` Eduardo Habkost
2016-04-04 19:46 ` Peter Maydell
2016-04-04 19:56 ` Eduardo Habkost
2016-03-29 12:50 ` Bastian Koppelmann
2016-03-30 16:58 ` Aleksandar Markovic
2016-04-01 19:02 ` Leon Alrae
2016-04-03 14:25 ` Aleksandar Markovic
2016-04-04 16:10 ` Leon Alrae [this message]
2016-03-25 12:50 ` [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008 functionality for R6 and MSA instructions Aleksandar Markovic
2016-03-28 21:49 ` Richard Henderson
2016-03-30 19:28 ` Aleksandar Markovic
2016-03-31 11:55 ` Aleksandar Markovic
2016-03-31 16:30 ` Richard Henderson
2016-04-01 19:07 ` Leon Alrae
2016-04-03 15:05 ` Aleksandar Markovic
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