[Qemu-devel] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Qemu-devel] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Luc MICHEL]

This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor instruction
to the cortex-r5. As stated in the TRM, this instruction invalidates all the
data cache. This trivial patch implements it as NOP as cache operations are not
implemented in QEMU.

The documentation is here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html

Tested using this minimal program:
 .global _start
 
 .section .text
 _start:
   mcr p15, 0, r1, c15, c5, 0
 
 idle:
   wfi
   b idle

Before implementation:
 IN: 
 0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}

 Taking exception 1 [Undefined Instruction]
 ...from EL1 to EL1
 ...with ESR 0x0/0x2000000

After implementation:
 IN: 
 0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}
 0x00008004:  e320f003      wfi

Luc MICHEL (1):
  target/arm: add data cache invalidation cp15 instruction to cortex-r5

 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.12.2

[Qemu-devel] [PATCH 1/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Luc MICHEL]

The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.

Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b357aee778..47687a40c4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1062,6 +1062,8 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST },
     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .type = ARM_CP_CONST },
+    { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
+      .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
     REGINFO_SENTINEL
 };
 
-- 
2.12.2

Re: [Qemu-devel] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Luc MICHEL]

[-- Attachment #1: Type: text/plain, Size: 1209 bytes --]

ping

The patchwork link: https://patchwork.ozlabs.org/patch/756408/

Thanks,

-- 
Luc

On 04/28/2017 02:56 PM, Luc MICHEL wrote:
> This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor
> instruction
> to the cortex-r5. As stated in the TRM, this instruction invalidates
> all the
> data cache. This trivial patch implements it as NOP as cache
> operations are not
> implemented in QEMU.
>
> The documentation is here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html
>
> Tested using this minimal program:
>  .global _start
>  
>  .section .text
>  _start:
>    mcr p15, 0, r1, c15, c5, 0
>  
>  idle:
>    wfi
>    b idle
>
> Before implementation:
>  IN:
>  0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}
>
>  Taking exception 1 [Undefined Instruction]
>  ...from EL1 to EL1
>  ...with ESR 0x0/0x2000000
>
> After implementation:
>  IN:
>  0x00008000:  ee0f1f15      mcr 15, 0, r1, cr15, cr5, {0}
>  0x00008004:  e320f003      wfi
>
> Luc MICHEL (1):
>   target/arm: add data cache invalidation cp15 instruction to cortex-r5
>
>  target/arm/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
>



[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [Qemu-devel] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5

[Michael Tokarev]

28.04.2017 15:56, Luc MICHEL wrote:
> This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor instruction
> to the cortex-r5. As stated in the TRM, this instruction invalidates all the
> data cache. This trivial patch implements it as NOP as cache operations are not
> implemented in QEMU.
> 
> The documentation is here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html

Applied to -trivial, since no one else picked it up so far :)

Thanks,

/mjt