From: Richard Henderson <richard.henderson@linaro.org>
To: liuzhiwei <zhiwei_liu@c-sky.com>,
Alistair.Francis@wdc.com, palmer@sifive.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
riku.voipio@iki.fi, laurent@vivier.eu, wenmeng_zhang@c-sky.com
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions
Date: Thu, 12 Sep 2019 10:57:47 -0400 [thread overview]
Message-ID: <5807ed99-e8a8-b845-2eb8-e8c5ae6176a4@linaro.org> (raw)
In-Reply-To: <1568183141-67641-8-git-send-email-zhiwei_liu@c-sky.com>
On 9/11/19 2:25 AM, liuzhiwei wrote:
> + case 64:
> + if (vector_elem_mask(env, vm, width, lmul, i)) {
> + int64_t tmp;
> + idx = (target_long)env->vfp.vreg[src2].s64[j];
> + addr = idx + env->gpr[rs1];
> +
> +#ifdef CONFIG_SOFTMMU
> + tmp = (int64_t)(int32_t)helper_atomic_xchgl_le(env, addr,
> + env->vfp.vreg[src3].s64[j],
> + make_memop_idx(memop & ~MO_SIGN, mem_idx));
> +#else
> + tmp = (int64_t)(int32_t)helper_atomic_xchgl_le(env, addr,
> + env->vfp.vreg[src3].s64[j]);
> +#endif
> + if (wd) {
> + env->vfp.vreg[src3].s64[j] = tmp;
> + }
> + env->vfp.vstart++;
> + }
> + break;
This will not link if !defined(CONFIG_ATOMIC64).
That's pretty rare these days, admittedly. I think you'd need to compile for
ppc32 or mips32 (or riscv32!) host to see this. You can force this condition
for i686 host with --extra-cflags='-march=i486', just to see if you've got it
right.
There should be two different versions of this helper: one that performs actual
atomic operations, as above, and a second that performs the same operation with
non-atomic operations.
The version of the helper that you call should be based on the translation time
setting of "tb_cflags(s->base.tb) & CF_PARALLEL": If PARALLEL is set, call the
atomic helper otherwise the non-atomic helper.
If you arrive at a situation in which the host cannot handle any atomic
operation, then you must raise the EXCP_ATOMIC exception. This will halt all
other cpus and run one instruction on this cpu while holding the exclusive lock.
If you cannot detect this condition any earlier than here at runtime, use
cpu_loop_exit_atomic(), but you must do so before altering any cpu state.
However, as per my comments for normal loads, you should be able to detect this
condition at translation time and call gen_helper_exit_atomic().
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: liuzhiwei <zhiwei_liu@c-sky.com>,
Alistair.Francis@wdc.com, palmer@sifive.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
riku.voipio@iki.fi, laurent@vivier.eu, wenmeng_zhang@c-sky.com
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions
Date: Thu, 12 Sep 2019 10:57:47 -0400 [thread overview]
Message-ID: <5807ed99-e8a8-b845-2eb8-e8c5ae6176a4@linaro.org> (raw)
In-Reply-To: <1568183141-67641-8-git-send-email-zhiwei_liu@c-sky.com>
On 9/11/19 2:25 AM, liuzhiwei wrote:
> + case 64:
> + if (vector_elem_mask(env, vm, width, lmul, i)) {
> + int64_t tmp;
> + idx = (target_long)env->vfp.vreg[src2].s64[j];
> + addr = idx + env->gpr[rs1];
> +
> +#ifdef CONFIG_SOFTMMU
> + tmp = (int64_t)(int32_t)helper_atomic_xchgl_le(env, addr,
> + env->vfp.vreg[src3].s64[j],
> + make_memop_idx(memop & ~MO_SIGN, mem_idx));
> +#else
> + tmp = (int64_t)(int32_t)helper_atomic_xchgl_le(env, addr,
> + env->vfp.vreg[src3].s64[j]);
> +#endif
> + if (wd) {
> + env->vfp.vreg[src3].s64[j] = tmp;
> + }
> + env->vfp.vstart++;
> + }
> + break;
This will not link if !defined(CONFIG_ATOMIC64).
That's pretty rare these days, admittedly. I think you'd need to compile for
ppc32 or mips32 (or riscv32!) host to see this. You can force this condition
for i686 host with --extra-cflags='-march=i486', just to see if you've got it
right.
There should be two different versions of this helper: one that performs actual
atomic operations, as above, and a second that performs the same operation with
non-atomic operations.
The version of the helper that you call should be based on the translation time
setting of "tb_cflags(s->base.tb) & CF_PARALLEL": If PARALLEL is set, call the
atomic helper otherwise the non-atomic helper.
If you arrive at a situation in which the host cannot handle any atomic
operation, then you must raise the EXCP_ATOMIC exception. This will halt all
other cpus and run one instruction on this cpu while holding the exclusive lock.
If you cannot detect this condition any earlier than here at runtime, use
cpu_loop_exit_atomic(), but you must do so before altering any cpu state.
However, as per my comments for normal loads, you should be able to detect this
condition at translation time and call gen_helper_exit_atomic().
r~
next prev parent reply other threads:[~2019-09-12 14:59 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 6:25 [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 14:51 ` [Qemu-devel] " Chih-Min Chao
2019-09-11 14:51 ` [Qemu-riscv] " Chih-Min Chao
2019-09-11 22:39 ` Richard Henderson
2019-09-11 22:39 ` [Qemu-riscv] " Richard Henderson
2019-09-12 14:53 ` Chih-Min Chao
2019-09-12 14:53 ` [Qemu-riscv] " Chih-Min Chao
2019-09-12 15:06 ` Richard Henderson
2019-09-12 15:06 ` [Qemu-riscv] " Richard Henderson
2019-09-17 8:09 ` liuzhiwei
2019-09-17 8:09 ` [Qemu-riscv] " liuzhiwei
2019-09-11 22:32 ` Richard Henderson
2019-09-11 22:32 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 15:00 ` [Qemu-devel] " Chih-Min Chao
2019-09-11 15:00 ` [Qemu-riscv] " Chih-Min Chao
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 15:25 ` [Qemu-devel] " Chih-Min Chao
2019-09-11 15:25 ` Chih-Min Chao
2019-09-11 22:43 ` [Qemu-devel] " Richard Henderson
2019-09-11 22:43 ` [Qemu-riscv] " Richard Henderson
2019-09-14 13:58 ` Palmer Dabbelt
2019-09-14 13:58 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 16:04 ` [Qemu-devel] " Chih-Min Chao
2019-09-11 16:04 ` Chih-Min Chao
2019-09-11 23:09 ` [Qemu-devel] " Richard Henderson
2019-09-11 23:09 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 14:23 ` [Qemu-devel] " Richard Henderson
2019-09-12 14:23 ` [Qemu-riscv] " Richard Henderson
2020-01-08 1:32 ` LIU Zhiwei
2020-01-08 1:32 ` LIU Zhiwei
2020-01-08 2:08 ` Richard Henderson
2020-01-08 2:08 ` Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 14:32 ` [Qemu-devel] " Richard Henderson
2019-09-12 14:32 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 14:57 ` Richard Henderson [this message]
2019-09-12 14:57 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 15:27 ` [Qemu-devel] " Richard Henderson
2019-09-12 15:27 ` [Qemu-riscv] " Richard Henderson
2019-09-12 15:35 ` Richard Henderson
2019-09-12 15:35 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 16:41 ` [Qemu-devel] " Richard Henderson
2019-09-12 16:41 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 11/17] RISC-V: add vector extension integer instructions part4, mul/div/merge liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 12/17] RISC-V: add vector extension fixed point instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 13/17] RISC-V: add vector extension float instruction part1, add/sub/mul/div liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 14/17] RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 16:54 ` [Qemu-devel] " Richard Henderson
2019-09-12 16:54 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 17:07 ` [Qemu-devel] " Richard Henderson
2019-09-12 17:07 ` [Qemu-riscv] " Richard Henderson
2019-09-11 6:25 ` [Qemu-devel] [PATCH v2 17/17] RISC-V: add vector extension premutation instructions liuzhiwei
2019-09-11 6:25 ` [Qemu-riscv] " liuzhiwei
2019-09-12 17:13 ` [Qemu-devel] " Richard Henderson
2019-09-12 17:13 ` [Qemu-riscv] " Richard Henderson
2019-09-11 7:00 ` [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension Aleksandar Markovic
2019-09-11 7:00 ` [Qemu-riscv] " Aleksandar Markovic
2019-09-14 12:59 ` Palmer Dabbelt
2019-09-14 12:59 ` [Qemu-riscv] " Palmer Dabbelt
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