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From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Kevin Tian <kevin.tian@intel.com>, Wei Liu <wei.liu2@citrix.com>,
	Tim Deegan <tim@xen.org>, Xen-devel <xen-devel@lists.xen.org>,
	Jun Nakajima <jun.nakajima@intel.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v2 9/9] x86/vmx: Don't leak EFER.NXE into guest context
Date: Tue, 12 Jun 2018 02:54:15 -0600	[thread overview]
Message-ID: <5B1F8A3702000078001CA457@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <1528483723-4128-10-git-send-email-andrew.cooper3@citrix.com>

>>> On 08.06.18 at 20:48, <andrew.cooper3@citrix.com> wrote:
> @@ -1646,22 +1637,71 @@ static void vmx_update_guest_cr(struct vcpu *v, unsigned int cr,
>  
>  static void vmx_update_guest_efer(struct vcpu *v)
>  {
> -    unsigned long vm_entry_value;
> +    unsigned long entry_ctls, guest_efer = v->arch.hvm_vcpu.guest_efer,
> +        xen_efer = read_efer();
> +
> +    if ( paging_mode_shadow(v->domain) )
> +    {
> +        /*
> +         * When using shadow pagetables, EFER.NX is a Xen-owned bit and is not
> +         * under guest control.
> +         */
> +        guest_efer &= ~EFER_NX;
> +        guest_efer |= xen_efer & EFER_NX;
> +    }
> +
> +    if ( !(v->arch.hvm_vmx.secondary_exec_control &
> +           SECONDARY_EXEC_UNRESTRICTED_GUEST) )

!vmx_unrestricted_guest(v)

> +    {
> +        /*
> +         * When Unrestricted Guest is not enabled in the VMCS, hardware does
> +         * not tolerate the LME and LMA settings being different.  As writes
> +         * to CR0 are intercepted, it is safe to leave LME clear at this
> +         * point, and fix up both LME and LMA when CR0.PG is set.
> +         */
> +        if ( !(guest_efer & EFER_LMA) )
> +            guest_efer &= ~EFER_LME;
> +    }
>  
>      vmx_vmcs_enter(v);
>  
> -    __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
> -    if ( v->arch.hvm_vcpu.guest_efer & EFER_LMA )
> -        vm_entry_value |= VM_ENTRY_IA32E_MODE;
> +    /*
> +     * The intended guest running mode is derived from VM_ENTRY_IA32E_MODE,
> +     * which (architecturally) is the guest's LMA setting.
> +     */
> +    __vmread(VM_ENTRY_CONTROLS, &entry_ctls);
> +
> +    entry_ctls &= ~VM_ENTRY_IA32E_MODE;
> +    if ( guest_efer & EFER_LMA )
> +        entry_ctls |= VM_ENTRY_IA32E_MODE;
> +
> +    __vmwrite(VM_ENTRY_CONTROLS, entry_ctls);
> +
> +    /* We expect to use EFER loading in the common case, but... */
> +    if ( likely(cpu_has_vmx_efer) )
> +        __vmwrite(GUEST_EFER, guest_efer);
> +
> +    /* ... on Gen1 VT-x hardware, we have to use MSR load/save lists instead. */
>      else
> -        vm_entry_value &= ~VM_ENTRY_IA32E_MODE;
> -    __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
> +    {
> +        /*
> +         * When the guests choice of EFER matches Xen's, remove the load/save
> +         * list entries.  It is unnecessary overhead, especially as this is
> +         * expected to be the common case for 64bit guests.
> +         */
> +        if ( guest_efer == xen_efer )
> +        {
> +            vmx_del_msr(v, MSR_EFER, VMX_MSR_HOST);
> +            vmx_del_msr(v, MSR_EFER, VMX_MSR_GUEST_LOADONLY);
> +        }
> +        else
> +        {
> +            vmx_add_msr(v, MSR_EFER, xen_efer, VMX_MSR_HOST);
> +            vmx_add_msr(v, MSR_EFER, guest_efer, VMX_MSR_GUEST_LOADONLY);
> +        }
> +    }
>  
>      vmx_vmcs_exit(v);
> -
> -    if ( v == current )
> -        write_efer((read_efer() & ~EFER_SCE) |
> -                   (v->arch.hvm_vcpu.guest_efer & EFER_SCE));
>  }

As mentioned before, overall this would allow for disabling read intercepts in
certain cases. If you don't want to do this right away that's certainly fine, but
could I talk you into at least adding a comment to this effect?

> --- a/xen/include/asm-x86/hvm/vmx/vmcs.h
> +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
> @@ -311,6 +311,8 @@ extern u64 vmx_ept_vpid_cap;
>      (vmx_cpu_based_exec_control & CPU_BASED_MONITOR_TRAP_FLAG)
>  #define cpu_has_vmx_pat \
>      (vmx_vmentry_control & VM_ENTRY_LOAD_GUEST_PAT)
> +#define cpu_has_vmx_efer \
> +    (vmx_vmentry_control & VM_ENTRY_LOAD_GUEST_EFER)

I think this was asked before, but I'm concerned (of at least the inconsistency)
anyway: cpu_has_vmx_mpx, for example, checks both flags. Of course there's
unlikely to be any hardware with just one of the two features, but what about
buggy virtual environments we might run in?

IOW - if you want to check just one of the two flags here, I think you want to
enforce the dependency in vmx_init_vmcs_config(), clearing the entry control
bit if the exit control one comes out clear from adjust_vmx_controls().

Jan


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  parent reply	other threads:[~2018-06-12  8:54 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-08 18:48 [PATCH v2 0/9] x86/vmx: Don't leak EFER.NXE into guest context Andrew Cooper
2018-06-08 18:48 ` [PATCH v2 1/9] x86/vmx: API improvements for MSR load/save infrastructure Andrew Cooper
2018-06-08 18:48 ` [PATCH v2 2/9] x86/vmx: Internal cleanup " Andrew Cooper
2018-06-08 18:48 ` [PATCH v2 3/9] x86/vmx: Factor locate_msr_entry() out of vmx_find_msr() and vmx_add_msr() Andrew Cooper
2018-06-08 18:48 ` [PATCH v2 4/9] x86/vmx: Support remote access to the MSR lists Andrew Cooper
2018-06-12  2:49   ` Tian, Kevin
2018-06-12  8:06   ` Jan Beulich
2018-06-08 18:48 ` [PATCH v2 5/9] x86/vmx: Improvements to LBR MSR handling Andrew Cooper
2018-06-12  2:58   ` Tian, Kevin
2018-06-12  8:15   ` Jan Beulich
2018-06-12  8:51     ` Andrew Cooper
2018-06-12  9:00       ` Jan Beulich
2018-06-12 16:33         ` Andrew Cooper
2018-06-13  6:30           ` Jan Beulich
2018-06-13 10:37             ` Andrew Cooper
2018-06-27  8:43   ` [PATCH v3 " Andrew Cooper
2018-06-27  9:12     ` Jan Beulich
2018-06-27  9:50       ` Andrew Cooper
2018-06-27  9:58         ` Jan Beulich
2018-06-27  9:59           ` Andrew Cooper
2018-06-08 18:48 ` [PATCH v2 6/9] x86/vmx: Pass an MSR value into vmx_msr_add() Andrew Cooper
2018-06-12  3:11   ` Tian, Kevin
2018-06-12  8:19   ` Jan Beulich
2018-06-08 18:48 ` [PATCH v2 7/9] x86/vmx: Support load-only guest MSR list entries Andrew Cooper
2018-06-12  3:22   ` Tian, Kevin
2018-06-08 18:48 ` [PATCH v2 8/9] x86/vmx: Support removing MSRs from the host/guest load/save lists Andrew Cooper
2018-06-12  3:24   ` Tian, Kevin
2018-06-12  8:27   ` Jan Beulich
2018-06-12 17:40     ` Andrew Cooper
2018-06-12 18:23       ` Andrew Cooper
2018-06-13  6:33       ` Jan Beulich
2018-06-08 18:48 ` [PATCH v2 9/9] x86/vmx: Don't leak EFER.NXE into guest context Andrew Cooper
2018-06-12  6:04   ` Tian, Kevin
2018-06-12  8:54   ` Jan Beulich [this message]
2018-06-13 10:19     ` Andrew Cooper
2018-06-13 11:19   ` [PATCH v3 " Andrew Cooper

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