[RFC 00/15] support subsets of bitmanip extension

[RFC 00/15] support subsets of bitmanip extension

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

This patchset implements RISC-V B-extension latest draft version
(2020.10.26) Zbb, Zbs and Zba subset instructions.

Specification:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf

The port is available here:
https://github.com/sifive/qemu/tree/rvb-upstream-v1

To test rvb implementation, specify cpu argument with 'x-b=true' to
enable B-extension support.


Frank Chang (2):
  target/riscv: rvb: generalized reverse
  target/riscv: rvb: generalized or-combine

Kito Cheng (13):
  target/riscv: reformat @sh format encoding for B-extension
  target/riscv: rvb: count leading/trailing zeros
  target/riscv: rvb: count bits set
  target/riscv: rvb: logic-with-negate
  target/riscv: rvb: pack two words into one register
  target/riscv: rvb: min/max instructions
  target/riscv: rvb: sign-extend instructions
  target/riscv: rvb: single-bit instructions
  target/riscv: rvb: shift ones
  target/riscv: rvb: rotate (left/right)
  target/riscv: rvb: address calculation
  target/riscv: rvb: add/sub with postfix zero-extend
  target/riscv: rvb: support and turn on B-extension from command line

 target/riscv/bitmanip_helper.c          | 128 +++++
 target/riscv/cpu.c                      |   4 +
 target/riscv/cpu.h                      |   2 +
 target/riscv/helper.h                   |   9 +
 target/riscv/insn32-64.decode           |  37 ++
 target/riscv/insn32.decode              |  54 ++-
 target/riscv/insn_trans/trans_rvb.c.inc | 475 +++++++++++++++++++
 target/riscv/meson.build                |   1 +
 target/riscv/translate.c                | 597 ++++++++++++++++++++++++
 9 files changed, 1301 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/bitmanip_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

--
2.17.1

[RFC 01/15] target/riscv: reformat @sh format encoding for B-extension

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..190ce469faf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,7 +22,7 @@
 %rs1       15:5
 %rd        7:5
 
-%sh10    20:10
+%sh6    20:6
 %csr    20:12
 %rm     12:3
 %nf     29:3                     !function=ex_plus_1
@@ -58,7 +58,7 @@
 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
 
-@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
+@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh6     %rs1 %rd
 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
 
 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@@ -122,9 +122,9 @@ sltiu    ............     ..... 011 ..... 0010011 @i
 xori     ............     ..... 100 ..... 0010011 @i
 ori      ............     ..... 110 ..... 0010011 @i
 andi     ............     ..... 111 ..... 0010011 @i
-slli     00.... ......    ..... 001 ..... 0010011 @sh
-srli     00.... ......    ..... 101 ..... 0010011 @sh
-srai     01.... ......    ..... 101 ..... 0010011 @sh
+slli     000000 ......    ..... 001 ..... 0010011 @sh
+srli     000000 ......    ..... 101 ..... 0010011 @sh
+srai     010000 ......    ..... 101 ..... 0010011 @sh
 add      0000000 .....    ..... 000 ..... 0110011 @r
 sub      0100000 .....    ..... 000 ..... 0110011 @r
 sll      0000000 .....    ..... 001 ..... 0110011 @r
-- 
2.17.1

[RFC 01/15] target/riscv: reformat @sh format encoding for B-extension

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..190ce469faf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,7 +22,7 @@
 %rs1       15:5
 %rd        7:5
 
-%sh10    20:10
+%sh6    20:6
 %csr    20:12
 %rm     12:3
 %nf     29:3                     !function=ex_plus_1
@@ -58,7 +58,7 @@
 @u       ....................      ..... ....... &u      imm=%imm_u          %rd
 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
 
-@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
+@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh6     %rs1 %rd
 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
 
 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@@ -122,9 +122,9 @@ sltiu    ............     ..... 011 ..... 0010011 @i
 xori     ............     ..... 100 ..... 0010011 @i
 ori      ............     ..... 110 ..... 0010011 @i
 andi     ............     ..... 111 ..... 0010011 @i
-slli     00.... ......    ..... 001 ..... 0010011 @sh
-srli     00.... ......    ..... 101 ..... 0010011 @sh
-srai     01.... ......    ..... 101 ..... 0010011 @sh
+slli     000000 ......    ..... 001 ..... 0010011 @sh
+srli     000000 ......    ..... 101 ..... 0010011 @sh
+srai     010000 ......    ..... 101 ..... 0010011 @sh
 add      0000000 .....    ..... 000 ..... 0110011 @r
 sub      0100000 .....    ..... 000 ..... 0110011 @r
 sll      0000000 .....    ..... 001 ..... 0110011 @r
-- 
2.17.1

Re: [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> -slli     00.... ......    ..... 001 ..... 0010011 @sh
> -srli     00.... ......    ..... 101 ..... 0010011 @sh
> -srai     01.... ......    ..... 101 ..... 0010011 @sh
> +slli     000000 ......    ..... 001 ..... 0010011 @sh
> +srli     000000 ......    ..... 101 ..... 0010011 @sh
> +srai     010000 ......    ..... 101 ..... 0010011 @sh

We need at least 7 bits here for rv128, if we ever get around to it.  The code
in trans_slli et al already eliminates numbers that are two large.

In the rvb draft, only 5 bits are used in the uppermost field.  Let's leave it
at that.


r~

Re: [RFC 01/15] target/riscv: reformat @sh format encoding for B-extension

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> -slli     00.... ......    ..... 001 ..... 0010011 @sh
> -srli     00.... ......    ..... 101 ..... 0010011 @sh
> -srai     01.... ......    ..... 101 ..... 0010011 @sh
> +slli     000000 ......    ..... 001 ..... 0010011 @sh
> +srli     000000 ......    ..... 101 ..... 0010011 @sh
> +srai     010000 ......    ..... 101 ..... 0010011 @sh

We need at least 7 bits here for rv128, if we ever get around to it.  The code
in trans_slli et al already eliminates numbers that are two large.

In the rvb draft, only 5 bits are used in the uppermost field.  Let's leave it
at that.


r~

[RFC 02/15] target/riscv: rvb: count leading/trailing zeros

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  4 +++
 target/riscv/insn32.decode              |  7 +++-
 target/riscv/insn_trans/trans_rvb.c.inc | 47 ++++++++++++++++++++++++
 target/riscv/translate.c                | 48 +++++++++++++++++++++++++
 4 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..250279e62ea 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -86,3 +86,7 @@ fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw       011000000000 ..... 001 ..... 0011011 @r2
+ctzw       011000000001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 190ce469faf..884ed2a42fa 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
 &i    imm rs1 rd
 &j    imm rd
 &r    rd rs1 rs2
+&r2   rd rs1
 &s    imm rs1 rs2
 &u    imm rd
 &shift     shamt rs1 rd
@@ -67,7 +68,7 @@
 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
+@r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -592,3 +593,7 @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
+
+# *** RV32B Standard Extension ***
+clz        011000000000 ..... 001 ..... 0010011 @r2
+ctz        011000000001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..1f02cb91a0a
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,47 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxz(ctx, a, &tcg_gen_clzi_tl);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxz(ctx, a, &tcg_gen_ctzi_tl);
+}
+
+/* RV64-only instructions */
+#ifdef TARGET_RISCV64
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxzw(ctx, a, &tcg_gen_clzi_i32);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32);
+}
+
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 79dca2291bc..20b47f7a660 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -710,6 +710,34 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 
 #endif
 
+#ifdef TARGET_RISCV64
+
+static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
+                     void(*func)(TCGv_i32, TCGv_i32, uint32_t))
+{
+    TCGv source;
+    TCGv_i32 tmp;
+
+    tmp = tcg_temp_new_i32();
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(tmp, source);
+
+    (*func)(tmp, tmp, 32);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(source, tmp);
+    gen_set_gpr(a->rd, source);
+
+    tcg_temp_free(source);
+    tcg_temp_free_i32(tmp);
+    return true;
+}
+
+#endif
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
@@ -746,6 +774,25 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
     return true;
 }
 
+static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
+                    void(*func)(TCGv, TCGv, target_ulong))
+{
+    TCGv source;
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+
+#ifdef TARGET_RISCV64
+    (*func)(source, source, 64);
+#else
+    (*func)(source, source, 32);
+#endif
+
+    gen_set_gpr(a->rd, source);
+    tcg_temp_free(source);
+    return true;
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
@@ -754,6 +801,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rvd.c.inc"
 #include "insn_trans/trans_rvh.c.inc"
 #include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
-- 
2.17.1

[RFC 02/15] target/riscv: rvb: count leading/trailing zeros

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  4 +++
 target/riscv/insn32.decode              |  7 +++-
 target/riscv/insn_trans/trans_rvb.c.inc | 47 ++++++++++++++++++++++++
 target/riscv/translate.c                | 48 +++++++++++++++++++++++++
 4 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..250279e62ea 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -86,3 +86,7 @@ fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw       011000000000 ..... 001 ..... 0011011 @r2
+ctzw       011000000001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 190ce469faf..884ed2a42fa 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
 &i    imm rs1 rd
 &j    imm rd
 &r    rd rs1 rs2
+&r2   rd rs1
 &s    imm rs1 rs2
 &u    imm rd
 &shift     shamt rs1 rd
@@ -67,7 +68,7 @@
 @r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
 @r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
+@r2      .......   ..... ..... ... ..... ....... &r2 %rs1 %rd
 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
 @r2_vm   ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
 @r1_vm   ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -592,3 +593,7 @@ vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
+
+# *** RV32B Standard Extension ***
+clz        011000000000 ..... 001 ..... 0010011 @r2
+ctz        011000000001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..1f02cb91a0a
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,47 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxz(ctx, a, &tcg_gen_clzi_tl);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxz(ctx, a, &tcg_gen_ctzi_tl);
+}
+
+/* RV64-only instructions */
+#ifdef TARGET_RISCV64
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxzw(ctx, a, &tcg_gen_clzi_i32);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32);
+}
+
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 79dca2291bc..20b47f7a660 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -710,6 +710,34 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 
 #endif
 
+#ifdef TARGET_RISCV64
+
+static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
+                     void(*func)(TCGv_i32, TCGv_i32, uint32_t))
+{
+    TCGv source;
+    TCGv_i32 tmp;
+
+    tmp = tcg_temp_new_i32();
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(tmp, source);
+
+    (*func)(tmp, tmp, 32);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(source, tmp);
+    gen_set_gpr(a->rd, source);
+
+    tcg_temp_free(source);
+    tcg_temp_free_i32(tmp);
+    return true;
+}
+
+#endif
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
@@ -746,6 +774,25 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
     return true;
 }
 
+static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
+                    void(*func)(TCGv, TCGv, target_ulong))
+{
+    TCGv source;
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+
+#ifdef TARGET_RISCV64
+    (*func)(source, source, 64);
+#else
+    (*func)(source, source, 32);
+#endif
+
+    gen_set_gpr(a->rd, source);
+    tcg_temp_free(source);
+    return true;
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
@@ -754,6 +801,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rvd.c.inc"
 #include "insn_trans/trans_rvh.c.inc"
 #include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
-- 
2.17.1

Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
> +                     void(*func)(TCGv_i32, TCGv_i32, uint32_t))
...
> +static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
> +                    void(*func)(TCGv, TCGv, target_ulong))

I think both of these are unnecessary and you should use the gen_unary that you
introduce in the next patch.  ctz/clz cannot produce a negative number and do
not need extension.

You should simply add wrappers like you do for gen_pcntw to truncate and operate:

static void gen_ctz(TCGv ret, TCGv arg1)
{
    tcg_gen_ctz_tl(ret, arg1, TARGET_LONG_BITS);
}

static void gen_clz(TCGv ret, TCGv arg1)
{
    tcg_gen_clz_tl(ret, arg1, TARGET_LONG_BITS);
}

static void gen_ctzw(TCGv ret, TCGv arg1)
{
    tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
    tcg_gen_ctz_i64(ret, ret, 32);
}

static void gen_clzw(TCGv ret, TCGv arg1)
{
    tcg_gen_ext32u_i64(ret, arg1);
    tcg_gen_ctz_i64(ret, ret, 64);
    tcg_gen_subi_i64(ret, ret, 32);
}


r~

Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
> +                     void(*func)(TCGv_i32, TCGv_i32, uint32_t))
...
> +static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
> +                    void(*func)(TCGv, TCGv, target_ulong))

I think both of these are unnecessary and you should use the gen_unary that you
introduce in the next patch.  ctz/clz cannot produce a negative number and do
not need extension.

You should simply add wrappers like you do for gen_pcntw to truncate and operate:

static void gen_ctz(TCGv ret, TCGv arg1)
{
    tcg_gen_ctz_tl(ret, arg1, TARGET_LONG_BITS);
}

static void gen_clz(TCGv ret, TCGv arg1)
{
    tcg_gen_clz_tl(ret, arg1, TARGET_LONG_BITS);
}

static void gen_ctzw(TCGv ret, TCGv arg1)
{
    tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
    tcg_gen_ctz_i64(ret, ret, 32);
}

static void gen_clzw(TCGv ret, TCGv arg1)
{
    tcg_gen_ext32u_i64(ret, arg1);
    tcg_gen_ctz_i64(ret, ret, 64);
    tcg_gen_subi_i64(ret, ret, 32);
}


r~

Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw       011000000000 ..... 001 ..... 0011011 @r2
> +ctzw       011000000001 ..... 001 ..... 0011011 @r2

Oh, one more thing.  In the draft, the top decode bits are split into two
fields: 7+5.  It would be easier to read all of these if you did the same here.


r~

Re: [RFC 02/15] target/riscv: rvb: count leading/trailing zeros

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw       011000000000 ..... 001 ..... 0011011 @r2
> +ctzw       011000000001 ..... 001 ..... 0011011 @r2

Oh, one more thing.  In the draft, the top decode bits are split into two
fields: 7+5.  It would be easier to read all of these if you did the same here.


r~

[RFC 03/15] target/riscv: rvb: count bits set

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  1 +
 target/riscv/insn32.decode              |  1 +
 target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
 target/riscv/translate.c                | 21 +++++++++++++++++++++
 4 files changed, 35 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 250279e62ea..d5bea5af273 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       011000000000 ..... 001 ..... 0011011 @r2
 ctzw       011000000001 ..... 001 ..... 0011011 @r2
+pcntw      011000000010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 884ed2a42fa..9e70a85d6f0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 # *** RV32B Standard Extension ***
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
+pcnt       011000000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 1f02cb91a0a..6f1054e3908 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
     return gen_cxz(ctx, a, &tcg_gen_ctzi_tl);
 }
 
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
     return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32);
 }
 
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &gen_pcntw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 20b47f7a660..97e5899750e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -736,6 +736,12 @@ static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
     return true;
 }
 
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_ctpop_tl(ret, arg1);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
@@ -793,6 +799,21 @@ static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
     return true;
 }
 
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+                      void(*func)(TCGv, TCGv))
+{
+    TCGv source;
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+
+    (*func)(source, source);
+
+    gen_set_gpr(a->rd, source);
+    tcg_temp_free(source);
+    return true;
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
-- 
2.17.1

[RFC 03/15] target/riscv: rvb: count bits set

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  1 +
 target/riscv/insn32.decode              |  1 +
 target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
 target/riscv/translate.c                | 21 +++++++++++++++++++++
 4 files changed, 35 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 250279e62ea..d5bea5af273 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       011000000000 ..... 001 ..... 0011011 @r2
 ctzw       011000000001 ..... 001 ..... 0011011 @r2
+pcntw      011000000010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 884ed2a42fa..9e70a85d6f0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 # *** RV32B Standard Extension ***
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
+pcnt       011000000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 1f02cb91a0a..6f1054e3908 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
     return gen_cxz(ctx, a, &tcg_gen_ctzi_tl);
 }
 
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
     return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32);
 }
 
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &gen_pcntw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 20b47f7a660..97e5899750e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -736,6 +736,12 @@ static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
     return true;
 }
 
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_ctpop_tl(ret, arg1);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
@@ -793,6 +799,21 @@ static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
     return true;
 }
 
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+                      void(*func)(TCGv, TCGv))
+{
+    TCGv source;
+    source = tcg_temp_new();
+
+    gen_get_gpr(source, a->rs1);
+
+    (*func)(source, source);
+
+    gen_set_gpr(a->rd, source);
+    tcg_temp_free(source);
+    return true;
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
-- 
2.17.1

Re: [RFC 03/15] target/riscv: rvb: count bits set

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32-64.decode           |  1 +
>  target/riscv/insn32.decode              |  1 +
>  target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
>  target/riscv/translate.c                | 21 +++++++++++++++++++++
>  4 files changed, 35 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC 03/15] target/riscv: rvb: count bits set

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32-64.decode           |  1 +
>  target/riscv/insn32.decode              |  1 +
>  target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
>  target/riscv/translate.c                | 21 +++++++++++++++++++++
>  4 files changed, 35 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC 04/15] target/riscv: rvb: logic-with-negate

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  4 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++
 target/riscv/translate.c                | 33 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9e70a85d6f0..29a3d4c6ebc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
 pcnt       011000000010 ..... 001 ..... 0010011 @r2
+
+andn       0100000 .......... 111 ..... 0110011 @r
+orn        0100000 .......... 110 ..... 0110011 @r
+xnor       0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6f1054e3908..be25431e990 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
     return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
 }
 
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_andn);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_orn);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_xnor);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 97e5899750e..254a9dca8c2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -710,6 +710,39 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 
 #endif
 
+static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_and_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_or_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_xor_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
 #ifdef TARGET_RISCV64
 
 static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
-- 
2.17.1

[RFC 04/15] target/riscv: rvb: logic-with-negate

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  4 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++
 target/riscv/translate.c                | 33 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9e70a85d6f0..29a3d4c6ebc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
 pcnt       011000000010 ..... 001 ..... 0010011 @r2
+
+andn       0100000 .......... 111 ..... 0110011 @r
+orn        0100000 .......... 110 ..... 0110011 @r
+xnor       0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6f1054e3908..be25431e990 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
     return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
 }
 
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_andn);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_orn);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_xnor);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 97e5899750e..254a9dca8c2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -710,6 +710,39 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
 
 #endif
 
+static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_and_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_or_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
+static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    tcg_gen_not_tl(t, arg2);
+    tcg_gen_xor_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
 #ifdef TARGET_RISCV64
 
 static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
-- 
2.17.1

Re: [RFC 04/15] target/riscv: rvb: logic-with-negate

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_and_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_andc_tl.

> +static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_or_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_orc_tl.

> +static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_xor_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_eqv_tl.


r~

Re: [RFC 04/15] target/riscv: rvb: logic-with-negate

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_and_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_andc_tl.

> +static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_or_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_orc_tl.

> +static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();
> +
> +    tcg_gen_not_tl(t, arg2);
> +    tcg_gen_xor_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}

This is tcg_gen_eqv_tl.


r~

[RFC 05/15] target/riscv: rvb: pack two words into one register

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 +
 target/riscv/insn32.decode              |  3 +
 target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++
 target/riscv/translate.c                | 92 +++++++++++++++++++++++++
 4 files changed, 128 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index d5bea5af273..2f00f96e36b 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -91,3 +91,6 @@ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 clzw       011000000000 ..... 001 ..... 0011011 @r2
 ctzw       011000000001 ..... 001 ..... 0011011 @r2
 pcntw      011000000010 ..... 001 ..... 0011011 @r2
+
+packw      0000100 .......... 100 ..... 0111011 @r
+packuw     0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 29a3d4c6ebc..79aa40f03dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,3 +602,6 @@ pcnt       011000000010 ..... 001 ..... 0010011 @r2
 andn       0100000 .......... 111 ..... 0110011 @r
 orn        0100000 .......... 110 ..... 0110011 @r
 xnor       0100000 .......... 100 ..... 0110011 @r
+pack       0000100 .......... 100 ..... 0110011 @r
+packu      0100100 .......... 100 ..... 0110011 @r
+packh      0000100 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index be25431e990..9257373ae0b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
     return gen_arith(ctx, a, &gen_xnor);
 }
 
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packh);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -74,4 +92,16 @@ static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
     return gen_unary(ctx, a, &gen_pcntw);
 }
 
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packuw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 254a9dca8c2..fb30ee83aa8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -743,6 +743,65 @@ static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+#ifdef TARGET_RISCV64
+    tcg_gen_ext32u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 32);
+#else
+    tcg_gen_ext16u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 16);
+#endif
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+#ifdef TARGET_RISCV64
+    tcg_gen_shri_tl(lower, arg1, 32);
+    tcg_gen_shri_tl(higher, arg2, 32);
+    tcg_gen_shli_tl(higher, higher, 32);
+#else
+    tcg_gen_shri_tl(lower, arg1, 16);
+    tcg_gen_shri_tl(higher, arg2, 16);
+    tcg_gen_shli_tl(higher, higher, 16);
+#endif
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_ext8u_tl(lower, arg1);
+    tcg_gen_ext8u_tl(higher, arg2);
+    tcg_gen_shli_tl(higher, higher, 8);
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+
 #ifdef TARGET_RISCV64
 
 static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
@@ -775,6 +834,39 @@ static void gen_pcntw(TCGv ret, TCGv arg1)
     tcg_gen_ctpop_tl(ret, arg1);
 }
 
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_ext16u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 16);
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_shri_tl(lower, arg1, 16);
+    tcg_gen_shri_tl(higher, arg2, 16);
+    tcg_gen_shli_tl(higher, higher, 16);
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 05/15] target/riscv: rvb: pack two words into one register

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 +
 target/riscv/insn32.decode              |  3 +
 target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++
 target/riscv/translate.c                | 92 +++++++++++++++++++++++++
 4 files changed, 128 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index d5bea5af273..2f00f96e36b 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -91,3 +91,6 @@ hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 clzw       011000000000 ..... 001 ..... 0011011 @r2
 ctzw       011000000001 ..... 001 ..... 0011011 @r2
 pcntw      011000000010 ..... 001 ..... 0011011 @r2
+
+packw      0000100 .......... 100 ..... 0111011 @r
+packuw     0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 29a3d4c6ebc..79aa40f03dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,3 +602,6 @@ pcnt       011000000010 ..... 001 ..... 0010011 @r2
 andn       0100000 .......... 111 ..... 0110011 @r
 orn        0100000 .......... 110 ..... 0110011 @r
 xnor       0100000 .......... 100 ..... 0110011 @r
+pack       0000100 .......... 100 ..... 0110011 @r
+packu      0100100 .......... 100 ..... 0110011 @r
+packh      0000100 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index be25431e990..9257373ae0b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
     return gen_arith(ctx, a, &gen_xnor);
 }
 
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packh);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -74,4 +92,16 @@ static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
     return gen_unary(ctx, a, &gen_pcntw);
 }
 
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_packuw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 254a9dca8c2..fb30ee83aa8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -743,6 +743,65 @@ static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+#ifdef TARGET_RISCV64
+    tcg_gen_ext32u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 32);
+#else
+    tcg_gen_ext16u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 16);
+#endif
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+#ifdef TARGET_RISCV64
+    tcg_gen_shri_tl(lower, arg1, 32);
+    tcg_gen_shri_tl(higher, arg2, 32);
+    tcg_gen_shli_tl(higher, higher, 32);
+#else
+    tcg_gen_shri_tl(lower, arg1, 16);
+    tcg_gen_shri_tl(higher, arg2, 16);
+    tcg_gen_shli_tl(higher, higher, 16);
+#endif
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_ext8u_tl(lower, arg1);
+    tcg_gen_ext8u_tl(higher, arg2);
+    tcg_gen_shli_tl(higher, higher, 8);
+
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+
 #ifdef TARGET_RISCV64
 
 static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
@@ -775,6 +834,39 @@ static void gen_pcntw(TCGv ret, TCGv arg1)
     tcg_gen_ctpop_tl(ret, arg1);
 }
 
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_ext16u_tl(lower, arg1);
+    tcg_gen_shli_tl(higher, arg2, 16);
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv lower, higher;
+    lower = tcg_temp_new();
+    higher = tcg_temp_new();
+
+    tcg_gen_shri_tl(lower, arg1, 16);
+    tcg_gen_shri_tl(higher, arg2, 16);
+    tcg_gen_shli_tl(higher, higher, 16);
+    tcg_gen_or_tl(ret, higher, lower);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(lower);
+    tcg_temp_free(higher);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 05/15] target/riscv: rvb: pack two words into one register

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> +    tcg_gen_ext32u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 32);
> +#else
> +    tcg_gen_ext16u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 16);
> +#endif
> +

tcg_gen_deposit(ret, arg1, arg2,
                TARGET_LONG_BITS / 2,
                TARGET_LONG_BITS / 2);

> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> +    tcg_gen_shri_tl(lower, arg1, 32);
> +    tcg_gen_shri_tl(higher, arg2, 32);
> +    tcg_gen_shli_tl(higher, higher, 32);
> +#else
> +    tcg_gen_shri_tl(lower, arg1, 16);
> +    tcg_gen_shri_tl(higher, arg2, 16);
> +    tcg_gen_shli_tl(higher, higher, 16);
> +#endif
> +
> +    tcg_gen_or_tl(ret, higher, lower);

tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);

> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_ext8u_tl(lower, arg1);
> +    tcg_gen_ext8u_tl(higher, arg2);
> +    tcg_gen_shli_tl(higher, higher, 8);
> +
> +    tcg_gen_or_tl(ret, higher, lower);

tcg_gen_ext8u_tl(t, arg2);
tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);

> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_ext16u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 16);
> +    tcg_gen_or_tl(ret, higher, lower);
> +
> +    tcg_gen_ext32s_tl(ret, ret);
> +
> +    tcg_temp_free(lower);
> +    tcg_temp_free(higher);
> +}

tcg_gen_ext16s_i64(t, arg2);
tcg_gen_deposit_i64(ret, arg1, t, 16, 48);

> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_shri_tl(lower, arg1, 16);
> +    tcg_gen_shri_tl(higher, arg2, 16);
> +    tcg_gen_shli_tl(higher, higher, 16);
> +    tcg_gen_or_tl(ret, higher, lower);
> +
> +    tcg_gen_ext32s_tl(ret, ret);

tcg_gen_shri_i64(t, arg1, 16);
tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
tcg_gen_ext32s_i64(ret, ret);


r~

Re: [RFC 05/15] target/riscv: rvb: pack two words into one register

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> +    tcg_gen_ext32u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 32);
> +#else
> +    tcg_gen_ext16u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 16);
> +#endif
> +

tcg_gen_deposit(ret, arg1, arg2,
                TARGET_LONG_BITS / 2,
                TARGET_LONG_BITS / 2);

> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +#ifdef TARGET_RISCV64
> +    tcg_gen_shri_tl(lower, arg1, 32);
> +    tcg_gen_shri_tl(higher, arg2, 32);
> +    tcg_gen_shli_tl(higher, higher, 32);
> +#else
> +    tcg_gen_shri_tl(lower, arg1, 16);
> +    tcg_gen_shri_tl(higher, arg2, 16);
> +    tcg_gen_shli_tl(higher, higher, 16);
> +#endif
> +
> +    tcg_gen_or_tl(ret, higher, lower);

tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);

> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_ext8u_tl(lower, arg1);
> +    tcg_gen_ext8u_tl(higher, arg2);
> +    tcg_gen_shli_tl(higher, higher, 8);
> +
> +    tcg_gen_or_tl(ret, higher, lower);

tcg_gen_ext8u_tl(t, arg2);
tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);

> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_ext16u_tl(lower, arg1);
> +    tcg_gen_shli_tl(higher, arg2, 16);
> +    tcg_gen_or_tl(ret, higher, lower);
> +
> +    tcg_gen_ext32s_tl(ret, ret);
> +
> +    tcg_temp_free(lower);
> +    tcg_temp_free(higher);
> +}

tcg_gen_ext16s_i64(t, arg2);
tcg_gen_deposit_i64(ret, arg1, t, 16, 48);

> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv lower, higher;
> +    lower = tcg_temp_new();
> +    higher = tcg_temp_new();
> +
> +    tcg_gen_shri_tl(lower, arg1, 16);
> +    tcg_gen_shri_tl(higher, arg2, 16);
> +    tcg_gen_shli_tl(higher, higher, 16);
> +    tcg_gen_or_tl(ret, higher, lower);
> +
> +    tcg_gen_ext32s_tl(ret, ret);

tcg_gen_shri_i64(t, arg1, 16);
tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
tcg_gen_ext32s_i64(ret, ret);


r~

[RFC 06/15] target/riscv: rvb: min/max instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  4 ++++
 target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 79aa40f03dd..372476f1d2c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -605,3 +605,7 @@ xnor       0100000 .......... 100 ..... 0110011 @r
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
+min        0000101 .......... 100 ..... 0110011 @r
+minu       0000101 .......... 101 ..... 0110011 @r
+max        0000101 .......... 110 ..... 0110011 @r
+maxu       0000101 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9257373ae0b..b9a0e39a3e5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
     return gen_arith(ctx, a, &gen_packh);
 }
 
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_umax_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
-- 
2.17.1

[RFC 06/15] target/riscv: rvb: min/max instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  4 ++++
 target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 79aa40f03dd..372476f1d2c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -605,3 +605,7 @@ xnor       0100000 .......... 100 ..... 0110011 @r
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
+min        0000101 .......... 100 ..... 0110011 @r
+minu       0000101 .......... 101 ..... 0110011 @r
+max        0000101 .......... 110 ..... 0110011 @r
+maxu       0000101 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9257373ae0b..b9a0e39a3e5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
     return gen_arith(ctx, a, &gen_packh);
 }
 
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_umax_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
-- 
2.17.1

Re: [RFC 06/15] target/riscv: rvb: min/max instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32.decode              |  4 ++++
>  target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC 06/15] target/riscv: rvb: min/max instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32.decode              |  4 ++++
>  target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC 07/15] target/riscv: rvb: sign-extend instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  2 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 372476f1d2c..626641333c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,6 +598,8 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
 pcnt       011000000010 ..... 001 ..... 0010011 @r2
+sext_b     011000000100 ..... 001 ..... 0010011 @r2
+sext_h     011000000101 ..... 001 ..... 0010011 @r2
 
 andn       0100000 .......... 111 ..... 0110011 @r
 orn        0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b9a0e39a3e5..bf15611f85a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,19 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
     return gen_arith(ctx, a, &tcg_gen_umax_tl);
 }
 
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
+}
+
+{
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
-- 
2.17.1

[RFC 07/15] target/riscv: rvb: sign-extend instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32.decode              |  2 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 372476f1d2c..626641333c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,6 +598,8 @@ vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
 clz        011000000000 ..... 001 ..... 0010011 @r2
 ctz        011000000001 ..... 001 ..... 0010011 @r2
 pcnt       011000000010 ..... 001 ..... 0010011 @r2
+sext_b     011000000100 ..... 001 ..... 0010011 @r2
+sext_h     011000000101 ..... 001 ..... 0010011 @r2
 
 andn       0100000 .......... 111 ..... 0110011 @r
 orn        0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b9a0e39a3e5..bf15611f85a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,19 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
     return gen_arith(ctx, a, &tcg_gen_umax_tl);
 }
 
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
+}
+
+{
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
-- 
2.17.1

Re: [RFC 07/15] target/riscv: rvb: sign-extend instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32.decode              |  2 ++
>  target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
>  2 files changed, 15 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC 07/15] target/riscv: rvb: sign-extend instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  target/riscv/insn32.decode              |  2 ++
>  target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
>  2 files changed, 15 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC 08/15] target/riscv: rvb: single-bit instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |   8 ++
 target/riscv/insn32.decode              |   9 ++
 target/riscv/insn_trans/trans_rvb.c.inc |  90 ++++++++++++++
 target/riscv/translate.c                | 155 ++++++++++++++++++++++++
 4 files changed, 262 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 2f00f96e36b..92f3aaac3b6 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -94,3 +94,11 @@ pcntw      011000000010 ..... 001 ..... 0011011 @r2
 
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
+sbsetw     0010100 .......... 001 ..... 0111011 @r
+sbclrw     0100100 .......... 001 ..... 0111011 @r
+sbinvw     0110100 .......... 001 ..... 0111011 @r
+sbextw     0100100 .......... 101 ..... 0111011 @r
+
+sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
+sbclriw    0100100 .......... 001 ..... 0011011 @sh5
+sbinviw    0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 626641333c6..69e542da19c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -611,3 +611,12 @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 max        0000101 .......... 110 ..... 0110011 @r
 maxu       0000101 .......... 111 ..... 0110011 @r
+sbset      0010100 .......... 001 ..... 0110011 @r
+sbclr      0100100 .......... 001 ..... 0110011 @r
+sbinv      0110100 .......... 001 ..... 0110011 @r
+sbext      0100100 .......... 101 ..... 0110011 @r
+
+sbseti     001010 ........... 001 ..... 0010011 @sh
+sbclri     010010 ........... 001 ..... 0010011 @sh
+sbinvi     011010 ........... 001 ..... 0010011 @sh
+sbexti     010010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index bf15611f85a..dabf8e09c3d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
     return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
 }
 
+static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbext(DisasContext *ctx, arg_sbext *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbext);
+}
+
+static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbext);
+}
+
 {
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
@@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
     return gen_arith(ctx, a, &gen_packuw);
 }
 
+static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbsetw);
+}
+
+static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbsetw);
+}
+
+static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbclrw);
+}
+
+static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbclrw);
+}
+
+static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbinvw);
+}
+
+static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbinvw);
+}
+
+static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbextw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb30ee83aa8..e7d9e4a1abf 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -647,6 +647,24 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
     return true;
 }
 
+static bool gen_arith_shamt_tl(DisasContext *ctx, arg_shift *a,
+                               void (*func)(TCGv, TCGv, TCGv))
+{
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+    source2 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+    tcg_gen_movi_tl(source2, a->shamt);
+
+    (*func)(source1, source1, source2);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+    return true;
+}
+
 #ifdef TARGET_RISCV64
 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 {
@@ -801,6 +819,74 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(higher);
 }
 
+static void gen_sbop_shamt(TCGv ret, TCGv shamt)
+{
+    tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1);
+}
+
+static void gen_sbop_common(TCGv ret, TCGv shamt)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(ret, shamt);
+
+    tcg_gen_movi_tl(t, 1);
+    tcg_gen_shl_tl(ret, t, ret);
+
+    tcg_temp_free(t);
+}
+
+static void gen_sbset(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_or_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbclr(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_not_tl(mask, mask);
+    tcg_gen_and_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbinv(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_xor_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    tcg_gen_shr_tl(ret, arg1, shamt);
+
+    tcg_gen_andi_tl(ret, ret, 1);
+
+    tcg_temp_free(shamt);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -867,6 +953,75 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(higher);
 }
 
+static void gen_sbopw_shamt(TCGv ret, TCGv shamt)
+{
+    tcg_gen_andi_tl(ret, shamt, 31);
+}
+
+static void gen_sbopw_common(TCGv ret, TCGv shamt)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    gen_sbopw_shamt(ret, shamt);
+    tcg_gen_movi_tl(t, 1);
+    tcg_gen_shl_tl(ret, t, ret);
+
+    tcg_temp_free(t);
+}
+
+static void gen_sbsetw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_or_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbclrw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_not_tl(mask, mask);
+    tcg_gen_and_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbinvw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_xor_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_shr_tl(ret, arg1, shamt);
+    tcg_gen_andi_tl(ret, ret, 1);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 08/15] target/riscv: rvb: single-bit instructions

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |   8 ++
 target/riscv/insn32.decode              |   9 ++
 target/riscv/insn_trans/trans_rvb.c.inc |  90 ++++++++++++++
 target/riscv/translate.c                | 155 ++++++++++++++++++++++++
 4 files changed, 262 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 2f00f96e36b..92f3aaac3b6 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -94,3 +94,11 @@ pcntw      011000000010 ..... 001 ..... 0011011 @r2
 
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
+sbsetw     0010100 .......... 001 ..... 0111011 @r
+sbclrw     0100100 .......... 001 ..... 0111011 @r
+sbinvw     0110100 .......... 001 ..... 0111011 @r
+sbextw     0100100 .......... 101 ..... 0111011 @r
+
+sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
+sbclriw    0100100 .......... 001 ..... 0011011 @sh5
+sbinviw    0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 626641333c6..69e542da19c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -611,3 +611,12 @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 max        0000101 .......... 110 ..... 0110011 @r
 maxu       0000101 .......... 111 ..... 0110011 @r
+sbset      0010100 .......... 001 ..... 0110011 @r
+sbclr      0100100 .......... 001 ..... 0110011 @r
+sbinv      0110100 .......... 001 ..... 0110011 @r
+sbext      0100100 .......... 101 ..... 0110011 @r
+
+sbseti     001010 ........... 001 ..... 0010011 @sh
+sbclri     010010 ........... 001 ..... 0010011 @sh
+sbinvi     011010 ........... 001 ..... 0010011 @sh
+sbexti     010010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index bf15611f85a..dabf8e09c3d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
     return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
 }
 
+static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbext(DisasContext *ctx, arg_sbext *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbext);
+}
+
+static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbext);
+}
+
 {
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
@@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
     return gen_arith(ctx, a, &gen_packuw);
 }
 
+static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbsetw);
+}
+
+static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbsetw);
+}
+
+static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbclrw);
+}
+
+static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbclrw);
+}
+
+static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbinvw);
+}
+
+static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_sbinvw);
+}
+
+static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sbextw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb30ee83aa8..e7d9e4a1abf 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -647,6 +647,24 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
     return true;
 }
 
+static bool gen_arith_shamt_tl(DisasContext *ctx, arg_shift *a,
+                               void (*func)(TCGv, TCGv, TCGv))
+{
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+    source2 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+    tcg_gen_movi_tl(source2, a->shamt);
+
+    (*func)(source1, source1, source2);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    tcg_temp_free(source2);
+    return true;
+}
+
 #ifdef TARGET_RISCV64
 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
 {
@@ -801,6 +819,74 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(higher);
 }
 
+static void gen_sbop_shamt(TCGv ret, TCGv shamt)
+{
+    tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1);
+}
+
+static void gen_sbop_common(TCGv ret, TCGv shamt)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(ret, shamt);
+
+    tcg_gen_movi_tl(t, 1);
+    tcg_gen_shl_tl(ret, t, ret);
+
+    tcg_temp_free(t);
+}
+
+static void gen_sbset(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_or_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbclr(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_not_tl(mask, mask);
+    tcg_gen_and_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbinv(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbop_common(mask, arg2);
+
+    tcg_gen_xor_tl(ret, arg1, mask);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    tcg_gen_shr_tl(ret, arg1, shamt);
+
+    tcg_gen_andi_tl(ret, ret, 1);
+
+    tcg_temp_free(shamt);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -867,6 +953,75 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(higher);
 }
 
+static void gen_sbopw_shamt(TCGv ret, TCGv shamt)
+{
+    tcg_gen_andi_tl(ret, shamt, 31);
+}
+
+static void gen_sbopw_common(TCGv ret, TCGv shamt)
+{
+    TCGv t;
+    t = tcg_temp_new();
+
+    gen_sbopw_shamt(ret, shamt);
+    tcg_gen_movi_tl(t, 1);
+    tcg_gen_shl_tl(ret, t, ret);
+
+    tcg_temp_free(t);
+}
+
+static void gen_sbsetw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_or_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbclrw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_not_tl(mask, mask);
+    tcg_gen_and_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbinvw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv mask;
+    mask = tcg_temp_new();
+
+    gen_sbopw_common(mask, arg2);
+    tcg_gen_xor_tl(ret, arg1, mask);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(mask);
+}
+
+static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_shr_tl(ret, arg1, shamt);
+    tcg_gen_andi_tl(ret, ret, 1);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_sbop_shamt(TCGv ret, TCGv shamt)
> +{
> +    tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1);
> +}
> +
> +static void gen_sbop_common(TCGv ret, TCGv shamt)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();

All of the places where you declare then initialize on the next line, please
merge them:

   TCGv t = tcg_temp_new();

It would be nice to share more code between the normal and *w versions.  As it
is, there's a *lot* of repetition with only TARGET_LONG_BITS vs 32 separating them.

> +    tcg_gen_not_tl(mask, mask);
> +    tcg_gen_and_tl(ret, arg1, mask);

andc.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_sbop_shamt(TCGv ret, TCGv shamt)
> +{
> +    tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1);
> +}
> +
> +static void gen_sbop_common(TCGv ret, TCGv shamt)
> +{
> +    TCGv t;
> +    t = tcg_temp_new();

All of the places where you declare then initialize on the next line, please
merge them:

   TCGv t = tcg_temp_new();

It would be nice to share more code between the normal and *w versions.  As it
is, there's a *lot* of repetition with only TARGET_LONG_BITS vs 32 separating them.

> +    tcg_gen_not_tl(mask, mask);
> +    tcg_gen_and_tl(ret, arg1, mask);

andc.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbset);
> +}
> +
> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
> +}
> +
> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbclr);
> +}

Coming back to my re-use of code thing, these should use gen_shift.  That
handles the truncate of source2 to the shift amount.

> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
> +}
> +
> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbinv);
> +}
> +
> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
> +}

I think there ought to be a gen_shifti for these.

Similarly gen_shiftiw and gen_shiftw, which would truncate and sign-extend the
result.  Existing code in trans_rvi.c.inc should be converted to use the new
functions.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbset);
> +}
> +
> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
> +}
> +
> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbclr);
> +}

Coming back to my re-use of code thing, these should use gen_shift.  That
handles the truncate of source2 to the shift amount.

> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
> +}
> +
> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sbinv);
> +}
> +
> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
> +}

I think there ought to be a gen_shifti for these.

Similarly gen_shiftiw and gen_shiftw, which would truncate and sign-extend the
result.  Existing code in trans_rvi.c.inc should be converted to use the new
functions.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/19/20 12:35 PM, Richard Henderson wrote:
> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
>> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbclr);
>> +}
> 
> Coming back to my re-use of code thing, these should use gen_shift.  That
> handles the truncate of source2 to the shift amount.
> 
>> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
>> +}
>> +
>> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbinv);
>> +}
>> +
>> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
>> +}
> 
> I think there ought to be a gen_shifti for these.

Hmm.  I just realized that gen_shifti would have a generator callback with a
constant argument, a-la tcg_gen_shli_tl.

I don't know if it's worth duplicating gen_sbclr et al for a constant argument.
 And the sloi/sroi insns besides.  Perhaps a gen_shifti_var helper instead?

Let me know what you think, but at the moment we're left with an incoherent set
of helpers that seem split along lines that are less than ideal.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Richard Henderson]

On 11/19/20 12:35 PM, Richard Henderson wrote:
> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
>> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbclr);
>> +}
> 
> Coming back to my re-use of code thing, these should use gen_shift.  That
> handles the truncate of source2 to the shift amount.
> 
>> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
>> +}
>> +
>> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith(ctx, a, &gen_sbinv);
>> +}
>> +
>> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
>> +{
>> +    REQUIRE_EXT(ctx, RVB);
>> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
>> +}
> 
> I think there ought to be a gen_shifti for these.

Hmm.  I just realized that gen_shifti would have a generator callback with a
constant argument, a-la tcg_gen_shli_tl.

I don't know if it's worth duplicating gen_sbclr et al for a constant argument.
 And the sloi/sroi insns besides.  Perhaps a gen_shifti_var helper instead?

Let me know what you think, but at the moment we're left with an incoherent set
of helpers that seem split along lines that are less than ideal.


r~

Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Frank Chang]

[-- Attachment #1: Type: text/plain, Size: 5214 bytes --]

On Fri, Nov 20, 2020 at 5:04 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 11/19/20 12:35 PM, Richard Henderson wrote:
> > On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> >> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbset);
> >> +}
> >> +
> >> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
> >> +}
> >> +
> >> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbclr);
> >> +}
> >
> > Coming back to my re-use of code thing, these should use gen_shift.  That
> > handles the truncate of source2 to the shift amount.
> >
> >> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
> >> +}
> >> +
> >> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbinv);
> >> +}
> >> +
> >> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
> >> +}
> >
> > I think there ought to be a gen_shifti for these.
>
> Hmm.  I just realized that gen_shifti would have a generator callback with
> a
> constant argument, a-la tcg_gen_shli_tl.
>
> I don't know if it's worth duplicating gen_sbclr et al for a constant
> argument.
>  And the sloi/sroi insns besides.  Perhaps a gen_shifti_var helper instead?
>
> Let me know what you think, but at the moment we're left with an
> incoherent set
> of helpers that seem split along lines that are less than ideal.
>
>
> r~
>

Thanks Richard and sorry for the late reply.....

If we can have gen_shift(), gen_shifti(), gen_shiftw() and gen_shiftiw(),
then we can eliminate the needs of:
gen_arith_shamt_tl(), gen_sbop_shamt(), gen_sbopw_shamt()
and gen_sbopw_common()
and most of the *w version generators can be removed, too.

For *w version, we just need to call gen_shiftw() or gen_shiftiw()
with the reused non-*w version generator.
For example:

  static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_shiftw(ctx, a, &gen_sbclr);
  }

  static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_shiftiw(ctx, a, &gen_sbclr);
  }

both of which can reuse gen_sbclr() generator:

  static void gen_sbclr(TCGv ret, TCGv arg1, TCGv shamt)
  {
      TCGv t = tcg_temp_new();
      tcg_gen_movi_tl(t, 1);
      tcg_gen_shl_tl(t, t, shamt);
      tcg_gen_andc_tl(ret, arg1, t);
      tcg_temp_free(t);
  }

The gen_shift*() I have now are as follow:

  static bool gen_shift(DisasContext *ctx, arg_r *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

      gen_get_gpr(source1, a->rs1);
      gen_get_gpr(source2, a->rs2);

      tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
      (*func)(source1, source1, source2);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shifti(DisasContext *ctx, arg_shift *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

     gen_get_gpr(source1, a->rs1);
     tcg_gen_movi_tl(source2, a->shamt);

      tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
      (*func)(source1, source1, source2);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shiftw(DisasContext *ctx, arg_r *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

      gen_get_gpr(source1, a->rs1);
      gen_get_gpr(source2, a->rs2);

      tcg_gen_andi_tl(source2, source2, 31);
      (*func)(source1, source1, source2);
      tcg_gen_ext32s_tl(source1, source1);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

     gen_get_gpr(source1, a->rs1);
     tcg_gen_movi_tl(source2, a->shamt);

     tcg_gen_andi_tl(source2, source2, 31);
     (*func)(source1, source1, source2);
     tcg_gen_ext32s_tl(source1, source1);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

They may be further merged as most of them are duplicate with only the
differences of:
gen_get_gpr(source2, a->rs2); vs. tcg_gen_movi_tl(source2, a->shamt);
TARGET_LONG_BITS - 1 vs. 31, and
tcg_gen_ext32s_tl(); to sign-extend the 32-bit return value for *w
instructions

Any thoughts?

Frank Chang

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Re: [RFC 08/15] target/riscv: rvb: single-bit instructions

[Frank Chang]

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On Fri, Nov 20, 2020 at 5:04 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 11/19/20 12:35 PM, Richard Henderson wrote:
> > On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> >> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbset);
> >> +}
> >> +
> >> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbset);
> >> +}
> >> +
> >> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbclr);
> >> +}
> >
> > Coming back to my re-use of code thing, these should use gen_shift.  That
> > handles the truncate of source2 to the shift amount.
> >
> >> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
> >> +}
> >> +
> >> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith(ctx, a, &gen_sbinv);
> >> +}
> >> +
> >> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
> >> +{
> >> +    REQUIRE_EXT(ctx, RVB);
> >> +    return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
> >> +}
> >
> > I think there ought to be a gen_shifti for these.
>
> Hmm.  I just realized that gen_shifti would have a generator callback with
> a
> constant argument, a-la tcg_gen_shli_tl.
>
> I don't know if it's worth duplicating gen_sbclr et al for a constant
> argument.
>  And the sloi/sroi insns besides.  Perhaps a gen_shifti_var helper instead?
>
> Let me know what you think, but at the moment we're left with an
> incoherent set
> of helpers that seem split along lines that are less than ideal.
>
>
> r~
>

Thanks Richard and sorry for the late reply.....

If we can have gen_shift(), gen_shifti(), gen_shiftw() and gen_shiftiw(),
then we can eliminate the needs of:
gen_arith_shamt_tl(), gen_sbop_shamt(), gen_sbopw_shamt()
and gen_sbopw_common()
and most of the *w version generators can be removed, too.

For *w version, we just need to call gen_shiftw() or gen_shiftiw()
with the reused non-*w version generator.
For example:

  static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_shiftw(ctx, a, &gen_sbclr);
  }

  static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_shiftiw(ctx, a, &gen_sbclr);
  }

both of which can reuse gen_sbclr() generator:

  static void gen_sbclr(TCGv ret, TCGv arg1, TCGv shamt)
  {
      TCGv t = tcg_temp_new();
      tcg_gen_movi_tl(t, 1);
      tcg_gen_shl_tl(t, t, shamt);
      tcg_gen_andc_tl(ret, arg1, t);
      tcg_temp_free(t);
  }

The gen_shift*() I have now are as follow:

  static bool gen_shift(DisasContext *ctx, arg_r *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

      gen_get_gpr(source1, a->rs1);
      gen_get_gpr(source2, a->rs2);

      tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
      (*func)(source1, source1, source2);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shifti(DisasContext *ctx, arg_shift *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

     gen_get_gpr(source1, a->rs1);
     tcg_gen_movi_tl(source2, a->shamt);

      tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
      (*func)(source1, source1, source2);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shiftw(DisasContext *ctx, arg_r *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

      gen_get_gpr(source1, a->rs1);
      gen_get_gpr(source2, a->rs2);

      tcg_gen_andi_tl(source2, source2, 31);
      (*func)(source1, source1, source2);
      tcg_gen_ext32s_tl(source1, source1);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

  static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
                          void(*func)(TCGv, TCGv, TCGv))
  {
      TCGv source1 = tcg_temp_new();
      TCGv source2 = tcg_temp_new();

     gen_get_gpr(source1, a->rs1);
     tcg_gen_movi_tl(source2, a->shamt);

     tcg_gen_andi_tl(source2, source2, 31);
     (*func)(source1, source1, source2);
     tcg_gen_ext32s_tl(source1, source1);

      gen_set_gpr(a->rd, source1);
      tcg_temp_free(source1);
      tcg_temp_free(source2);
      return true;
  }

They may be further merged as most of them are duplicate with only the
differences of:
gen_get_gpr(source2, a->rs2); vs. tcg_gen_movi_tl(source2, a->shamt);
TARGET_LONG_BITS - 1 vs. 31, and
tcg_gen_ext32s_tl(); to sign-extend the 32-bit return value for *w
instructions

Any thoughts?

Frank Chang

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[RFC 09/15] target/riscv: rvb: shift ones

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  4 ++
 target/riscv/insn32.decode              |  4 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 58 ++++++++++++++++++++
 target/riscv/translate.c                | 70 +++++++++++++++++++++++++
 4 files changed, 136 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 92f3aaac3b6..cc6b7d63774 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -98,7 +98,11 @@ sbsetw     0010100 .......... 001 ..... 0111011 @r
 sbclrw     0100100 .......... 001 ..... 0111011 @r
 sbinvw     0110100 .......... 001 ..... 0111011 @r
 sbextw     0100100 .......... 101 ..... 0111011 @r
+slow       0010000 .......... 001 ..... 0111011 @r
+srow       0010000 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
 sbinviw    0110100 .......... 001 ..... 0011011 @sh5
+sloiw      0010000 .......... 001 ..... 0011011 @sh5
+sroiw      0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 69e542da19c..6e3eef84144 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -615,8 +615,12 @@ sbset      0010100 .......... 001 ..... 0110011 @r
 sbclr      0100100 .......... 001 ..... 0110011 @r
 sbinv      0110100 .......... 001 ..... 0110011 @r
 sbext      0100100 .......... 101 ..... 0110011 @r
+slo        0010000 .......... 001 ..... 0110011 @r
+sro        0010000 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
 sbinvi     011010 ........... 001 ..... 0010011 @sh
 sbexti     010010 ........... 101 ..... 0010011 @sh
+sloi       001000 ........... 001 ..... 0010011 @sh
+sroi       001000 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index dabf8e09c3d..4c93c5aab8b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
     return gen_arith_shamt_tl(ctx, a, &gen_sbext);
 }
 
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_sro);
+}
+
 {
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
@@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
     return gen_arith(ctx, a, &gen_sbextw);
 }
 
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_slow);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_slow);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_srow);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_srow);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e7d9e4a1abf..8972e247bd7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -887,6 +887,38 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shl_tl(t, t, arg2);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shr_tl(t, t, arg2);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1022,6 +1054,44 @@ static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_slow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shl_tl(t, t, shamt);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
+static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shr_tl(t, t, shamt);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 09/15] target/riscv: rvb: shift ones

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  4 ++
 target/riscv/insn32.decode              |  4 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 58 ++++++++++++++++++++
 target/riscv/translate.c                | 70 +++++++++++++++++++++++++
 4 files changed, 136 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 92f3aaac3b6..cc6b7d63774 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -98,7 +98,11 @@ sbsetw     0010100 .......... 001 ..... 0111011 @r
 sbclrw     0100100 .......... 001 ..... 0111011 @r
 sbinvw     0110100 .......... 001 ..... 0111011 @r
 sbextw     0100100 .......... 101 ..... 0111011 @r
+slow       0010000 .......... 001 ..... 0111011 @r
+srow       0010000 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
 sbinviw    0110100 .......... 001 ..... 0011011 @sh5
+sloiw      0010000 .......... 001 ..... 0011011 @sh5
+sroiw      0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 69e542da19c..6e3eef84144 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -615,8 +615,12 @@ sbset      0010100 .......... 001 ..... 0110011 @r
 sbclr      0100100 .......... 001 ..... 0110011 @r
 sbinv      0110100 .......... 001 ..... 0110011 @r
 sbext      0100100 .......... 101 ..... 0110011 @r
+slo        0010000 .......... 001 ..... 0110011 @r
+sro        0010000 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
 sbinvi     011010 ........... 001 ..... 0010011 @sh
 sbexti     010010 ........... 101 ..... 0010011 @sh
+sloi       001000 ........... 001 ..... 0010011 @sh
+sroi       001000 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index dabf8e09c3d..4c93c5aab8b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
     return gen_arith_shamt_tl(ctx, a, &gen_sbext);
 }
 
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_sro);
+}
+
 {
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
@@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
     return gen_arith(ctx, a, &gen_sbextw);
 }
 
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_slow);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_slow);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_srow);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_shamt_tl(ctx, a, &gen_srow);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e7d9e4a1abf..8972e247bd7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -887,6 +887,38 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shl_tl(t, t, arg2);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shr_tl(t, t, arg2);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1022,6 +1054,44 @@ static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_slow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shl_tl(t, t, shamt);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
+static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt, t;
+    shamt = tcg_temp_new();
+    t = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    tcg_gen_not_tl(t, arg1);
+    tcg_gen_shr_tl(t, t, shamt);
+    tcg_gen_not_tl(ret, t);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free(t);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 09/15] target/riscv: rvb: shift ones

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_slo(DisasContext *ctx, arg_slo *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sro(DisasContext *ctx, arg_sro *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sro);
> +}
> +
> +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &gen_sro);
> +}

Use the same gen_shift family of functions discussed vs patch 8.


r~

Re: [RFC 09/15] target/riscv: rvb: shift ones

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_slo(DisasContext *ctx, arg_slo *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &gen_slo);
> +}
> +
> +static bool trans_sro(DisasContext *ctx, arg_sro *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_arith(ctx, a, &gen_sro);
> +}
> +
> +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &gen_sro);
> +}

Use the same gen_shift family of functions discussed vs patch 8.


r~

[RFC 10/15] target/riscv: rvb: rotate (left/right)

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 ++
 target/riscv/insn32.decode              |  3 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 54 +++++++++++++++++++++++++
 target/riscv/translate.c                | 48 ++++++++++++++++++++++
 4 files changed, 108 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index cc6b7d63774..a1a4b12f7ca 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -100,9 +100,12 @@ sbinvw     0110100 .......... 001 ..... 0111011 @r
 sbextw     0100100 .......... 101 ..... 0111011 @r
 slow       0010000 .......... 001 ..... 0111011 @r
 srow       0010000 .......... 101 ..... 0111011 @r
+rorw       0110000 .......... 101 ..... 0111011 @r
+rolw       0110000 .......... 001 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
 sbinviw    0110100 .......... 001 ..... 0011011 @sh5
 sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
+roriw      0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e3eef84144..01b8ebc4bee 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -617,6 +617,8 @@ sbinv      0110100 .......... 001 ..... 0110011 @r
 sbext      0100100 .......... 101 ..... 0110011 @r
 slo        0010000 .......... 001 ..... 0110011 @r
 sro        0010000 .......... 101 ..... 0110011 @r
+ror        0110000 .......... 101 ..... 0110011 @r
+rol        0110000 .......... 001 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -624,3 +626,4 @@ sbinvi     011010 ........... 001 ..... 0010011 @sh
 sbexti     010010 ........... 101 ..... 0010011 @sh
 sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
+rori       011000 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 4c93c5aab8b..ba8734203ac 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -189,7 +189,29 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
     return gen_arith_shamt_tl(ctx, a, &gen_sro);
 }
 
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_rotl_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -289,4 +311,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_srow);
 }
 
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    if (a->shamt == 0) {
+        TCGv t = tcg_temp_new();
+        gen_get_gpr(t, a->rs1);
+        tcg_gen_ext32s_tl(t, t);
+        gen_set_gpr(a->rd, t);
+        tcg_temp_free(t);
+        return true;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_rolw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8972e247bd7..68870bd9202 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1092,6 +1092,54 @@ static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    TCGv_i32 t1, t2;
+    shamt = tcg_temp_new();
+    t1 = tcg_temp_new_i32();
+    t2 = tcg_temp_new_i32();
+
+    gen_sbopw_shamt(shamt, arg2);
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, shamt);
+
+    tcg_gen_rotr_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    TCGv_i32 t1, t2;
+    shamt = tcg_temp_new();
+    t1 = tcg_temp_new_i32();
+    t2 = tcg_temp_new_i32();
+
+    gen_sbopw_shamt(shamt, arg2);
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, shamt);
+
+    tcg_gen_rotl_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 10/15] target/riscv: rvb: rotate (left/right)

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 ++
 target/riscv/insn32.decode              |  3 ++
 target/riscv/insn_trans/trans_rvb.c.inc | 54 +++++++++++++++++++++++++
 target/riscv/translate.c                | 48 ++++++++++++++++++++++
 4 files changed, 108 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index cc6b7d63774..a1a4b12f7ca 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -100,9 +100,12 @@ sbinvw     0110100 .......... 001 ..... 0111011 @r
 sbextw     0100100 .......... 101 ..... 0111011 @r
 slow       0010000 .......... 001 ..... 0111011 @r
 srow       0010000 .......... 101 ..... 0111011 @r
+rorw       0110000 .......... 101 ..... 0111011 @r
+rolw       0110000 .......... 001 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
 sbinviw    0110100 .......... 001 ..... 0011011 @sh5
 sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
+roriw      0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e3eef84144..01b8ebc4bee 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -617,6 +617,8 @@ sbinv      0110100 .......... 001 ..... 0110011 @r
 sbext      0100100 .......... 101 ..... 0110011 @r
 slo        0010000 .......... 001 ..... 0110011 @r
 sro        0010000 .......... 101 ..... 0110011 @r
+ror        0110000 .......... 101 ..... 0110011 @r
+rol        0110000 .......... 001 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -624,3 +626,4 @@ sbinvi     011010 ........... 001 ..... 0010011 @sh
 sbexti     010010 ........... 101 ..... 0010011 @sh
 sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
+rori       011000 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 4c93c5aab8b..ba8734203ac 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -189,7 +189,29 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
     return gen_arith_shamt_tl(ctx, a, &gen_sro);
 }
 
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &tcg_gen_rotl_tl);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -289,4 +311,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_srow);
 }
 
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    if (a->shamt == 0) {
+        TCGv t = tcg_temp_new();
+        gen_get_gpr(t, a->rs1);
+        tcg_gen_ext32s_tl(t, t);
+        gen_set_gpr(a->rd, t);
+        tcg_temp_free(t);
+        return true;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_rolw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8972e247bd7..68870bd9202 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1092,6 +1092,54 @@ static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    TCGv_i32 t1, t2;
+    shamt = tcg_temp_new();
+    t1 = tcg_temp_new_i32();
+    t2 = tcg_temp_new_i32();
+
+    gen_sbopw_shamt(shamt, arg2);
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, shamt);
+
+    tcg_gen_rotr_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    TCGv_i32 t1, t2;
+    shamt = tcg_temp_new();
+    t1 = tcg_temp_new_i32();
+    t2 = tcg_temp_new_i32();
+
+    gen_sbopw_shamt(shamt, arg2);
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, shamt);
+
+    tcg_gen_rotl_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free(shamt);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 10/15] target/riscv: rvb: rotate (left/right)

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &tcg_gen_rotr_tl);
> +}

We most definitely want to use tcg_gen_rotri_tl here, as we have special
expansions of constant shifts for hosts without rotate (e.g. riscv64g ;-).

Otherwise, this patch should be included in the shift cleanup discussed upthread.


r~

Re: [RFC 10/15] target/riscv: rvb: rotate (left/right)

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_arith_shamt_tl(ctx, a, &tcg_gen_rotr_tl);
> +}

We most definitely want to use tcg_gen_rotri_tl here, as we have special
expansions of constant shifts for hosts without rotate (e.g. riscv64g ;-).

Otherwise, this patch should be included in the shift cleanup discussed upthread.


r~

[RFC 11/15] target/riscv: rvb: generalized reverse

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/bitmanip_helper.c          | 79 +++++++++++++++++++++++++
 target/riscv/helper.h                   |  7 +++
 target/riscv/insn32-64.decode           |  2 +
 target/riscv/insn32.decode              |  2 +
 target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++
 target/riscv/meson.build                |  1 +
 target/riscv/translate.c                | 53 +++++++++++++++++
 7 files changed, 178 insertions(+)
 create mode 100644 target/riscv/bitmanip_helper.c

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..1d133db1552
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,79 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+
+static inline target_ulong do_swap(target_ulong x, target_ulong mask, int shift)
+{
+    return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+                            target_ulong rs2,
+                            const target_ulong masks[])
+{
+    target_ulong x = rs1;
+    int shift = 1;
+    int i = 0;
+
+    while (shift < TARGET_LONG_BITS) {
+        if (rs2 & shift) {
+            x = do_swap(x, masks[i], shift);
+        }
+        shift <<= 1;
+        ++i;
+    }
+
+    return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+#ifdef TARGET_RISCV32
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+#else
+        0x5555555555555555, 0x3333333333333333,
+        0x0f0f0f0f0f0f0f0f, 0x00ff00ff00ff00ff,
+        0x0000ffff0000ffff, 0x00000000ffffffff,
+#endif
+    };
+
+    return do_grev(rs1, rs2, masks);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+    };
+
+    return do_grev(rs1, rs2, masks);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 4b690147fb2..15243a00761 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,13 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 #endif
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
+#if defined(TARGET_RISCV64)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+#endif
+
 /* Special functions */
 DEF_HELPER_3(csrrw, tl, env, tl, tl)
 DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a1a4b12f7ca..f2d3b6a5b5d 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -102,6 +102,7 @@ slow       0010000 .......... 001 ..... 0111011 @r
 srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
+grevw      0110100 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -109,3 +110,4 @@ sbinviw    0110100 .......... 001 ..... 0011011 @sh5
 sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
+greviw     0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 01b8ebc4bee..60821a16661 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -619,6 +619,7 @@ slo        0010000 .......... 001 ..... 0110011 @r
 sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
+grev       0110100 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -627,3 +628,4 @@ sbexti     010010 ........... 101 ..... 0010011 @sh
 sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
 rori       011000 ........... 101 ..... 0010011 @sh
+grevi      011010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ba8734203ac..9f1482d313a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -212,6 +212,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_arith(ctx, a, &tcg_gen_rotl_tl);
 }
 
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_grevi(ctx, a);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -343,4 +360,21 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     return gen_arith(ctx, a, &gen_rolw);
 }
 
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_grevw);
+}
+
 #endif
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1c..df77cd24ada 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -21,6 +21,7 @@ riscv_ss.add(files(
   'gdbstub.c',
   'op_helper.c',
   'vector_helper.c',
+  'bitmanip_helper.c',
   'translate.c',
 ))
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 68870bd9202..80549154d6e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -919,6 +919,44 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_grev(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    gen_helper_grev(ret, arg1, shamt);
+
+    tcg_temp_free(shamt);
+}
+
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+
+    if (a->shamt == (TARGET_LONG_BITS - 8)) {
+        /* rev8, byte swaps */
+#ifdef TARGET_RISCV32
+        tcg_gen_bswap32_tl(source1, source1);
+#else
+        tcg_gen_bswap64_tl(source1, source1);
+#endif
+    } else {
+        source2 = tcg_temp_new();
+        tcg_gen_movi_tl(source2, a->shamt);
+        gen_helper_grev(source1, source1, source2);
+        tcg_temp_free(source2);
+    }
+
+    gen_set_gpr(a->rd, source1);
+
+    tcg_temp_free(source1);
+    return true;
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1140,6 +1178,21 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free_i32(t2);
 }
 
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    gen_helper_grev(ret, arg1, shamt);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 11/15] target/riscv: rvb: generalized reverse

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/bitmanip_helper.c          | 79 +++++++++++++++++++++++++
 target/riscv/helper.h                   |  7 +++
 target/riscv/insn32-64.decode           |  2 +
 target/riscv/insn32.decode              |  2 +
 target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++
 target/riscv/meson.build                |  1 +
 target/riscv/translate.c                | 53 +++++++++++++++++
 7 files changed, 178 insertions(+)
 create mode 100644 target/riscv/bitmanip_helper.c

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..1d133db1552
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,79 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+
+static inline target_ulong do_swap(target_ulong x, target_ulong mask, int shift)
+{
+    return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+                            target_ulong rs2,
+                            const target_ulong masks[])
+{
+    target_ulong x = rs1;
+    int shift = 1;
+    int i = 0;
+
+    while (shift < TARGET_LONG_BITS) {
+        if (rs2 & shift) {
+            x = do_swap(x, masks[i], shift);
+        }
+        shift <<= 1;
+        ++i;
+    }
+
+    return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+#ifdef TARGET_RISCV32
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+#else
+        0x5555555555555555, 0x3333333333333333,
+        0x0f0f0f0f0f0f0f0f, 0x00ff00ff00ff00ff,
+        0x0000ffff0000ffff, 0x00000000ffffffff,
+#endif
+    };
+
+    return do_grev(rs1, rs2, masks);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+    };
+
+    return do_grev(rs1, rs2, masks);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 4b690147fb2..15243a00761 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,13 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 #endif
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
+#if defined(TARGET_RISCV64)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+#endif
+
 /* Special functions */
 DEF_HELPER_3(csrrw, tl, env, tl, tl)
 DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a1a4b12f7ca..f2d3b6a5b5d 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -102,6 +102,7 @@ slow       0010000 .......... 001 ..... 0111011 @r
 srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
+grevw      0110100 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -109,3 +110,4 @@ sbinviw    0110100 .......... 001 ..... 0011011 @sh5
 sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
+greviw     0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 01b8ebc4bee..60821a16661 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -619,6 +619,7 @@ slo        0010000 .......... 001 ..... 0110011 @r
 sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
+grev       0110100 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -627,3 +628,4 @@ sbexti     010010 ........... 101 ..... 0010011 @sh
 sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
 rori       011000 ........... 101 ..... 0010011 @sh
+grevi      011010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ba8734203ac..9f1482d313a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -212,6 +212,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_arith(ctx, a, &tcg_gen_rotl_tl);
 }
 
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_grevi(ctx, a);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -343,4 +360,21 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     return gen_arith(ctx, a, &gen_rolw);
 }
 
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_grevw);
+}
+
 #endif
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1c..df77cd24ada 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -21,6 +21,7 @@ riscv_ss.add(files(
   'gdbstub.c',
   'op_helper.c',
   'vector_helper.c',
+  'bitmanip_helper.c',
   'translate.c',
 ))
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 68870bd9202..80549154d6e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -919,6 +919,44 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(t);
 }
 
+static void gen_grev(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    gen_helper_grev(ret, arg1, shamt);
+
+    tcg_temp_free(shamt);
+}
+
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    TCGv source1, source2;
+    source1 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+
+    if (a->shamt == (TARGET_LONG_BITS - 8)) {
+        /* rev8, byte swaps */
+#ifdef TARGET_RISCV32
+        tcg_gen_bswap32_tl(source1, source1);
+#else
+        tcg_gen_bswap64_tl(source1, source1);
+#endif
+    } else {
+        source2 = tcg_temp_new();
+        tcg_gen_movi_tl(source2, a->shamt);
+        gen_helper_grev(source1, source1, source2);
+        tcg_temp_free(source2);
+    }
+
+    gen_set_gpr(a->rd, source1);
+
+    tcg_temp_free(source1);
+    return true;
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1140,6 +1178,21 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free_i32(t2);
 }
 
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    gen_helper_grev(ret, arg1, shamt);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 11/15] target/riscv: rvb: generalized reverse

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static target_ulong do_grev(target_ulong rs1,
> +                            target_ulong rs2,
> +                            const target_ulong masks[])
> +{

I think the masks should be placed here, and not passed in.
What you should pass in is "int bits".


> +    target_ulong x = rs1;
> +    int shift = 1;
> +    int i = 0;
> +
> +    while (shift < TARGET_LONG_BITS) {
> +        if (rs2 & shift) {
> +            x = do_swap(x, masks[i], shift);
> +        }
> +        shift <<= 1;
> +        ++i;

Cleaner as for loop:

    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1)

> +    static const target_ulong masks[] = {
> +#ifdef TARGET_RISCV32
> +        0x55555555, 0x33333333, 0x0f0f0f0f,
> +        0x00ff00ff, 0x0000ffff,
> +#else
> +        0x5555555555555555, 0x3333333333333333,
> +        0x0f0f0f0f0f0f0f0f, 0x00ff00ff00ff00ff,
> +        0x0000ffff0000ffff, 0x00000000ffffffff,
> +#endif

You don't need to replicate every entry.

    dup_const(0x55, MO_8),
    dup_const(0x33, MO_8),
    dup_const(0x0f, MO_8),
    dup_const(0xff, MO_16),
    dup_const(0xffff, MO_32),
#ifdef TARGET_RISCV64
    UINT32_MAX
#endif

> +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
> +{
> +    static const target_ulong masks[] = {
> +        0x55555555, 0x33333333, 0x0f0f0f0f,
> +        0x00ff00ff, 0x0000ffff,
> +    };
> +
> +    return do_grev(rs1, rs2, masks);

This one is broken because do_grev iterated to TARGET_LONG_BITS == 64, and the
masks array is too small.

Fixed by passing in 32 as bits parameter to do_grev, as above.

> +static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_grevi(ctx, a);
> +}

While this is ok for an initial implementation, it is worth noticing the shamt
for rev8 as a special case for tcg_gen_bswap_tl.

Otherwise, this needs the same gen_shift treatment.


r~

Re: [RFC 11/15] target/riscv: rvb: generalized reverse

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static target_ulong do_grev(target_ulong rs1,
> +                            target_ulong rs2,
> +                            const target_ulong masks[])
> +{

I think the masks should be placed here, and not passed in.
What you should pass in is "int bits".


> +    target_ulong x = rs1;
> +    int shift = 1;
> +    int i = 0;
> +
> +    while (shift < TARGET_LONG_BITS) {
> +        if (rs2 & shift) {
> +            x = do_swap(x, masks[i], shift);
> +        }
> +        shift <<= 1;
> +        ++i;

Cleaner as for loop:

    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1)

> +    static const target_ulong masks[] = {
> +#ifdef TARGET_RISCV32
> +        0x55555555, 0x33333333, 0x0f0f0f0f,
> +        0x00ff00ff, 0x0000ffff,
> +#else
> +        0x5555555555555555, 0x3333333333333333,
> +        0x0f0f0f0f0f0f0f0f, 0x00ff00ff00ff00ff,
> +        0x0000ffff0000ffff, 0x00000000ffffffff,
> +#endif

You don't need to replicate every entry.

    dup_const(0x55, MO_8),
    dup_const(0x33, MO_8),
    dup_const(0x0f, MO_8),
    dup_const(0xff, MO_16),
    dup_const(0xffff, MO_32),
#ifdef TARGET_RISCV64
    UINT32_MAX
#endif

> +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
> +{
> +    static const target_ulong masks[] = {
> +        0x55555555, 0x33333333, 0x0f0f0f0f,
> +        0x00ff00ff, 0x0000ffff,
> +    };
> +
> +    return do_grev(rs1, rs2, masks);

This one is broken because do_grev iterated to TARGET_LONG_BITS == 64, and the
masks array is too small.

Fixed by passing in 32 as bits parameter to do_grev, as above.

> +static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +
> +    if (a->shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    return gen_grevi(ctx, a);
> +}

While this is ok for an initial implementation, it is worth noticing the shamt
for rev8 as a special case for tcg_gen_bswap_tl.

Otherwise, this needs the same gen_shift treatment.


r~

[RFC 12/15] target/riscv: rvb: generalized or-combine

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/bitmanip_helper.c          | 49 +++++++++++++++++++++++++
 target/riscv/helper.h                   |  2 +
 target/riscv/insn32-64.decode           |  2 +
 target/riscv/insn32.decode              |  2 +
 target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++++++++
 target/riscv/translate.c                | 26 +++++++++++++
 6 files changed, 115 insertions(+)

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 1d133db1552..83c4ac8e960 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -77,3 +77,52 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
 
 #endif
 
+static target_ulong do_gorc(target_ulong rs1,
+                            target_ulong rs2,
+                            const target_ulong masks[])
+{
+    target_ulong x = rs1;
+    int shift = 1;
+    int i = 0;
+
+    while (shift < TARGET_LONG_BITS) {
+        if (rs2 & shift) {
+            x |= do_swap(x, masks[i], shift);
+        }
+        shift <<= 1;
+        ++i;
+    }
+
+    return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+#ifdef TARGET_RISCV32
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+#else
+        0x5555555555555555, 0x3333333333333333, 0x0f0f0f0f0f0f0f0f,
+        0x00ff00ff00ff00ff, 0x0000ffff0000ffff, 0x00000000ffffffff,
+#endif
+    };
+
+    return do_gorc(rs1, rs2, masks);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+    };
+
+    return do_gorc(rs1, rs2, masks);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 15243a00761..8effa427b1a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,9 +68,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 #if defined(TARGET_RISCV64)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 #endif
 
 /* Special functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index f2d3b6a5b5d..8e6ec4750f3 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -103,6 +103,7 @@ srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
+gorcw      0010100 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -111,3 +112,4 @@ sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
+gorciw     0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 60821a16661..76ba0698511 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -620,6 +620,7 @@ sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
+gorc       0010100 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -629,3 +630,4 @@ sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
 rori       011000 ........... 101 ..... 0010011 @sh
 grevi      011010 ........... 101 ..... 0010011 @sh
+gorci      001010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9f1482d313a..eade85125c5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -229,6 +229,23 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
     return gen_grevi(ctx, a);
 }
 
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_gorc);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -377,4 +394,21 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_grevw);
 }
 
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_gorcw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 80549154d6e..566e60d0d20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -957,6 +957,17 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
     return true;
 }
 
+static void gen_gorc(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    gen_helper_gorc(ret, arg1, shamt);
+
+    tcg_temp_free(shamt);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1193,6 +1204,21 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    gen_helper_gorc(ret, arg1, shamt);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 12/15] target/riscv: rvb: generalized or-combine

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/bitmanip_helper.c          | 49 +++++++++++++++++++++++++
 target/riscv/helper.h                   |  2 +
 target/riscv/insn32-64.decode           |  2 +
 target/riscv/insn32.decode              |  2 +
 target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++++++++
 target/riscv/translate.c                | 26 +++++++++++++
 6 files changed, 115 insertions(+)

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 1d133db1552..83c4ac8e960 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -77,3 +77,52 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
 
 #endif
 
+static target_ulong do_gorc(target_ulong rs1,
+                            target_ulong rs2,
+                            const target_ulong masks[])
+{
+    target_ulong x = rs1;
+    int shift = 1;
+    int i = 0;
+
+    while (shift < TARGET_LONG_BITS) {
+        if (rs2 & shift) {
+            x |= do_swap(x, masks[i], shift);
+        }
+        shift <<= 1;
+        ++i;
+    }
+
+    return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+#ifdef TARGET_RISCV32
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+#else
+        0x5555555555555555, 0x3333333333333333, 0x0f0f0f0f0f0f0f0f,
+        0x00ff00ff00ff00ff, 0x0000ffff0000ffff, 0x00000000ffffffff,
+#endif
+    };
+
+    return do_gorc(rs1, rs2, masks);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+    static const target_ulong masks[] = {
+        0x55555555, 0x33333333, 0x0f0f0f0f,
+        0x00ff00ff, 0x0000ffff,
+    };
+
+    return do_gorc(rs1, rs2, masks);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 15243a00761..8effa427b1a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,9 +68,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 #if defined(TARGET_RISCV64)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 #endif
 
 /* Special functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index f2d3b6a5b5d..8e6ec4750f3 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -103,6 +103,7 @@ srow       0010000 .......... 101 ..... 0111011 @r
 rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
+gorcw      0010100 .......... 101 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -111,3 +112,4 @@ sloiw      0010000 .......... 001 ..... 0011011 @sh5
 sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
+gorciw     0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 60821a16661..76ba0698511 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -620,6 +620,7 @@ sro        0010000 .......... 101 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
+gorc       0010100 .......... 101 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
@@ -629,3 +630,4 @@ sloi       001000 ........... 001 ..... 0010011 @sh
 sroi       001000 ........... 101 ..... 0010011 @sh
 rori       011000 ........... 101 ..... 0010011 @sh
 grevi      011010 ........... 101 ..... 0010011 @sh
+gorci      001010 ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9f1482d313a..eade85125c5 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -229,6 +229,23 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
     return gen_grevi(ctx, a);
 }
 
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_gorc);
+}
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -377,4 +394,21 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_grevw);
 }
 
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+
+    if (a->shamt >= 32) {
+        return false;
+    }
+
+    return gen_arith_shamt_tl(ctx, a, &gen_gorcw);
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 80549154d6e..566e60d0d20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -957,6 +957,17 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
     return true;
 }
 
+static void gen_gorc(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    gen_sbop_shamt(shamt, arg2);
+    gen_helper_gorc(ret, arg1, shamt);
+
+    tcg_temp_free(shamt);
+}
+
 
 #ifdef TARGET_RISCV64
 
@@ -1193,6 +1204,21 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv shamt;
+    shamt = tcg_temp_new();
+
+    tcg_gen_ext32u_tl(arg1, arg1);
+
+    gen_sbopw_shamt(shamt, arg2);
+    gen_helper_gorc(ret, arg1, shamt);
+
+    tcg_gen_ext32s_tl(ret, ret);
+
+    tcg_temp_free(shamt);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 12/15] target/riscv: rvb: generalized or-combine

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static target_ulong do_gorc(target_ulong rs1,
> +                            target_ulong rs2,
> +                            const target_ulong masks[])

Similar comments to grev.  I'll also say that the masks array should *not* be
local to do_grev, but placed at file level so that it can be shared between the
two functions.


r~

Re: [RFC 12/15] target/riscv: rvb: generalized or-combine

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static target_ulong do_gorc(target_ulong rs1,
> +                            target_ulong rs2,
> +                            const target_ulong masks[])

Similar comments to grev.  I'll also say that the masks array should *not* be
local to do_grev, but placed at file level so that it can be shared between the
two functions.


r~

[RFC 13/15] target/riscv: rvb: address calculation

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 +++
 target/riscv/insn32.decode              |  3 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 23 +++++++++++++++++
 target/riscv/translate.c                | 33 +++++++++++++++++++++++++
 4 files changed, 62 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8e6ec4750f3..42bafbc03a0 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -104,6 +104,9 @@ rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
+sh1addu_w  0010000 .......... 010 ..... 0111011 @r
+sh2addu_w  0010000 .......... 100 ..... 0111011 @r
+sh3addu_w  0010000 .......... 110 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 76ba0698511..e23a378dec4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -621,6 +621,9 @@ ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
 gorc       0010100 .......... 101 ..... 0110011 @r
+sh1add     0010000 .......... 010 ..... 0110011 @r
+sh2add     0010000 .......... 100 ..... 0110011 @r
+sh3add     0010000 .......... 110 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index eade85125c5..31d791236d9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -246,6 +246,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
     return gen_arith_shamt_tl(ctx, a, &gen_gorc);
 }
 
+#define GEN_TRANS_SHADD(SHAMT)                                             \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{                                                                          \
+    REQUIRE_EXT(ctx, RVB);                                                 \
+    return gen_arith(ctx, a, &gen_sh##SHAMT##add);                         \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -411,4 +422,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_gorcw);
 }
 
+#define GEN_TRANS_SHADDU_W(SHAMT)                             \
+static bool trans_sh##SHAMT##addu_w(DisasContext *ctx,        \
+                                    arg_sh##SHAMT##addu_w *a) \
+{                                                             \
+    REQUIRE_EXT(ctx, RVB);                                    \
+    return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w);         \
+}
+
+GEN_TRANS_SHADDU_W(1)
+GEN_TRANS_SHADDU_W(2)
+GEN_TRANS_SHADDU_W(3)
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 566e60d0d20..584550a9db2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -968,6 +968,21 @@ static void gen_gorc(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+#define GEN_SHADD(SHAMT)                                       \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                              \
+    TCGv t;                                                    \
+    t = tcg_temp_new();                                        \
+                                                               \
+    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
+    tcg_gen_add_tl(ret, t, arg2);                              \
+                                                               \
+    tcg_temp_free(t);                                          \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
 
 #ifdef TARGET_RISCV64
 
@@ -1219,6 +1234,24 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+#define GEN_SHADDU_W(SHAMT)                                       \
+static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                                 \
+    TCGv t;                                                       \
+    t = tcg_temp_new();                                           \
+                                                                  \
+    tcg_gen_ext32u_tl(t, arg1);                                   \
+                                                                  \
+    tcg_gen_shli_tl(t, t, SHAMT);                                 \
+    tcg_gen_add_tl(ret, t, arg2);                                 \
+                                                                  \
+    tcg_temp_free(t);                                             \
+}
+
+GEN_SHADDU_W(1)
+GEN_SHADDU_W(2)
+GEN_SHADDU_W(3)
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 13/15] target/riscv: rvb: address calculation

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn32-64.decode           |  3 +++
 target/riscv/insn32.decode              |  3 +++
 target/riscv/insn_trans/trans_rvb.c.inc | 23 +++++++++++++++++
 target/riscv/translate.c                | 33 +++++++++++++++++++++++++
 4 files changed, 62 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8e6ec4750f3..42bafbc03a0 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -104,6 +104,9 @@ rorw       0110000 .......... 101 ..... 0111011 @r
 rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
+sh1addu_w  0010000 .......... 010 ..... 0111011 @r
+sh2addu_w  0010000 .......... 100 ..... 0111011 @r
+sh3addu_w  0010000 .......... 110 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 76ba0698511..e23a378dec4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -621,6 +621,9 @@ ror        0110000 .......... 101 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
 gorc       0010100 .......... 101 ..... 0110011 @r
+sh1add     0010000 .......... 010 ..... 0110011 @r
+sh2add     0010000 .......... 100 ..... 0110011 @r
+sh3add     0010000 .......... 110 ..... 0110011 @r
 
 sbseti     001010 ........... 001 ..... 0010011 @sh
 sbclri     010010 ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index eade85125c5..31d791236d9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -246,6 +246,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
     return gen_arith_shamt_tl(ctx, a, &gen_gorc);
 }
 
+#define GEN_TRANS_SHADD(SHAMT)                                             \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{                                                                          \
+    REQUIRE_EXT(ctx, RVB);                                                 \
+    return gen_arith(ctx, a, &gen_sh##SHAMT##add);                         \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
 /* RV64-only instructions */
 #ifdef TARGET_RISCV64
 
@@ -411,4 +422,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
     return gen_arith_shamt_tl(ctx, a, &gen_gorcw);
 }
 
+#define GEN_TRANS_SHADDU_W(SHAMT)                             \
+static bool trans_sh##SHAMT##addu_w(DisasContext *ctx,        \
+                                    arg_sh##SHAMT##addu_w *a) \
+{                                                             \
+    REQUIRE_EXT(ctx, RVB);                                    \
+    return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w);         \
+}
+
+GEN_TRANS_SHADDU_W(1)
+GEN_TRANS_SHADDU_W(2)
+GEN_TRANS_SHADDU_W(3)
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 566e60d0d20..584550a9db2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -968,6 +968,21 @@ static void gen_gorc(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+#define GEN_SHADD(SHAMT)                                       \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                              \
+    TCGv t;                                                    \
+    t = tcg_temp_new();                                        \
+                                                               \
+    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
+    tcg_gen_add_tl(ret, t, arg2);                              \
+                                                               \
+    tcg_temp_free(t);                                          \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
 
 #ifdef TARGET_RISCV64
 
@@ -1219,6 +1234,24 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(shamt);
 }
 
+#define GEN_SHADDU_W(SHAMT)                                       \
+static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                                 \
+    TCGv t;                                                       \
+    t = tcg_temp_new();                                           \
+                                                                  \
+    tcg_gen_ext32u_tl(t, arg1);                                   \
+                                                                  \
+    tcg_gen_shli_tl(t, t, SHAMT);                                 \
+    tcg_gen_add_tl(ret, t, arg2);                                 \
+                                                                  \
+    tcg_temp_free(t);                                             \
+}
+
+GEN_SHADDU_W(1)
+GEN_SHADDU_W(2)
+GEN_SHADDU_W(3)
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 13/15] target/riscv: rvb: address calculation

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn32-64.decode           |  3 +++
>  target/riscv/insn32.decode              |  3 +++
>  target/riscv/insn_trans/trans_rvb.c.inc | 23 +++++++++++++++++
>  target/riscv/translate.c                | 33 +++++++++++++++++++++++++
>  4 files changed, 62 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC 13/15] target/riscv: rvb: address calculation

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
> 
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn32-64.decode           |  3 +++
>  target/riscv/insn32.decode              |  3 +++
>  target/riscv/insn_trans/trans_rvb.c.inc | 23 +++++++++++++++++
>  target/riscv/translate.c                | 33 +++++++++++++++++++++++++
>  4 files changed, 62 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  7 +++++
 target/riscv/insn_trans/trans_rvb.c.inc | 38 +++++++++++++++++++++++++
 target/riscv/translate.c                | 18 ++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 42bafbc03a0..5df10cd3066 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -107,6 +107,9 @@ gorcw      0010100 .......... 101 ..... 0111011 @r
 sh1addu_w  0010000 .......... 010 ..... 0111011 @r
 sh2addu_w  0010000 .......... 100 ..... 0111011 @r
 sh3addu_w  0010000 .......... 110 ..... 0111011 @r
+addwu      0000101 .......... 000 ..... 0111011 @r
+subwu      0100101 .......... 000 ..... 0111011 @r
+addu_w     0000100 .......... 000 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -116,3 +119,7 @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
+
+addiwu     ................. 100 ..... 0011011 @i
+
+slliu_w    000010 ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 31d791236d9..c6fcdc5f0c1 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -434,4 +434,42 @@ GEN_TRANS_SHADDU_W(1)
 GEN_TRANS_SHADDU_W(2)
 GEN_TRANS_SHADDU_W(3)
 
+static bool trans_addwu(DisasContext *ctx, arg_addwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_addwu);
+}
+
+static bool trans_addiwu(DisasContext *ctx, arg_addiwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_imm_tl(ctx, a, &gen_addwu);
+}
+
+static bool trans_subwu(DisasContext *ctx, arg_subwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_subwu);
+}
+
+static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_addu_w);
+}
+
+static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
+{
+    TCGv source1;
+    source1 = tcg_temp_new();
+    gen_get_gpr(source1, a->rs1);
+
+    tcg_gen_ext32u_tl(source1, source1);
+    tcg_gen_shli_tl(source1, source1, a->shamt);
+    gen_set_gpr(a->rd, source1);
+
+    tcg_temp_free(source1);
+    return true;
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 584550a9db2..9d36d2bd685 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -672,12 +672,24 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_gen_ext32s_tl(ret, ret);
 }
 
+static void gen_addwu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_add_tl(ret, arg1, arg2);
+    tcg_gen_ext32u_tl(ret, ret);
+}
+
 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_sub_tl(ret, arg1, arg2);
     tcg_gen_ext32s_tl(ret, ret);
 }
 
+static void gen_subwu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_sub_tl(ret, arg1, arg2);
+    tcg_gen_ext32u_tl(ret, ret);
+}
+
 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_mul_tl(ret, arg1, arg2);
@@ -1252,6 +1264,12 @@ GEN_SHADDU_W(1)
 GEN_SHADDU_W(2)
 GEN_SHADDU_W(3)
 
+static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_add_tl(ret, arg1, arg2);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

[RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/insn32-64.decode           |  7 +++++
 target/riscv/insn_trans/trans_rvb.c.inc | 38 +++++++++++++++++++++++++
 target/riscv/translate.c                | 18 ++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 42bafbc03a0..5df10cd3066 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -107,6 +107,9 @@ gorcw      0010100 .......... 101 ..... 0111011 @r
 sh1addu_w  0010000 .......... 010 ..... 0111011 @r
 sh2addu_w  0010000 .......... 100 ..... 0111011 @r
 sh3addu_w  0010000 .......... 110 ..... 0111011 @r
+addwu      0000101 .......... 000 ..... 0111011 @r
+subwu      0100101 .......... 000 ..... 0111011 @r
+addu_w     0000100 .......... 000 ..... 0111011 @r
 
 sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
 sbclriw    0100100 .......... 001 ..... 0011011 @sh5
@@ -116,3 +119,7 @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
+
+addiwu     ................. 100 ..... 0011011 @i
+
+slliu_w    000010 ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 31d791236d9..c6fcdc5f0c1 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -434,4 +434,42 @@ GEN_TRANS_SHADDU_W(1)
 GEN_TRANS_SHADDU_W(2)
 GEN_TRANS_SHADDU_W(3)
 
+static bool trans_addwu(DisasContext *ctx, arg_addwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_addwu);
+}
+
+static bool trans_addiwu(DisasContext *ctx, arg_addiwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith_imm_tl(ctx, a, &gen_addwu);
+}
+
+static bool trans_subwu(DisasContext *ctx, arg_subwu *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_subwu);
+}
+
+static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, &gen_addu_w);
+}
+
+static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
+{
+    TCGv source1;
+    source1 = tcg_temp_new();
+    gen_get_gpr(source1, a->rs1);
+
+    tcg_gen_ext32u_tl(source1, source1);
+    tcg_gen_shli_tl(source1, source1, a->shamt);
+    gen_set_gpr(a->rd, source1);
+
+    tcg_temp_free(source1);
+    return true;
+}
+
 #endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 584550a9db2..9d36d2bd685 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -672,12 +672,24 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_gen_ext32s_tl(ret, ret);
 }
 
+static void gen_addwu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_add_tl(ret, arg1, arg2);
+    tcg_gen_ext32u_tl(ret, ret);
+}
+
 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_sub_tl(ret, arg1, arg2);
     tcg_gen_ext32s_tl(ret, ret);
 }
 
+static void gen_subwu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_sub_tl(ret, arg1, arg2);
+    tcg_gen_ext32u_tl(ret, ret);
+}
+
 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_mul_tl(ret, arg1, arg2);
@@ -1252,6 +1264,12 @@ GEN_SHADDU_W(1)
 GEN_SHADDU_W(2)
 GEN_SHADDU_W(3)
 
+static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_add_tl(ret, arg1, arg2);
+}
+
 #endif
 
 static bool gen_arith(DisasContext *ctx, arg_r *a,
-- 
2.17.1

Re: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +addwu      0000101 .......... 000 ..... 0111011 @r
> +subwu      0100101 .......... 000 ..... 0111011 @r
> +addu_w     0000100 .......... 000 ..... 0111011 @r
>  
>  sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
>  sbclriw    0100100 .......... 001 ..... 0011011 @sh5
> @@ -116,3 +119,7 @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
>  roriw      0110000 .......... 101 ..... 0011011 @sh5
>  greviw     0110100 .......... 101 ..... 0011011 @sh5
>  gorciw     0010100 .......... 101 ..... 0011011 @sh5
> +
> +addiwu     ................. 100 ..... 0011011 @i
> +
> +slliu_w    000010 ........... 001 ..... 0011011 @sh


addwu, subwu, addiwu have been removed in the current draft.

> +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
> +{
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +    gen_get_gpr(source1, a->rs1);
> +
> +    tcg_gen_ext32u_tl(source1, source1);
> +    tcg_gen_shli_tl(source1, source1, a->shamt);
> +    gen_set_gpr(a->rd, source1);

if (a->shamt < 32) {
    tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
} else {
    tcg_gen_shli_i64(source1, source1, a->shamt);
}


r~

Re: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +addwu      0000101 .......... 000 ..... 0111011 @r
> +subwu      0100101 .......... 000 ..... 0111011 @r
> +addu_w     0000100 .......... 000 ..... 0111011 @r
>  
>  sbsetiw    0010100 .......... 001 ..... 0011011 @sh5
>  sbclriw    0100100 .......... 001 ..... 0011011 @sh5
> @@ -116,3 +119,7 @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
>  roriw      0110000 .......... 101 ..... 0011011 @sh5
>  greviw     0110100 .......... 101 ..... 0011011 @sh5
>  gorciw     0010100 .......... 101 ..... 0011011 @sh5
> +
> +addiwu     ................. 100 ..... 0011011 @i
> +
> +slliu_w    000010 ........... 001 ..... 0011011 @sh


addwu, subwu, addiwu have been removed in the current draft.

> +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
> +{
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +    gen_get_gpr(source1, a->rs1);
> +
> +    tcg_gen_ext32u_tl(source1, source1);
> +    tcg_gen_shli_tl(source1, source1, a->shamt);
> +    gen_set_gpr(a->rd, source1);

if (a->shamt < 32) {
    tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
} else {
    tcg_gen_shli_i64(source1, source1, a->shamt);
}


r~

[RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/cpu.c | 4 ++++
 target/riscv/cpu.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f4574..bc29e118c6d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
+        if (cpu->cfg.ext_b) {
+            target_misa |= RVB;
+        }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de4705bb578..c1c77c58a87 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,7 @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
+#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
@@ -278,6 +279,7 @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
+        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
-- 
2.17.1

[RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[frank.chang]

From: Kito Cheng <kito.cheng@sifive.com>

B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
 target/riscv/cpu.c | 4 ++++
 target/riscv/cpu.h | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f4574..bc29e118c6d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
+        if (cpu->cfg.ext_b) {
+            target_misa |= RVB;
+        }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de4705bb578..c1c77c58a87 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,7 @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
+#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
@@ -278,6 +279,7 @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
+        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
-- 
2.17.1

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Alistair Francis]

On Wed, Nov 18, 2020 at 12:45 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> B-extension is default off, use cpu rv32 or rv64 with x-b=true to
> enable B-extension.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 4 ++++
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> +        if (cpu->cfg.ext_b) {
> +            target_misa |= RVB;
> +        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index de4705bb578..c1c77c58a87 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -66,6 +66,7 @@
>  #define RVS RV('S')
>  #define RVU RV('U')
>  #define RVH RV('H')
> +#define RVB RV('B')
>
>  /* S extension denotes that Supervisor mode exists, however it is possible
>     to have a core that support S mode but does not have an MMU and there
> @@ -278,6 +279,7 @@ struct RISCVCPU {
>          bool ext_f;
>          bool ext_d;
>          bool ext_c;
> +        bool ext_b;
>          bool ext_s;
>          bool ext_u;
>          bool ext_h;
> --
> 2.17.1
>
>

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Alistair Francis]

On Wed, Nov 18, 2020 at 12:45 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> B-extension is default off, use cpu rv32 or rv64 with x-b=true to
> enable B-extension.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 4 ++++
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> +        if (cpu->cfg.ext_b) {
> +            target_misa |= RVB;
> +        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index de4705bb578..c1c77c58a87 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -66,6 +66,7 @@
>  #define RVS RV('S')
>  #define RVU RV('U')
>  #define RVH RV('H')
> +#define RVB RV('B')
>
>  /* S extension denotes that Supervisor mode exists, however it is possible
>     to have a core that support S mode but does not have an MMU and there
> @@ -278,6 +279,7 @@ struct RISCVCPU {
>          bool ext_f;
>          bool ext_d;
>          bool ext_c;
> +        bool ext_b;
>          bool ext_s;
>          bool ext_u;
>          bool ext_h;
> --
> 2.17.1
>
>

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Kito Cheng]

> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> +        if (cpu->cfg.ext_b) {
> +            target_misa |= RVB;
> +        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),

I think the default value should be false?

>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Kito Cheng]

> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0bbfd7f4574..bc29e118c6d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> +        if (cpu->cfg.ext_b) {
> +            target_misa |= RVB;
> +        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),

I think the default value should be false?

>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Alistair Francis]

On 19/11/2020 7:02 pm, Kito Cheng wrote:
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 0bbfd7f4574..bc29e118c6d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>>           if (cpu->cfg.ext_h) {
>>               target_misa |= RVH;
>>           }
>> +        if (cpu->cfg.ext_b) {
>> +            target_misa |= RVB;
>> +        }
>>           if (cpu->cfg.ext_v) {
>>               target_misa |= RVV;
>>               if (!is_power_of_2(cpu->cfg.vlen)) {
>> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>>       DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>>       DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>>       /* This is experimental so mark with 'x-' */
>> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
> 
> I think the default value should be false?

Good catch, I missed that.

Yes it should be false.

Alistair

> 
>>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>>       DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>>       DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> 

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Alistair Francis]

On 19/11/2020 7:02 pm, Kito Cheng wrote:
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 0bbfd7f4574..bc29e118c6d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>>           if (cpu->cfg.ext_h) {
>>               target_misa |= RVH;
>>           }
>> +        if (cpu->cfg.ext_b) {
>> +            target_misa |= RVB;
>> +        }
>>           if (cpu->cfg.ext_v) {
>>               target_misa |= RVV;
>>               if (!is_power_of_2(cpu->cfg.vlen)) {
>> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
>>       DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>>       DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>>       /* This is experimental so mark with 'x-' */
>> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
> 
> I think the default value should be false?

Good catch, I missed that.

Yes it should be false.

Alistair

> 
>>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>>       DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>>       DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> 

Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Frank Chang]

[-- Attachment #1: Type: text/plain, Size: 1398 bytes --]

On Sat, Nov 21, 2020 at 12:24 AM Alistair Francis <alistair23@gmail.com>
wrote:

>
>
> On 19/11/2020 7:02 pm, Kito Cheng wrote:
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 0bbfd7f4574..bc29e118c6d 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> >>           if (cpu->cfg.ext_h) {
> >>               target_misa |= RVH;
> >>           }
> >> +        if (cpu->cfg.ext_b) {
> >> +            target_misa |= RVB;
> >> +        }
> >>           if (cpu->cfg.ext_v) {
> >>               target_misa |= RVV;
> >>               if (!is_power_of_2(cpu->cfg.vlen)) {
> >> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
> >>       DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> >>       DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> >>       /* This is experimental so mark with 'x-' */
> >> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
> >
> > I think the default value should be false?
>
> Good catch, I missed that.
>
> Yes it should be false.
>
> Alistair
>

Thanks, I'll fix it in my next patchset.

Frank Chang


>
> >
> >>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> >>       DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> >>       DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> >
>

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Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line

[Frank Chang]

[-- Attachment #1: Type: text/plain, Size: 1398 bytes --]

On Sat, Nov 21, 2020 at 12:24 AM Alistair Francis <alistair23@gmail.com>
wrote:

>
>
> On 19/11/2020 7:02 pm, Kito Cheng wrote:
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 0bbfd7f4574..bc29e118c6d 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> >>           if (cpu->cfg.ext_h) {
> >>               target_misa |= RVH;
> >>           }
> >> +        if (cpu->cfg.ext_b) {
> >> +            target_misa |= RVB;
> >> +        }
> >>           if (cpu->cfg.ext_v) {
> >>               target_misa |= RVV;
> >>               if (!is_power_of_2(cpu->cfg.vlen)) {
> >> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = {
> >>       DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> >>       DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> >>       /* This is experimental so mark with 'x-' */
> >> +    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true),
> >
> > I think the default value should be false?
>
> Good catch, I missed that.
>
> Yes it should be false.
>
> Alistair
>

Thanks, I'll fix it in my next patchset.

Frank Chang


>
> >
> >>       DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> >>       DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> >>       DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> >
>

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Re: [RFC 00/15] support subsets of bitmanip extension

[Richard Henderson]

On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> This patchset implements RISC-V B-extension latest draft version
> (2020.10.26) Zbb, Zbs and Zba subset instructions.

With some additional instructions from Zbp, it seems.  Although the document
isn't completely coherent, with various instructions being present in multiple
subsets, and some instructions w/ strike-out.

The B extension requires more than these three, but I suppose turning it on
with just these 3 subsets during development is ok.


r~

Re: [RFC 00/15] support subsets of bitmanip extension

[Frank Chang]

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On Fri, Nov 20, 2020 at 6:26 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> > This patchset implements RISC-V B-extension latest draft version
> > (2020.10.26) Zbb, Zbs and Zba subset instructions.
>
> With some additional instructions from Zbp, it seems.  Although the
> document
> isn't completely coherent, with various instructions being present in
> multiple
> subsets, and some instructions w/ strike-out.
>
> The B extension requires more than these three, but I suppose turning it on
> with just these 3 subsets during development is ok.
>
>
> r~
>

Yes, some instructions are striked out and moved to another subset during
my implementation.
The B extension spec. is still changing occasionally.

I will send out the next patchset based on your comments.
Thanks for the reviews.

Frank Chang

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Re: [RFC 00/15] support subsets of bitmanip extension

[Frank Chang]

[-- Attachment #1: Type: text/plain, Size: 871 bytes --]

On Fri, Nov 20, 2020 at 6:26 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> > This patchset implements RISC-V B-extension latest draft version
> > (2020.10.26) Zbb, Zbs and Zba subset instructions.
>
> With some additional instructions from Zbp, it seems.  Although the
> document
> isn't completely coherent, with various instructions being present in
> multiple
> subsets, and some instructions w/ strike-out.
>
> The B extension requires more than these three, but I suppose turning it on
> with just these 3 subsets during development is ok.
>
>
> r~
>

Yes, some instructions are striked out and moved to another subset during
my implementation.
The B extension spec. is still changing occasionally.

I will send out the next patchset based on your comments.
Thanks for the reviews.

Frank Chang

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