* [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission @ 2021-06-21 11:41 Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use intel_context->pin_mutex only for context allocation Maarten Lankhorst ` (5 more replies) 0 siblings, 6 replies; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 11:41 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson It doesn't work for legacy ring submission, and is in the best case ignored. In the worst case we end up freeing engine->legacy.ring for all other active engines, resulting in a use-after-free. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 88be76cdafc7 ("drm/i915: Allow userspace to specify ringsize on construction") Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_param.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c b/drivers/gpu/drm/i915/gt/intel_context_param.c index 65dcd090245d..412c36d1b1dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_param.c +++ b/drivers/gpu/drm/i915/gt/intel_context_param.c @@ -12,6 +12,9 @@ int intel_context_set_ring_size(struct intel_context *ce, long sz) { int err; + if (ce->engine->gt->submission_method == INTEL_SUBMISSION_RING) + return 0; + if (intel_context_lock_pinned(ce)) return -EINTR; -- 2.31.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Use intel_context->pin_mutex only for context allocation 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst @ 2021-06-21 11:41 ` Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 3/3] drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) Maarten Lankhorst ` (4 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 11:41 UTC (permalink / raw) To: intel-gfx Rename pin_mutex to alloc_mutex, and only use it for context allocation. This will allow us to simplify __intel_context_do_pin_ww, which no longer needs to run the pre_pin callback separately. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 40 ++++++--------- drivers/gpu/drm/i915/gt/intel_context.h | 17 +++++-- drivers/gpu/drm/i915/gt/intel_context_param.c | 49 ++++++++++++------- drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +- 5 files changed, 62 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 4033184f13b9..e6dab37c4266 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -53,7 +53,10 @@ int intel_context_alloc_state(struct intel_context *ce) { int err = 0; - if (mutex_lock_interruptible(&ce->pin_mutex)) + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) + return 0; + + if (mutex_lock_interruptible(&ce->alloc_mutex)) return -EINTR; if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { @@ -66,11 +69,12 @@ int intel_context_alloc_state(struct intel_context *ce) if (unlikely(err)) goto unlock; + smp_mb__before_atomic(); set_bit(CONTEXT_ALLOC_BIT, &ce->flags); } unlock: - mutex_unlock(&ce->pin_mutex); + mutex_unlock(&ce->alloc_mutex); return err; } @@ -205,19 +209,11 @@ int __intel_context_do_pin_ww(struct intel_context *ce, { bool handoff = false; void *vaddr; - int err = 0; - - if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) { - err = intel_context_alloc_state(ce); - if (err) - return err; - } + int err; - /* - * We always pin the context/ring/timeline here, to ensure a pin - * refcount for __intel_context_active(), which prevent a lock - * inversion of ce->pin_mutex vs dma_resv_lock(). - */ + err = intel_context_alloc_state(ce); + if (err) + return err; err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww); if (!err && ce->ring->vma->obj) @@ -237,24 +233,20 @@ int __intel_context_do_pin_ww(struct intel_context *ce, if (err) goto err_release; - err = mutex_lock_interruptible(&ce->pin_mutex); - if (err) - goto err_post_unpin; - if (unlikely(intel_context_is_closed(ce))) { err = -ENOENT; - goto err_unlock; + goto err_post_unpin; } if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { err = intel_context_active_acquire(ce); if (unlikely(err)) - goto err_unlock; + goto err_post_unpin; err = ce->ops->pin(ce, vaddr); if (err) { intel_context_active_release(ce); - goto err_unlock; + goto err_post_unpin; } CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", @@ -268,8 +260,6 @@ int __intel_context_do_pin_ww(struct intel_context *ce, GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ -err_unlock: - mutex_unlock(&ce->pin_mutex); err_post_unpin: if (!handoff) ce->ops->post_unpin(ce); @@ -381,7 +371,7 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine) spin_lock_init(&ce->signal_lock); INIT_LIST_HEAD(&ce->signals); - mutex_init(&ce->pin_mutex); + mutex_init(&ce->alloc_mutex); i915_active_init(&ce->active, __intel_context_active, __intel_context_retire, 0); @@ -393,7 +383,7 @@ void intel_context_fini(struct intel_context *ce) intel_timeline_put(ce->timeline); i915_vm_put(ce->vm); - mutex_destroy(&ce->pin_mutex); + mutex_destroy(&ce->alloc_mutex); i915_active_fini(&ce->active); } diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index f83a73a2b39f..4cf6901fcb81 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -49,9 +49,16 @@ int intel_context_reconfigure_sseu(struct intel_context *ce, * intel_context_is_pinned() remains stable. */ static inline int intel_context_lock_pinned(struct intel_context *ce) - __acquires(ce->pin_mutex) { - return mutex_lock_interruptible(&ce->pin_mutex); + int ret = intel_context_alloc_state(ce); + + if (ret) + return ret; + + if (ce->state) + return i915_gem_object_lock_interruptible(ce->state->obj, NULL); + else + return i915_gem_object_lock_interruptible(ce->timeline->hwsp_ggtt->obj, NULL); } /** @@ -76,9 +83,11 @@ intel_context_is_pinned(struct intel_context *ce) * Releases the lock earlier acquired by intel_context_unlock_pinned(). */ static inline void intel_context_unlock_pinned(struct intel_context *ce) - __releases(ce->pin_mutex) { - mutex_unlock(&ce->pin_mutex); + if (ce->state) + return i915_gem_object_unlock(ce->state->obj); + else + return i915_gem_object_unlock(ce->timeline->hwsp_ggtt->obj); } int __intel_context_do_pin(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c b/drivers/gpu/drm/i915/gt/intel_context_param.c index 412c36d1b1dd..eba026d63361 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_param.c +++ b/drivers/gpu/drm/i915/gt/intel_context_param.c @@ -10,13 +10,34 @@ int intel_context_set_ring_size(struct intel_context *ce, long sz) { + struct intel_ring *ring; int err; if (ce->engine->gt->submission_method == INTEL_SUBMISSION_RING) return 0; - if (intel_context_lock_pinned(ce)) - return -EINTR; + /* Try fast case (unallocated) first */ + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + bool done = false; + + err = mutex_lock_interruptible(&ce->alloc_mutex); + if (err) + return err; + + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + ce->ring = __intel_context_ring_size(sz); + done = true; + } + mutex_unlock(&ce->alloc_mutex); + + if (done) + return 0; + } + + /* Context already allocated */ + err = intel_context_lock_pinned(ce); + if (err) + return err; err = i915_active_wait(&ce->active); if (err < 0) @@ -27,23 +48,17 @@ int intel_context_set_ring_size(struct intel_context *ce, long sz) goto unlock; } - if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { - struct intel_ring *ring; - - /* Replace the existing ringbuffer */ - ring = intel_engine_create_ring(ce->engine, sz); - if (IS_ERR(ring)) { - err = PTR_ERR(ring); - goto unlock; - } + /* Replace the existing ringbuffer */ + ring = intel_engine_create_ring(ce->engine, sz); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto unlock; + } - intel_ring_put(ce->ring); - ce->ring = ring; + intel_ring_put(ce->ring); + ce->ring = ring; - /* Context image will be updated on next pin */ - } else { - ce->ring = __intel_context_ring_size(sz); - } + /* Context image will be updated on next pin */ unlock: intel_context_unlock_pinned(ce); diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c index e86d8255feec..447b278b107b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c @@ -42,7 +42,7 @@ gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) struct i915_request *rq; int ret; - lockdep_assert_held(&ce->pin_mutex); + assert_object_held(ce->state->obj); /* * If the context is not idle, we have to submit an ordered request to diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index ed8c447a7346..b104d5e9d3b6 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -122,7 +122,7 @@ struct intel_context { unsigned int active_count; /* protected by timeline->mutex */ atomic_t pin_count; - struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ + struct mutex alloc_mutex; /* guards allocation (ops->alloc) */ /** * active: Active tracker for the rq activity (inc. external) on this -- 2.31.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use intel_context->pin_mutex only for context allocation Maarten Lankhorst @ 2021-06-21 11:41 ` Maarten Lankhorst 2021-06-21 12:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Tvrtko Ursulin ` (3 subsequent siblings) 5 siblings, 0 replies; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 11:41 UTC (permalink / raw) To: intel-gfx Now that intel_context->pin_mutex is gone, the reason for splitting pre_pin/post_unpin ops is also gone. Remove those ops, and handle this detail inside guc/execlists submission only. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 19 ++----- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- .../drm/i915/gt/intel_execlists_submission.c | 50 ++++++++----------- .../gpu/drm/i915/gt/intel_ring_submission.c | 16 +----- drivers/gpu/drm/i915/gt/mock_engine.c | 14 +----- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25 ++++++---- 6 files changed, 44 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e6dab37c4266..b630c1968794 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -207,8 +207,6 @@ static void intel_context_post_unpin(struct intel_context *ce) int __intel_context_do_pin_ww(struct intel_context *ce, struct i915_gem_ww_ctx *ww) { - bool handoff = false; - void *vaddr; int err; err = intel_context_alloc_state(ce); @@ -229,40 +227,32 @@ int __intel_context_do_pin_ww(struct intel_context *ce, if (err) goto err_ctx_unpin; - err = ce->ops->pre_pin(ce, ww, &vaddr); - if (err) - goto err_release; - if (unlikely(intel_context_is_closed(ce))) { err = -ENOENT; - goto err_post_unpin; + goto err_release; } if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { err = intel_context_active_acquire(ce); if (unlikely(err)) - goto err_post_unpin; + goto err_release; - err = ce->ops->pin(ce, vaddr); + err = ce->ops->pin(ce, ww); if (err) { intel_context_active_release(ce); - goto err_post_unpin; + goto err_release; } CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", i915_ggtt_offset(ce->ring->vma), ce->ring->head, ce->ring->tail); - handoff = true; smp_mb__before_atomic(); /* flush pin before it is visible */ atomic_inc(&ce->pin_count); } GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ -err_post_unpin: - if (!handoff) - ce->ops->post_unpin(ce); err_release: i915_active_release(&ce->active); err_ctx_unpin: @@ -303,7 +293,6 @@ void intel_context_unpin(struct intel_context *ce) CE_TRACE(ce, "unpin\n"); ce->ops->unpin(ce); - ce->ops->post_unpin(ce); /* * Once released, we may asynchronously drop the active reference. diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index b104d5e9d3b6..e10057901c6c 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -35,10 +35,8 @@ struct intel_context_ops { int (*alloc)(struct intel_context *ce); - int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); - int (*pin)(struct intel_context *ce, void *vaddr); + int (*pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww); void (*unpin)(struct intel_context *ce); - void (*post_unpin)(struct intel_context *ce); void (*enter)(struct intel_context *ce); void (*exit)(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index cdb2126a159a..6a1a45ffe816 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2509,35 +2509,38 @@ static void execlists_submit_request(struct i915_request *request) } static int -__execlists_context_pre_pin(struct intel_context *ce, - struct intel_engine_cs *engine, - struct i915_gem_ww_ctx *ww, void **vaddr) +__execlists_context_pin(struct intel_context *ce, + struct intel_engine_cs *engine, + struct i915_gem_ww_ctx *ww) { int err; + void *vaddr; - err = lrc_pre_pin(ce, engine, ww, vaddr); + err = lrc_pre_pin(ce, engine, ww, &vaddr); if (err) return err; if (!__test_and_set_bit(CONTEXT_INIT_BIT, &ce->flags)) { - lrc_init_state(ce, engine, *vaddr); + lrc_init_state(ce, engine, vaddr); __i915_gem_object_flush_map(ce->state->obj, 0, engine->context_size); } - return 0; + err = lrc_pin(ce, ce->engine, vaddr); + if (err) + lrc_post_unpin(ce); + return err; } -static int execlists_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, - void **vaddr) +static int execlists_context_pin(struct intel_context *ce, struct i915_gem_ww_ctx *ww) { - return __execlists_context_pre_pin(ce, ce->engine, ww, vaddr); + return __execlists_context_pin(ce, ce->engine, ww); } -static int execlists_context_pin(struct intel_context *ce, void *vaddr) +static void execlists_context_unpin(struct intel_context *ce) { - return lrc_pin(ce, ce->engine, vaddr); + lrc_unpin(ce); + lrc_post_unpin(ce); } static int execlists_context_alloc(struct intel_context *ce) @@ -2545,15 +2548,14 @@ static int execlists_context_alloc(struct intel_context *ce) return lrc_alloc(ce, ce->engine); } + static const struct intel_context_ops execlists_context_ops = { .flags = COPS_HAS_INFLIGHT, .alloc = execlists_context_alloc, - .pre_pin = execlists_context_pre_pin, .pin = execlists_context_pin, - .unpin = lrc_unpin, - .post_unpin = lrc_post_unpin, + .unpin = execlists_context_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, @@ -3467,21 +3469,11 @@ static int virtual_context_alloc(struct intel_context *ce) return lrc_alloc(ce, ve->siblings[0]); } -static int virtual_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, - void **vaddr) -{ - struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - - /* Note: we must use a real engine class for setting up reg state */ - return __execlists_context_pre_pin(ce, ve->siblings[0], ww, vaddr); -} - -static int virtual_context_pin(struct intel_context *ce, void *vaddr) +static int virtual_context_pin(struct intel_context *ce, struct i915_gem_ww_ctx *ww) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - return lrc_pin(ce, ve->siblings[0], vaddr); + return __execlists_context_pin(ce, ve->siblings[0], ww); } static void virtual_context_enter(struct intel_context *ce) @@ -3511,10 +3503,8 @@ static const struct intel_context_ops virtual_context_ops = { .alloc = virtual_context_alloc, - .pre_pin = virtual_context_pre_pin, .pin = virtual_context_pin, - .unpin = lrc_unpin, - .post_unpin = lrc_post_unpin, + .unpin = execlists_context_unpin, .enter = virtual_context_enter, .exit = virtual_context_exit, diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 5d42a12ef3d6..85b6a4d60e07 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -467,9 +467,8 @@ static int ring_context_init_default_state(struct intel_context *ce, return 0; } -static int ring_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, - void **unused) +static int ring_context_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) { struct i915_address_space *vm; int err = 0; @@ -498,10 +497,6 @@ static void __context_unpin_ppgtt(struct intel_context *ce) } static void ring_context_unpin(struct intel_context *ce) -{ -} - -static void ring_context_post_unpin(struct intel_context *ce) { __context_unpin_ppgtt(ce); } @@ -572,11 +567,6 @@ static int ring_context_alloc(struct intel_context *ce) return 0; } -static int ring_context_pin(struct intel_context *ce, void *unused) -{ - return 0; -} - static void ring_context_reset(struct intel_context *ce) { intel_ring_reset(ce->ring, ce->ring->emit); @@ -586,10 +576,8 @@ static void ring_context_reset(struct intel_context *ce) static const struct intel_context_ops ring_context_ops = { .alloc = ring_context_alloc, - .pre_pin = ring_context_pre_pin, .pin = ring_context_pin, .unpin = ring_context_unpin, - .post_unpin = ring_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index 68970398e4ef..3e4f6ef705c9 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -123,10 +123,6 @@ static void mock_context_unpin(struct intel_context *ce) { } -static void mock_context_post_unpin(struct intel_context *ce) -{ -} - static void mock_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -166,13 +162,7 @@ static int mock_context_alloc(struct intel_context *ce) return 0; } -static int mock_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, void **unused) -{ - return 0; -} - -static int mock_context_pin(struct intel_context *ce, void *unused) +static int mock_context_pin(struct intel_context *ce, struct i915_gem_ww_ctx *ww) { return 0; } @@ -184,10 +174,8 @@ static void mock_context_reset(struct intel_context *ce) static const struct intel_context_ops mock_context_ops = { .alloc = mock_context_alloc, - .pre_pin = mock_context_pre_pin, .pin = mock_context_pin, .unpin = mock_context_unpin, - .post_unpin = mock_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index e9c237b18692..5b26c0103429 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -437,25 +437,32 @@ static int guc_context_alloc(struct intel_context *ce) return lrc_alloc(ce, ce->engine); } -static int guc_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, - void **vaddr) +static int guc_context_pin(struct intel_context *ce, struct i915_gem_ww_ctx *ww) { - return lrc_pre_pin(ce, ce->engine, ww, vaddr); + void *vaddr; + int err; + + err = lrc_pre_pin(ce, ce->engine, ww, &vaddr); + if (err) + return err; + + err = lrc_pin(ce, ce->engine, vaddr); + if (err) + lrc_post_unpin(ce); + return err; } -static int guc_context_pin(struct intel_context *ce, void *vaddr) +static void guc_context_unpin(struct intel_context *ce) { - return lrc_pin(ce, ce->engine, vaddr); + lrc_unpin(ce); + lrc_post_unpin(ce); } static const struct intel_context_ops guc_context_ops = { .alloc = guc_context_alloc, - .pre_pin = guc_context_pre_pin, .pin = guc_context_pin, - .unpin = lrc_unpin, - .post_unpin = lrc_post_unpin, + .unpin = guc_context_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, -- 2.31.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use intel_context->pin_mutex only for context allocation Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 3/3] drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) Maarten Lankhorst @ 2021-06-21 12:08 ` Tvrtko Ursulin 2021-06-21 12:49 ` Maarten Lankhorst 2021-06-21 12:52 ` Tvrtko Ursulin 2021-06-21 12:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork ` (2 subsequent siblings) 5 siblings, 2 replies; 13+ messages in thread From: Tvrtko Ursulin @ 2021-06-21 12:08 UTC (permalink / raw) To: Maarten Lankhorst, intel-gfx; +Cc: Chris Wilson I had some questions on the trybot mailing list, let me copy&paste.. On 21/06/2021 12:41, Maarten Lankhorst wrote: > It doesn't work for legacy ring submission, and is in the best case > ignored. Looks rejected instead of ignored: static int set_ringsize(struct i915_gem_context *ctx, struct drm_i915_gem_context_param *args) { if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) return -ENODEV; > > In the worst case we end up freeing engine->legacy.ring for all other > active engines, resulting in a use-after-free. Worst case is cloning because ring_context_alloc is not taking a reference to engine->legacy.ring, or something else? Regards, Tvrtko > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Fixes: 88be76cdafc7 ("drm/i915: Allow userspace to specify ringsize on construction") > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_context_param.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c b/drivers/gpu/drm/i915/gt/intel_context_param.c > index 65dcd090245d..412c36d1b1dd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_context_param.c > +++ b/drivers/gpu/drm/i915/gt/intel_context_param.c > @@ -12,6 +12,9 @@ int intel_context_set_ring_size(struct intel_context *ce, long sz) > { > int err; > > + if (ce->engine->gt->submission_method == INTEL_SUBMISSION_RING) > + return 0; > + > if (intel_context_lock_pinned(ce)) > return -EINTR; > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 12:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Tvrtko Ursulin @ 2021-06-21 12:49 ` Maarten Lankhorst 2021-06-21 12:52 ` Tvrtko Ursulin 1 sibling, 0 replies; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 12:49 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: Chris Wilson Op 21-06-2021 om 14:08 schreef Tvrtko Ursulin: > > I had some questions on the trybot mailing list, let me copy&paste.. > > On 21/06/2021 12:41, Maarten Lankhorst wrote: >> It doesn't work for legacy ring submission, and is in the best case >> ignored. > > Looks rejected instead of ignored: > > static int set_ringsize(struct i915_gem_context *ctx, > struct drm_i915_gem_context_param *args) > { > if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) > return -ENODEV; >> >> In the worst case we end up freeing engine->legacy.ring for all other >> active engines, resulting in a use-after-free. > > Worst case is cloning because ring_context_alloc is not taking a reference to engine->legacy.ring, or something else? > > Regards, > > Tvrtko I only noticed this because tests started failing, if it should already hit -ENODEV then that's weird.. See: https://patchwork.freedesktop.org/series/91501/ for the failure. It should not hit the INCOMPLETEs there. The legacy contexts don't grab a reference to engine->legacy.ring, but a copy to the pointer, presumably because its lifetime is always shorter than the ring lifetime, so it will actually free it. ~Maarten _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 12:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Tvrtko Ursulin 2021-06-21 12:49 ` Maarten Lankhorst @ 2021-06-21 12:52 ` Tvrtko Ursulin 2021-06-21 13:07 ` Maarten Lankhorst 1 sibling, 1 reply; 13+ messages in thread From: Tvrtko Ursulin @ 2021-06-21 12:52 UTC (permalink / raw) To: Maarten Lankhorst, intel-gfx; +Cc: Chris Wilson On 21/06/2021 13:08, Tvrtko Ursulin wrote: > > I had some questions on the trybot mailing list, let me copy&paste.. > > On 21/06/2021 12:41, Maarten Lankhorst wrote: >> It doesn't work for legacy ring submission, and is in the best case >> ignored. > > Looks rejected instead of ignored: > > static int set_ringsize(struct i915_gem_context *ctx, > struct drm_i915_gem_context_param *args) > { > if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) > return -ENODEV; >> >> In the worst case we end up freeing engine->legacy.ring for all other >> active engines, resulting in a use-after-free. > > Worst case is cloning because ring_context_alloc is not taking a > reference to engine->legacy.ring, or something else? No can't be that, it was my incomplete analysis last week. Since ring_context_destroy does not actually free the legacy ring I don't see any use after free paths. Regards, Tvrtko >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> >> Fixes: 88be76cdafc7 ("drm/i915: Allow userspace to specify ringsize on >> construction") >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> --- >> drivers/gpu/drm/i915/gt/intel_context_param.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c >> b/drivers/gpu/drm/i915/gt/intel_context_param.c >> index 65dcd090245d..412c36d1b1dd 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_context_param.c >> +++ b/drivers/gpu/drm/i915/gt/intel_context_param.c >> @@ -12,6 +12,9 @@ int intel_context_set_ring_size(struct intel_context >> *ce, long sz) >> { >> int err; >> + if (ce->engine->gt->submission_method == INTEL_SUBMISSION_RING) >> + return 0; >> + >> if (intel_context_lock_pinned(ce)) >> return -EINTR; >> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 12:52 ` Tvrtko Ursulin @ 2021-06-21 13:07 ` Maarten Lankhorst 2021-06-21 13:12 ` Tvrtko Ursulin 0 siblings, 1 reply; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 13:07 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: Chris Wilson Op 21-06-2021 om 14:52 schreef Tvrtko Ursulin: > > On 21/06/2021 13:08, Tvrtko Ursulin wrote: >> >> I had some questions on the trybot mailing list, let me copy&paste.. >> >> On 21/06/2021 12:41, Maarten Lankhorst wrote: >>> It doesn't work for legacy ring submission, and is in the best case >>> ignored. >> >> Looks rejected instead of ignored: >> >> static int set_ringsize(struct i915_gem_context *ctx, >> struct drm_i915_gem_context_param *args) >> { >> if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) >> return -ENODEV; >>> >>> In the worst case we end up freeing engine->legacy.ring for all other >>> active engines, resulting in a use-after-free. >> >> Worst case is cloning because ring_context_alloc is not taking a reference to engine->legacy.ring, or something else? > > No can't be that, it was my incomplete analysis last week. Since ring_context_destroy does not actually free the legacy ring I don't see any use after free paths. > > Regards, Hmm, it gets stuck inside intel_context_set_ring_size when cloning engines.. I guess it can't happen in practice, just the code introduces the race by preallocating inside intel_context_lock_pinned().. copy_ring_size() should only be called for HAS_LOGICAL_RING_CONTEXTS(). I guess that makes this patch obsolete. It can safely be dropped from the series, I think I should probably introduce a check to only set the size when HAS_LOGICAL_RING_CONTEXTS evaluates to true, but that wouldn't block the rest of this series. ~Maarten _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 13:07 ` Maarten Lankhorst @ 2021-06-21 13:12 ` Tvrtko Ursulin 2021-06-21 13:20 ` Tvrtko Ursulin 0 siblings, 1 reply; 13+ messages in thread From: Tvrtko Ursulin @ 2021-06-21 13:12 UTC (permalink / raw) To: Maarten Lankhorst, intel-gfx; +Cc: Chris Wilson On 21/06/2021 14:07, Maarten Lankhorst wrote: > Op 21-06-2021 om 14:52 schreef Tvrtko Ursulin: >> >> On 21/06/2021 13:08, Tvrtko Ursulin wrote: >>> >>> I had some questions on the trybot mailing list, let me copy&paste.. >>> >>> On 21/06/2021 12:41, Maarten Lankhorst wrote: >>>> It doesn't work for legacy ring submission, and is in the best case >>>> ignored. >>> >>> Looks rejected instead of ignored: >>> >>> static int set_ringsize(struct i915_gem_context *ctx, >>> struct drm_i915_gem_context_param *args) >>> { >>> if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) >>> return -ENODEV; >>>> >>>> In the worst case we end up freeing engine->legacy.ring for all other >>>> active engines, resulting in a use-after-free. >>> >>> Worst case is cloning because ring_context_alloc is not taking a reference to engine->legacy.ring, or something else? >> >> No can't be that, it was my incomplete analysis last week. Since ring_context_destroy does not actually free the legacy ring I don't see any use after free paths. >> >> Regards, > > Hmm, it gets stuck inside intel_context_set_ring_size when cloning engines.. > > I guess it can't happen in practice, just the code introduces the race by preallocating > inside intel_context_lock_pinned().. "The code" being the rest of your series? Haven't looked in there, but can't find a problem in upstream. Since as you say, copy_ring_size will run but intel_context_set_ring_size will not free-and-allocate old/new ring since cloned context does not have a state allocated yet. Regards, Tvrtko > copy_ring_size() should only be called for HAS_LOGICAL_RING_CONTEXTS(). > I guess that makes this patch obsolete. It can safely be dropped from the series, > I think I should probably introduce a check to only set the size when HAS_LOGICAL_RING_CONTEXTS > evaluates to true, but that wouldn't block the rest of this series. > > ~Maarten > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 13:12 ` Tvrtko Ursulin @ 2021-06-21 13:20 ` Tvrtko Ursulin 2021-06-21 13:28 ` Maarten Lankhorst 0 siblings, 1 reply; 13+ messages in thread From: Tvrtko Ursulin @ 2021-06-21 13:20 UTC (permalink / raw) To: Maarten Lankhorst, intel-gfx; +Cc: Chris Wilson On 21/06/2021 14:12, Tvrtko Ursulin wrote: > > On 21/06/2021 14:07, Maarten Lankhorst wrote: >> Op 21-06-2021 om 14:52 schreef Tvrtko Ursulin: >>> >>> On 21/06/2021 13:08, Tvrtko Ursulin wrote: >>>> >>>> I had some questions on the trybot mailing list, let me copy&paste.. >>>> >>>> On 21/06/2021 12:41, Maarten Lankhorst wrote: >>>>> It doesn't work for legacy ring submission, and is in the best case >>>>> ignored. >>>> >>>> Looks rejected instead of ignored: >>>> >>>> static int set_ringsize(struct i915_gem_context *ctx, >>>> struct drm_i915_gem_context_param *args) >>>> { >>>> if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) >>>> return -ENODEV; >>>>> >>>>> In the worst case we end up freeing engine->legacy.ring for all other >>>>> active engines, resulting in a use-after-free. >>>> >>>> Worst case is cloning because ring_context_alloc is not taking a >>>> reference to engine->legacy.ring, or something else? >>> >>> No can't be that, it was my incomplete analysis last week. Since >>> ring_context_destroy does not actually free the legacy ring I don't >>> see any use after free paths. >>> >>> Regards, >> >> Hmm, it gets stuck inside intel_context_set_ring_size when cloning >> engines.. >> >> I guess it can't happen in practice, just the code introduces the race >> by preallocating >> inside intel_context_lock_pinned().. > > "The code" being the rest of your series? Haven't looked in there, but > can't find a problem in upstream. Since as you say, copy_ring_size will > run but intel_context_set_ring_size will not free-and-allocate old/new > ring since cloned context does not have a state allocated yet. P.S. Putting a HAS_LOGICAL_RING_CONTEXTS check in copy_ring_size would be a bit unfortunate because layering is a bit broken at the moment and that wouldn't make it better. To clarify my thinking: At the moment allocating the ring is responsibility of a backend specific hook. Apart from the generic intel_context_set_ring_size which breaks that by allocating in the layer above the backend. So proper fix could be to introduce backend specific hooks for ring allocation/freeing. *If* you need to allocate the state so early.. not sure about that. I'd first need to understand why. If you say it is a race then it was all accidental? Regards, Tvrtko > Regards, > > Tvrtko > >> copy_ring_size() should only be called for HAS_LOGICAL_RING_CONTEXTS(). >> I guess that makes this patch obsolete. It can safely be dropped from >> the series, >> I think I should probably introduce a check to only set the size when >> HAS_LOGICAL_RING_CONTEXTS >> evaluates to true, but that wouldn't block the rest of this series. >> >> ~Maarten >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 13:20 ` Tvrtko Ursulin @ 2021-06-21 13:28 ` Maarten Lankhorst 0 siblings, 0 replies; 13+ messages in thread From: Maarten Lankhorst @ 2021-06-21 13:28 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx; +Cc: Chris Wilson Op 21-06-2021 om 15:20 schreef Tvrtko Ursulin: > > On 21/06/2021 14:12, Tvrtko Ursulin wrote: >> >> On 21/06/2021 14:07, Maarten Lankhorst wrote: >>> Op 21-06-2021 om 14:52 schreef Tvrtko Ursulin: >>>> >>>> On 21/06/2021 13:08, Tvrtko Ursulin wrote: >>>>> >>>>> I had some questions on the trybot mailing list, let me copy&paste.. >>>>> >>>>> On 21/06/2021 12:41, Maarten Lankhorst wrote: >>>>>> It doesn't work for legacy ring submission, and is in the best case >>>>>> ignored. >>>>> >>>>> Looks rejected instead of ignored: >>>>> >>>>> static int set_ringsize(struct i915_gem_context *ctx, >>>>> struct drm_i915_gem_context_param *args) >>>>> { >>>>> if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) >>>>> return -ENODEV; >>>>>> >>>>>> In the worst case we end up freeing engine->legacy.ring for all other >>>>>> active engines, resulting in a use-after-free. >>>>> >>>>> Worst case is cloning because ring_context_alloc is not taking a reference to engine->legacy.ring, or something else? >>>> >>>> No can't be that, it was my incomplete analysis last week. Since ring_context_destroy does not actually free the legacy ring I don't see any use after free paths. >>>> >>>> Regards, >>> >>> Hmm, it gets stuck inside intel_context_set_ring_size when cloning engines.. >>> >>> I guess it can't happen in practice, just the code introduces the race by preallocating >>> inside intel_context_lock_pinned().. >> >> "The code" being the rest of your series? Haven't looked in there, but can't find a problem in upstream. Since as you say, copy_ring_size will run but intel_context_set_ring_size will not free-and-allocate old/new ring since cloned context does not have a state allocated yet. > > P.S. Putting a HAS_LOGICAL_RING_CONTEXTS check in copy_ring_size would be a bit unfortunate because layering is a bit broken at the moment and that wouldn't make it better. > > To clarify my thinking: At the moment allocating the ring is responsibility of a backend specific hook. Apart from the generic intel_context_set_ring_size which breaks that by allocating in the layer above the backend. So proper fix could be to introduce backend specific hooks for ring allocation/freeing. > > *If* you need to allocate the state so early.. not sure about that. I'd first need to understand why. If you say it is a race then it was all accidental? I noticed it mostly when debugging. I fixed it currenly by not allocating state in set_ring_size unnecessarily, hence this patch is no longer needed. :) So if that's the only thing, I can just drop this patch entirely. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst ` (2 preceding siblings ...) 2021-06-21 12:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Tvrtko Ursulin @ 2021-06-21 12:14 ` Patchwork 2021-06-21 12:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-06-21 15:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-06-21 12:14 UTC (permalink / raw) To: Maarten Lankhorst; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission URL : https://patchwork.freedesktop.org/series/91722/ State : warning == Summary == $ dim checkpatch origin/drm-tip 39d188a64ac1 drm/i915/gt: Do not allow setting ring size for legacy ring submission d95f14a77694 drm/i915: Use intel_context->pin_mutex only for context allocation -:33: WARNING:MEMORY_BARRIER: memory barrier without comment #33: FILE: drivers/gpu/drm/i915/gt/intel_context.c:72: + smp_mb__before_atomic(); total: 0 errors, 1 warnings, 0 checks, 213 lines checked 630f24c4d56c drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) -:153: CHECK:LINE_SPACING: Please don't use multiple blank lines #153: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2551: + total: 0 errors, 0 warnings, 1 checks, 288 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst ` (3 preceding siblings ...) 2021-06-21 12:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork @ 2021-06-21 12:45 ` Patchwork 2021-06-21 15:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-06-21 12:45 UTC (permalink / raw) To: Maarten Lankhorst; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3016 bytes --] == Series Details == Series: series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission URL : https://patchwork.freedesktop.org/series/91722/ State : success == Summary == CI Bug Log - changes from CI_DRM_10252 -> Patchwork_20418 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/index.html Known issues ------------ Here are the changes found in Patchwork_20418 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-bsw-nick: [INCOMPLETE][2] ([i915#2782] / [i915#2940]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/fi-bsw-nick/igt@i915_selftest@live@execlists.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/fi-bsw-nick/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@hangcheck: - {fi-hsw-gt1}: [DMESG-WARN][4] ([i915#3303]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 Participating hosts (46 -> 37) ------------------------------ Missing (9): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-2 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10252 -> Patchwork_20418 CI-20190529: 20190529 CI_DRM_10252: b6c631d4b0b55b47b95763da2df57e40ba55f283 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6113: 138a29e30277b1039e9934fca5c782dc1e7a9f99 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20418: 630f24c4d56c5151201d2be588308586ccfbff6c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 630f24c4d56c drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) d95f14a77694 drm/i915: Use intel_context->pin_mutex only for context allocation 39d188a64ac1 drm/i915/gt: Do not allow setting ring size for legacy ring submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/index.html [-- Attachment #1.2: Type: text/html, Size: 3630 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst ` (4 preceding siblings ...) 2021-06-21 12:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-06-21 15:04 ` Patchwork 5 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-06-21 15:04 UTC (permalink / raw) To: Maarten Lankhorst; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30261 bytes --] == Series Details == Series: series starting with [1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission URL : https://patchwork.freedesktop.org/series/91722/ State : success == Summary == CI Bug Log - changes from CI_DRM_10252_full -> Patchwork_20418_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_20418_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@legacy-engines-hang@blt: - shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271]) +57 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl4/igt@gem_ctx_persistence@legacy-engines-hang@blt.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed-process.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][9] ([i915#3633]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-snb5/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] / [i915#95]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-glk2/igt@gem_exec_whisper@basic-fds-priority-all.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-glk2/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-tglb: NOTRUN -> [SKIP][12] ([i915#3297]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gem_userptr_blits@input-checking: - shard-tglb: NOTRUN -> [DMESG-WARN][13] ([i915#3002]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb6/igt@gem_userptr_blits@input-checking.html * igt@gen7_exec_parse@basic-offset: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109289]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb1/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@bb-large: - shard-apl: NOTRUN -> [FAIL][15] ([i915#3296]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl3/igt@gen9_exec_parse@bb-large.html * igt@gen9_exec_parse@bb-secure: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#112306]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb6/igt@gen9_exec_parse@bb-secure.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][17] ([i915#454]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][18] ([i915#454]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl6/igt@i915_pm_dc@dc6-psr.html * igt@kms_chamelium@dp-crc-multiple: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl4/igt@kms_chamelium@dp-crc-multiple.html * igt@kms_chamelium@dp-mode-timings: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +17 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl3/igt@kms_chamelium@dp-mode-timings.html * igt@kms_chamelium@hdmi-hpd-for-each-pipe: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +11 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl4/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +21 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_content_protection@dp-mst-type-1: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#3116]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb6/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@srm: - shard-apl: NOTRUN -> [TIMEOUT][24] ([i915#1319]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl2/igt@kms_content_protection@srm.html * igt@kms_content_protection@uevent: - shard-apl: NOTRUN -> [FAIL][25] ([i915#2105]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl3/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding: - shard-skl: [PASS][26] -> [FAIL][27] ([i915#3444]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-random: - shard-apl: NOTRUN -> [FAIL][28] ([i915#3444]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#2346] / [i915#533]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-apl: [PASS][31] -> [FAIL][32] ([i915#2346]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled: - shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [PASS][35] -> [INCOMPLETE][36] ([i915#155] / [i915#180] / [i915#636]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#180]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a2: - shard-glk: [PASS][39] -> [FAIL][40] ([i915#2122]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-glk8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a2.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-glk2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a2.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt: - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271]) +77 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt: - shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111825]) +4 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff: - shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271]) +401 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-snb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][46] -> [INCOMPLETE][47] ([i915#123]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl10/igt@kms_frontbuffer_tracking@psr-suspend.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][48] -> [FAIL][49] ([i915#1188]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d: - shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html - shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: - shard-skl: [PASS][52] -> [FAIL][53] ([i915#53]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][54] -> [DMESG-WARN][55] ([i915#180]) +4 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][57] ([i915#265]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265]) +2 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][60] -> [FAIL][61] ([fdo#108145] / [i915#265]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3: - shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +3 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5: - shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109441]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271]) +142 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_writeback@writeback-invalid-parameters: - shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl6/igt@kms_writeback@writeback-invalid-parameters.html - shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2437]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl8/igt@kms_writeback@writeback-invalid-parameters.html * igt@prime_vgem@coherency-gtt: - shard-tglb: NOTRUN -> [SKIP][70] ([fdo#111656]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb1/igt@prime_vgem@coherency-gtt.html * igt@sysfs_clients@fair-7: - shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2994]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl6/igt@sysfs_clients@fair-7.html * igt@sysfs_clients@sema-25: - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994]) +2 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl6/igt@sysfs_clients@sema-25.html * igt@sysfs_clients@split-10: - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2994]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl3/igt@sysfs_clients@split-10.html #### Possible fixes #### * igt@drm_mm@all@insert_range: - shard-skl: [INCOMPLETE][74] ([i915#2485]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl8/igt@drm_mm@all@insert_range.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl1/igt@drm_mm@all@insert_range.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][76] ([i915#2842]) -> [PASS][77] +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [SKIP][78] ([fdo#109271]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl1/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [SKIP][80] ([fdo#109271]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [FAIL][82] ([i915#2842]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-apl1/igt@gem_exec_suspend@basic-s3.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-apl7/igt@gem_exec_suspend@basic-s3.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [FAIL][86] ([i915#307]) -> [PASS][87] +1 similar issue [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_mmap_gtt@medium-copy: - shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89] +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl10/igt@gem_mmap_gtt@medium-copy.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl5/igt@gem_mmap_gtt@medium-copy.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][90] ([i915#454]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb4/igt@i915_pm_dc@dc6-psr.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb3/igt@i915_pm_dc@dc6-psr.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [FAIL][92] ([i915#2521]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][94] ([i915#300]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_flip@dpms-off-confusion-interruptible@a-edp1: - shard-tglb: [INCOMPLETE][96] -> [PASS][97] +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-tglb6/igt@kms_flip@dpms-off-confusion-interruptible@a-edp1.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-tglb6/igt@kms_flip@dpms-off-confusion-interruptible@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][98] ([i915#180]) -> [PASS][99] +3 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][100] ([fdo#108145] / [i915#265]) -> [PASS][101] +1 similar issue [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][102] ([fdo#109441]) -> [PASS][103] +2 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][104] ([i915#180] / [i915#295]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html #### Warnings #### * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][106] ([i915#588]) -> [SKIP][107] ([i915#658]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][108] ([i915#1804] / [i915#2684]) -> [WARN][109] ([i915#2684]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2: - shard-iclb: [SKIP][110] ([i915#658]) -> [SKIP][111] ([i915#2920]) +2 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2: - shard-iclb: [SKIP][112] ([i915#2920]) -> [SKIP][113] ([i915#658]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html * igt@runner@aborted: - shard-kbl: ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl7/igt@runner@aborted.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl6/igt@runner@aborted.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl7/igt@runner@aborted.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl2/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-kbl3/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl2/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl2/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl7/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl2/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl2/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl7/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-kbl1/igt@runner@aborted.html - shard-skl: ([FAIL][126], [FAIL][127], [FAIL][128]) ([i915#2029] / [i915#3002] / [i915#3363]) -> ([FAIL][129], [FAIL][130]) ([i915#3002] / [i915#3363]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl3/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl1/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10252/shard-skl2/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl7/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/shard-skl7/igt@runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3444]: https://gitlab.freedesktop.org/drm/intel/issues/3444 [i915#3633]: https://gitlab.freedesktop.org/drm/intel/issues/3633 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_10252 -> Patchwork_20418 CI-20190529: 20190529 CI_DRM_10252: b6c631d4b0b55b47b95763da2df57e40ba55f283 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6113: 138a29e30277b1039e9934fca5c782dc1e7a9f99 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20418: 630f24c4d56c5151201d2be588308586ccfbff6c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20418/index.html [-- Attachment #1.2: Type: text/html, Size: 37887 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-06-21 15:04 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-21 11:41 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 2/3] drm/i915: Use intel_context->pin_mutex only for context allocation Maarten Lankhorst 2021-06-21 11:41 ` [Intel-gfx] [PATCH 3/3] drm/i915: Remove intel_context->ops->(pre_pin/post_unpin) Maarten Lankhorst 2021-06-21 12:08 ` [Intel-gfx] [PATCH 1/3] drm/i915/gt: Do not allow setting ring size for legacy ring submission Tvrtko Ursulin 2021-06-21 12:49 ` Maarten Lankhorst 2021-06-21 12:52 ` Tvrtko Ursulin 2021-06-21 13:07 ` Maarten Lankhorst 2021-06-21 13:12 ` Tvrtko Ursulin 2021-06-21 13:20 ` Tvrtko Ursulin 2021-06-21 13:28 ` Maarten Lankhorst 2021-06-21 12:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] " Patchwork 2021-06-21 12:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-06-21 15:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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