* [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support @ 2019-09-21 13:50 Huacai Chen 2019-09-21 13:50 ` [PATCH V2 2/3] MIPS: Loongson: Add Loongson-3A R4 basic support Huacai Chen ` (3 more replies) 0 siblings, 4 replies; 13+ messages in thread From: Huacai Chen @ 2019-09-21 13:50 UTC (permalink / raw) To: Paul Burton, Ralf Baechle, James Hogan Cc: linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Huacai Chen, Jiaxun Yang Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and CSR (Control and Status Register) extensions. This patch add read/write functionalities for them. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- .../include/asm/mach-loongson64/loongson_regs.h | 227 +++++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 arch/mips/include/asm/mach-loongson64/loongson_regs.h diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h new file mode 100644 index 00000000..6e3569a --- /dev/null +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -0,0 +1,227 @@ +/* + * Read/Write Loongson Extension Registers + */ + +#ifndef _LOONGSON_REGS_H_ +#define _LOONGSON_REGS_H_ + +#include <linux/types.h> +#include <linux/bits.h> + +#include <asm/mipsregs.h> +#include <asm/cpu.h> + +static inline bool cpu_has_cfg(void) +{ + return ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G); +} + +static inline u32 read_cpucfg(u32 reg) +{ + u32 __res; + + __asm__ __volatile__( + "parse_r __res,%0\n\t" + "parse_r reg,%1\n\t" + ".insn \n\t" + ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" + :"=r"(__res) + :"r"(reg) + : + ); + return __res; +} + +/* Bit Domains for CFG registers */ +#define LOONGSON_CFG0 0x0 +#define LOONGSON_CFG0_PRID GENMASK(31, 0) + +#define LOONGSON_CFG1 0x1 +#define LOONGSON_CFG1_FP BIT(0) +#define LOONGSON_CFG1_FPREV GENMASK(3, 1) +#define LOONGSON_CFG1_MMI BIT(4) +#define LOONGSON_CFG1_MSA1 BIT(5) +#define LOONGSON_CFG1_MSA2 BIT(6) +#define LOONGSON_CFG1_CGP BIT(7) +#define LOONGSON_CFG1_WRP BIT(8) +#define LOONGSON_CFG1_LSX1 BIT(9) +#define LOONGSON_CFG1_LSX2 BIT(10) +#define LOONGSON_CFG1_LASX BIT(11) +#define LOONGSON_CFG1_R6FXP BIT(12) +#define LOONGSON_CFG1_R6CRCP BIT(13) +#define LOONGSON_CFG1_R6FPP BIT(14) +#define LOONGSON_CFG1_CNT64 BIT(15) +#define LOONGSON_CFG1_LSLDR0 BIT(16) +#define LOONGSON_CFG1_LSPREF BIT(17) +#define LOONGSON_CFG1_LSPREFX BIT(18) +#define LOONGSON_CFG1_LSSYNCI BIT(19) +#define LOONGSON_CFG1_LSUCA BIT(20) +#define LOONGSON_CFG1_LLSYNC BIT(21) +#define LOONGSON_CFG1_TGTSYNC BIT(22) +#define LOONGSON_CFG1_LLEXC BIT(23) +#define LOONGSON_CFG1_SCRAND BIT(24) +#define LOONGSON_CFG1_MUALP BIT(25) +#define LOONGSON_CFG1_KMUALEN BIT(26) +#define LOONGSON_CFG1_ITLBT BIT(27) +#define LOONGSON_CFG1_LSUPERF BIT(28) +#define LOONGSON_CFG1_SFBP BIT(29) +#define LOONGSON_CFG1_CDMAP BIT(30) + +#define LOONGSON_CFG2 0x2 +#define LOONGSON_CFG2_LEXT1 BIT(0) +#define LOONGSON_CFG2_LEXT2 BIT(1) +#define LOONGSON_CFG2_LEXT3 BIT(2) +#define LOONGSON_CFG2_LSPW BIT(3) +#define LOONGSON_CFG2_LBT1 BIT(4) +#define LOONGSON_CFG2_LBT2 BIT(5) +#define LOONGSON_CFG2_LBT3 BIT(6) +#define LOONGSON_CFG2_LBTMMU BIT(7) +#define LOONGSON_CFG2_LPMP BIT(8) +#define LOONGSON_CFG2_LPMPREV GENMASK(11, 9) +#define LOONGSON_CFG2_LAMO BIT(12) +#define LOONGSON_CFG2_LPIXU BIT(13) +#define LOONGSON_CFG2_LPIXUN BIT(14) +#define LOONGSON_CFG2_LZVP BIT(15) +#define LOONGSON_CFG2_LZVREV GENMASK(18, 16) +#define LOONGSON_CFG2_LGFTP BIT(19) +#define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) +#define LOONGSON_CFG2_LLFTP BIT(23) +#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) +#define LOONGSON_CFG2_LCSRP BIT(27) +#define LOONGSON_CFG2_LDISBLIKELY BIT(28) + +#define LOONGSON_CFG3 0x3 +#define LOONGSON_CFG3_LCAMP BIT(0) +#define LOONGSON_CFG3_LCAMREV GENMASK(3, 1) +#define LOONGSON_CFG3_LCAMNUM GENMASK(11, 4) +#define LOONGSON_CFG3_LCAMKW GENMASK(19, 12) +#define LOONGSON_CFG3_LCAMVW GENMASK(27, 20) + +#define LOONGSON_CFG4 0x4 +#define LOONGSON_CFG4_CCFREQ GENMASK(31, 0) + +#define LOONGSON_CFG5 0x5 +#define LOONGSON_CFG5_CFM GENMASK(15, 0) +#define LOONGSON_CFG5_CFD GENMASK(31, 16) + +#define LOONGSON_CFG6 0x6 + +#define LOONGSON_CFG7 0x7 +#define LOONGSON_CFG7_GCCAEQRP BIT(0) +#define LOONGSON_CFG7_UCAWINP BIT(1) + +static inline bool cpu_has_csr(void) +{ + if (cpu_has_cfg()) + return (read_cpucfg(LOONGSON_CFG2) & LOONGSON_CFG2_LCSRP); + + return false; +} + +static inline u32 csr_readl(u32 reg) +{ + u32 __res; + + /* RDCSR reg, val */ + __asm__ __volatile__( + "parse_r __res,%0\n\t" + "parse_r reg,%1\n\t" + ".insn \n\t" + ".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t" + :"=r"(__res) + :"r"(reg) + : + ); + return __res; +} + +static inline u64 csr_readq(u32 reg) +{ + u64 __res; + + /* DWRCSR reg, val */ + __asm__ __volatile__( + "parse_r __res,%0\n\t" + "parse_r reg,%1\n\t" + ".insn \n\t" + ".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t" + :"=r"(__res) + :"r"(reg) + : + ); + return __res; +} + +static inline void csr_writel(u32 val, u32 reg) +{ + /* WRCSR reg, val */ + __asm__ __volatile__( + "parse_r reg,%0\n\t" + "parse_r val,%1\n\t" + ".insn \n\t" + ".word (0xc8010118 | (reg << 21) | (val << 11))\n\t" + : + :"r"(reg),"r"(val) + : + ); +} + +static inline void csr_writeq(u64 val, u32 reg) +{ + /* DWRCSR reg, val */ + __asm__ __volatile__( + "parse_r reg,%0\n\t" + "parse_r val,%1\n\t" + ".insn \n\t" + ".word (0xc8030118 | (reg << 21) | (val << 11))\n\t" + : + :"r"(reg),"r"(val) + : + ); +} + +/* Public CSR Register can also be accessed with regular addresses */ +#define CSR_PUBLIC_MMIO_BASE 0x1fe00000 + +#define MMIO_CSR(x) (void *)TO_UNCAC(CSR_PUBLIC_MMIO_BASE + x) + +#define LOONGSON_CSR_FEATURES 0x8 +#define LOONGSON_CSRF_TEMP BIT(0) +#define LOONGSON_CSRF_NODECNT BIT(1) +#define LOONGSON_CSRF_MSI BIT(2) +#define LOONGSON_CSRF_EXTIOI BIT(3) +#define LOONGSON_CSRF_IPI BIT(4) +#define LOONGSON_CSRF_FREQ BIT(5) + +#define LOONGSON_CSR_VENDOR 0x10 /* Vendor name string, should be "Loongson" */ +#define LOONGSON_CSR_CPUNAME 0x20 /* Processor name string */ +#define LOONGSON_CSR_NODECNT 0x408 +#define LOONGSON_CSR_CPUTEMP 0x428 + +/* PerCore CSR, only accessable by local cores */ +#define LOONGSON_CSR_IPI_STATUS 0x1000 +#define LOONGSON_CSR_IPI_EN 0x1004 +#define LOONGSON_CSR_IPI_SET 0x1008 +#define LOONGSON_CSR_IPI_CLEAR 0x100c +#define LOONGSON_CSR_IPI_SEND 0x1040 +#define CSR_IPI_SEND_IP_SHIFT 0 +#define CSR_IPI_SEND_CPU_SHIFT 16 +#define CSR_IPI_SEND_BLOCK BIT(31) + +static inline u64 drdtime(void) +{ + int rID = 0; + u64 val = 0; + + __asm__ __volatile__( + "parse_r rID,%0\n\t" + "parse_r val,%1\n\t" + ".insn \n\t" + ".word (0xc8090118 | (rID << 21) | (val << 11))\n\t" + :"=r"(rID),"=r"(val) + : + ); + return val; +} + +#endif -- 2.7.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 2/3] MIPS: Loongson: Add Loongson-3A R4 basic support 2019-09-21 13:50 [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Huacai Chen @ 2019-09-21 13:50 ` Huacai Chen 2019-09-21 13:50 ` [PATCH V2 3/3] MIPS: Loongson-3: Add CSR IPI support Huacai Chen ` (2 subsequent siblings) 3 siblings, 0 replies; 13+ messages in thread From: Huacai Chen @ 2019-09-21 13:50 UTC (permalink / raw) To: Paul Burton, Ralf Baechle, James Hogan Cc: linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Huacai Chen, Jiaxun Yang All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/Kconfig | 2 + arch/mips/include/asm/cpu.h | 4 +- .../asm/mach-loongson64/kernel-entry-init.h | 28 +++++-- arch/mips/kernel/cpu-probe.c | 16 +++- arch/mips/kernel/idle.c | 3 +- arch/mips/loongson64/loongson-3/smp.c | 90 ++++++++++++---------- arch/mips/mm/c-r4k.c | 3 +- drivers/platform/mips/cpu_hwmon.c | 15 ++++ 8 files changed, 111 insertions(+), 50 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2f7c050..f8485dc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1378,9 +1378,11 @@ config CPU_LOONGSON3 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select CPU_SUPPORTS_MSA select CPU_HAS_LOAD_STORE_LR select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC + select MIPS_ASID_BITS_VARIABLE select MIPS_PGD_C0_CONTEXT select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 7fddcb8..81ddb57 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -91,7 +91,9 @@ #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 -#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ +#define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */ +#define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */ +#define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */ #define PRID_IMP_UNKNOWN 0xff00 diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h index b5e288a..b968732 100644 --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h @@ -30,13 +30,21 @@ mtc0 t0, CP0_PAGEGRAIN /* Enable STFill Buffer */ mfc0 t0, CP0_PRID + /* Loongson-3A R4+ */ + andi t1, t0, PRID_IMP_MASK + li t2, PRID_IMP_LOONGSON_64G + beq t1, t2, 1f + nop + /* Loongson-3A R2/R3 */ andi t0, (PRID_IMP_MASK | PRID_REV_MASK) - slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0) - bnez t0, 1f + slti t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) + bnez t0, 2f + nop +1: mfc0 t0, CP0_CONFIG6 or t0, 0x100 mtc0 t0, CP0_CONFIG6 -1: +2: _ehb .set pop #endif @@ -59,13 +67,21 @@ mtc0 t0, CP0_PAGEGRAIN /* Enable STFill Buffer */ mfc0 t0, CP0_PRID + /* Loongson-3A R4+ */ + andi t1, t0, PRID_IMP_MASK + li t2, PRID_IMP_LOONGSON_64G + beq t1, t2, 1f + nop + /* Loongson-3A R2/R3 */ andi t0, (PRID_IMP_MASK | PRID_REV_MASK) - slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0) - bnez t0, 1f + slti t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) + bnez t0, 2f + nop +1: mfc0 t0, CP0_CONFIG6 or t0, 0x100 mtc0 t0, CP0_CONFIG6 -1: +2: _ehb .set pop #endif diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c2eb392..bbfc954 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1526,7 +1526,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; c->tlbsize = 64; break; - case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ + case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON2E: c->cputype = CPU_LOONGSON2; @@ -1565,6 +1565,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_FPU | MIPS_CPU_LLSC | MIPS_CPU_32FPR; c->tlbsize = 64; + set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); c->writecombine = _CACHE_UNCACHED_ACCELERATED; break; case PRID_IMP_LOONGSON_32: /* Loongson-1 */ @@ -1903,7 +1904,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { switch (c->processor_id & PRID_IMP_MASK) { - case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ + case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON3A_R2_0: case PRID_REV_LOONGSON3A_R2_1: @@ -1927,6 +1928,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); break; + case PRID_IMP_LOONGSON_64G: + c->cputype = CPU_LOONGSON3; + __cpu_name[cpu] = "ICT Loongson-3"; + set_elf_platform(cpu, "loongson3a"); + set_isa(c, MIPS_CPU_ISA_M64R2); + decode_configs(c); + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->writecombine = _CACHE_UNCACHED_ACCELERATED; + c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | + MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); + break; default: panic("Unknown Loongson Processor ID!"); break; diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index eb2afc0..980d6c3 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -179,7 +179,8 @@ void __init check_wait(void) cpu_wait = r4k_wait; break; case CPU_LOONGSON3: - if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0) + if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= + (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)) cpu_wait = r4k_wait; break; diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c index ce68cda..e999bb1 100644 --- a/arch/mips/loongson64/loongson-3/smp.c +++ b/arch/mips/loongson64/loongson-3/smp.c @@ -450,7 +450,7 @@ static void loongson3_cpu_die(unsigned int cpu) * flush all L1 entries at first. Then, another core (usually Core 0) can * safely disable the clock of the target core. loongson3_play_dead() is * called via CKSEG1 (uncached and unmmaped) */ -static void loongson3a_r1_play_dead(int *state_addr) +static void loongson3_type1_play_dead(int *state_addr) { register int val; register long cpuid, core, node, count; @@ -512,7 +512,7 @@ static void loongson3a_r1_play_dead(int *state_addr) : "a1"); } -static void loongson3a_r2r3_play_dead(int *state_addr) +static void loongson3_type2_play_dead(int *state_addr) { register int val; register long cpuid, core, node, count; @@ -532,27 +532,7 @@ static void loongson3a_r2r3_play_dead(int *state_addr) " cache 1, 3(%[addr]) \n" " addiu %[sets], %[sets], -1 \n" " bnez %[sets], 1b \n" - " addiu %[addr], %[addr], 0x40 \n" - " li %[addr], 0x80000000 \n" /* KSEG0 */ - "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */ - " cache 2, 1(%[addr]) \n" - " cache 2, 2(%[addr]) \n" - " cache 2, 3(%[addr]) \n" - " cache 2, 4(%[addr]) \n" - " cache 2, 5(%[addr]) \n" - " cache 2, 6(%[addr]) \n" - " cache 2, 7(%[addr]) \n" - " cache 2, 8(%[addr]) \n" - " cache 2, 9(%[addr]) \n" - " cache 2, 10(%[addr]) \n" - " cache 2, 11(%[addr]) \n" - " cache 2, 12(%[addr]) \n" - " cache 2, 13(%[addr]) \n" - " cache 2, 14(%[addr]) \n" - " cache 2, 15(%[addr]) \n" - " addiu %[vsets], %[vsets], -1 \n" - " bnez %[vsets], 2b \n" - " addiu %[addr], %[addr], 0x40 \n" + " addiu %[addr], %[addr], 0x20 \n" " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ " sw %[val], (%[state_addr]) \n" " sync \n" @@ -560,8 +540,7 @@ static void loongson3a_r2r3_play_dead(int *state_addr) " .set pop \n" : [addr] "=&r" (addr), [val] "=&r" (val) : [state_addr] "r" (state_addr), - [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), - [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets)); + [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); __asm__ __volatile__( " .set push \n" @@ -576,6 +555,8 @@ static void loongson3a_r2r3_play_dead(int *state_addr) " andi %[node], %[cpuid], 0xc \n" " dsll %[node], 42 \n" /* get node id */ " or %[base], %[base], %[node] \n" + " dsrl %[node], 30 \n" /* 15:14 */ + " or %[base], %[base], %[node] \n" "1: li %[count], 0x100 \n" /* wait for init loop */ "2: bnez %[count], 2b \n" /* limit mailbox access */ " addiu %[count], -1 \n" @@ -595,7 +576,7 @@ static void loongson3a_r2r3_play_dead(int *state_addr) : "a1"); } -static void loongson3b_play_dead(int *state_addr) +static void loongson3_type3_play_dead(int *state_addr) { register int val; register long cpuid, core, node, count; @@ -615,7 +596,27 @@ static void loongson3b_play_dead(int *state_addr) " cache 1, 3(%[addr]) \n" " addiu %[sets], %[sets], -1 \n" " bnez %[sets], 1b \n" - " addiu %[addr], %[addr], 0x20 \n" + " addiu %[addr], %[addr], 0x40 \n" + " li %[addr], 0x80000000 \n" /* KSEG0 */ + "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */ + " cache 2, 1(%[addr]) \n" + " cache 2, 2(%[addr]) \n" + " cache 2, 3(%[addr]) \n" + " cache 2, 4(%[addr]) \n" + " cache 2, 5(%[addr]) \n" + " cache 2, 6(%[addr]) \n" + " cache 2, 7(%[addr]) \n" + " cache 2, 8(%[addr]) \n" + " cache 2, 9(%[addr]) \n" + " cache 2, 10(%[addr]) \n" + " cache 2, 11(%[addr]) \n" + " cache 2, 12(%[addr]) \n" + " cache 2, 13(%[addr]) \n" + " cache 2, 14(%[addr]) \n" + " cache 2, 15(%[addr]) \n" + " addiu %[vsets], %[vsets], -1 \n" + " bnez %[vsets], 2b \n" + " addiu %[addr], %[addr], 0x40 \n" " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ " sw %[val], (%[state_addr]) \n" " sync \n" @@ -623,7 +624,8 @@ static void loongson3b_play_dead(int *state_addr) " .set pop \n" : [addr] "=&r" (addr), [val] "=&r" (val) : [state_addr] "r" (state_addr), - [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); + [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), + [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets)); __asm__ __volatile__( " .set push \n" @@ -638,8 +640,6 @@ static void loongson3b_play_dead(int *state_addr) " andi %[node], %[cpuid], 0xc \n" " dsll %[node], 42 \n" /* get node id */ " or %[base], %[base], %[node] \n" - " dsrl %[node], 30 \n" /* 15:14 */ - " or %[base], %[base], %[node] \n" "1: li %[count], 0x100 \n" /* wait for init loop */ "2: bnez %[count], 2b \n" /* limit mailbox access */ " addiu %[count], -1 \n" @@ -661,30 +661,42 @@ static void loongson3b_play_dead(int *state_addr) void play_dead(void) { - int *state_addr; + int prid_imp, prid_rev, *state_addr; unsigned int cpu = smp_processor_id(); void (*play_dead_at_ckseg1)(int *); idle_task_exit(); - switch (read_c0_prid() & PRID_REV_MASK) { + + prid_imp = read_c0_prid() & PRID_IMP_MASK; + prid_rev = read_c0_prid() & PRID_REV_MASK; + + if (prid_imp == PRID_IMP_LOONGSON_64G) { + play_dead_at_ckseg1 = + (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); + goto out; + } + + switch (prid_rev) { case PRID_REV_LOONGSON3A_R1: default: play_dead_at_ckseg1 = - (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead); + (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead); + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + play_dead_at_ckseg1 = + (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead); break; case PRID_REV_LOONGSON3A_R2_0: case PRID_REV_LOONGSON3A_R2_1: case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_1: play_dead_at_ckseg1 = - (void *)CKSEG1ADDR((unsigned long)loongson3a_r2r3_play_dead); - break; - case PRID_REV_LOONGSON3B_R1: - case PRID_REV_LOONGSON3B_R2: - play_dead_at_ckseg1 = - (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead); + (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); break; } + +out: state_addr = &per_cpu(cpu_state, cpu); mb(); play_dead_at_ckseg1(state_addr); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 89b9c85..4bf9906 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1267,7 +1267,8 @@ static void probe_pcache(void) c->dcache.ways * c->dcache.linesz; c->dcache.waybit = 0; - if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0) + if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= + (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)) c->options |= MIPS_CPU_PREFETCH; break; diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c index a7f184b..1833b51 100644 --- a/drivers/platform/mips/cpu_hwmon.c +++ b/drivers/platform/mips/cpu_hwmon.c @@ -9,6 +9,9 @@ #include <loongson.h> #include <boot_param.h> #include <loongson_hwmon.h> +#include <loongson_regs.h> + +static int csr_temp_enable = 0; /* * Loongson-3 series cpu has two sensors inside, @@ -20,8 +23,14 @@ int loongson3_cpu_temp(int cpu) { u32 reg, prid_rev; + if (csr_temp_enable) { + reg = (csr_readl(LOONGSON_CSR_CPUTEMP) & 0xff); + goto out; + } + reg = LOONGSON_CHIPTEMP(cpu); prid_rev = read_c0_prid() & PRID_REV_MASK; + switch (prid_rev) { case PRID_REV_LOONGSON3A_R1: reg = (reg >> 8) & 0xff; @@ -34,9 +43,12 @@ int loongson3_cpu_temp(int cpu) break; case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_1: + default: reg = (reg & 0xffff)*731/0x4000 - 273; break; } + +out: return (int)reg * 1000; } @@ -159,6 +171,9 @@ static int __init loongson_hwmon_init(void) pr_info("Loongson Hwmon Enter...\n"); + if (cpu_has_csr()) + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; + cpu_hwmon_dev = hwmon_device_register(NULL); if (IS_ERR(cpu_hwmon_dev)) { ret = -ENOMEM; -- 2.7.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH V2 3/3] MIPS: Loongson-3: Add CSR IPI support 2019-09-21 13:50 [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Huacai Chen 2019-09-21 13:50 ` [PATCH V2 2/3] MIPS: Loongson: Add Loongson-3A R4 basic support Huacai Chen @ 2019-09-21 13:50 ` Huacai Chen 2019-10-07 17:51 ` [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Paul Burton 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn 3 siblings, 0 replies; 13+ messages in thread From: Huacai Chen @ 2019-09-21 13:50 UTC (permalink / raw) To: Paul Burton, Ralf Baechle, James Hogan Cc: linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Huacai Chen CSR IPI and legacy MMIO use the same infrastructure, but CSR IPI is faster than legacy MMIO IPI. This patch enable CSR IPI if possible (except for MailBox, because CSR IPI is too complicated for MailBox). Signed-off-by: Huacai Chen <chenhc@lemote.com> --- arch/mips/loongson64/loongson-3/smp.c | 70 +++++++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 8 deletions(-) diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c index e999bb1..de8e074 100644 --- a/arch/mips/loongson64/loongson-3/smp.c +++ b/arch/mips/loongson64/loongson-3/smp.c @@ -18,6 +18,7 @@ #include <asm/tlbflush.h> #include <asm/cacheflush.h> #include <loongson.h> +#include <loongson_regs.h> #include <workarounds.h> #include "smp.h" @@ -48,6 +49,62 @@ static uint32_t core0_c0count[NR_CPUS]; __wbflush(); \ } while (0) +u32 (*ipi_read_clear)(int cpu); +void (*ipi_write_action)(int cpu, u32 action); + +static u32 csr_ipi_read_clear(int cpu) +{ + u32 action; + + /* Load the ipi register to figure out what we're supposed to do */ + action = csr_readl(LOONGSON_CSR_IPI_STATUS); + /* Clear the ipi register to clear the interrupt */ + csr_writel(action, LOONGSON_CSR_IPI_CLEAR); + + return action; +} + +static void csr_ipi_write_action(int cpu, u32 action) +{ + unsigned int irq = 0; + + while ((irq = ffs(action))) { + uint32_t val = CSR_IPI_SEND_BLOCK; + val |= (irq - 1); + val |= (cpu << CSR_IPI_SEND_CPU_SHIFT); + csr_writel(val, LOONGSON_CSR_IPI_SEND); + action &= ~BIT(irq - 1); + } +} + +static u32 legacy_ipi_read_clear(int cpu) +{ + u32 action; + + /* Load the ipi register to figure out what we're supposed to do */ + action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); + /* Clear the ipi register to clear the interrupt */ + loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); + + return action; +} + +static void legacy_ipi_write_action(int cpu, u32 action) +{ + loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); +} + +static void csr_ipi_probe(void) +{ + if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) { + ipi_read_clear = csr_ipi_read_clear; + ipi_write_action = csr_ipi_write_action; + } else { + ipi_read_clear = legacy_ipi_read_clear; + ipi_write_action = legacy_ipi_write_action; + } +} + static void ipi_set0_regs_init(void) { ipi_set0_regs[0] = (void *) @@ -233,7 +290,7 @@ static void ipi_mailbox_buf_init(void) */ static void loongson3_send_ipi_single(int cpu, unsigned int action) { - loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(cpu)]); + ipi_write_action(cpu_logical_map(cpu), (u32)action); } static void @@ -242,14 +299,14 @@ loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) unsigned int i; for_each_cpu(i, mask) - loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]); + ipi_write_action(cpu_logical_map(i), (u32)action); } #define IPI_IRQ_OFFSET 6 void loongson3_send_irq_by_ipi(int cpu, int irqs) { - loongson3_ipi_write32(irqs << IPI_IRQ_OFFSET, ipi_set0_regs[cpu_logical_map(cpu)]); + ipi_write_action(cpu_logical_map(cpu), irqs << IPI_IRQ_OFFSET); } void loongson3_ipi_interrupt(struct pt_regs *regs) @@ -257,13 +314,9 @@ void loongson3_ipi_interrupt(struct pt_regs *regs) int i, cpu = smp_processor_id(); unsigned int action, c0count, irqs; - /* Load the ipi register to figure out what we're supposed to do */ - action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); + action = ipi_read_clear(cpu); irqs = action >> IPI_IRQ_OFFSET; - /* Clear the ipi register to clear the interrupt */ - loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]); - if (action & SMP_RESCHEDULE_YOURSELF) scheduler_ipi(); @@ -372,6 +425,7 @@ static void __init loongson3_smp_setup(void) num++; } + csr_ipi_probe(); ipi_set0_regs_init(); ipi_clear0_regs_init(); ipi_status0_regs_init(); -- 2.7.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support 2019-09-21 13:50 [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Huacai Chen 2019-09-21 13:50 ` [PATCH V2 2/3] MIPS: Loongson: Add Loongson-3A R4 basic support Huacai Chen 2019-09-21 13:50 ` [PATCH V2 3/3] MIPS: Loongson-3: Add CSR IPI support Huacai Chen @ 2019-10-07 17:51 ` Paul Burton 2019-10-08 7:09 ` Huacai Chen 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn 3 siblings, 1 reply; 13+ messages in thread From: Paul Burton @ 2019-10-07 17:51 UTC (permalink / raw) To: Huacai Chen Cc: Paul Burton, Ralf Baechle, James Hogan, linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Huacai Chen, Jiaxun Yang, linux-mips Hello, Huacai Chen wrote: > Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and > CSR (Control and Status Register) extensions. This patch add read/write > functionalities for them. Series applied to mips-next. > MIPS: Loongson: Add CFUCFG&CSR support > commit 6a6f9b7dafd5 > https://git.kernel.org/mips/c/6a6f9b7dafd5 > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Paul Burton <paul.burton@mips.com> > > MIPS: Loongson: Add Loongson-3A R4 basic support > commit 7507445b1993 > https://git.kernel.org/mips/c/7507445b1993 > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Signed-off-by: Paul Burton <paul.burton@mips.com> > > MIPS: Loongson-3: Add CSR IPI support > commit ffe59ee36aaa > https://git.kernel.org/mips/c/ffe59ee36aaa > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Paul Burton <paul.burton@mips.com> Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support 2019-10-07 17:51 ` [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Paul Burton @ 2019-10-08 7:09 ` Huacai Chen 2019-10-08 18:00 ` Paul Burton 0 siblings, 1 reply; 13+ messages in thread From: Huacai Chen @ 2019-10-08 7:09 UTC (permalink / raw) To: Paul Burton Cc: Paul Burton, Ralf Baechle, James Hogan, linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Jiaxun Yang Hi, Paul, I found that there is a typo in the title, please change CFUCFG to CPUCFG, thanks. Huacai On Tue, Oct 8, 2019 at 1:51 AM Paul Burton <paul.burton@mips.com> wrote: > > Hello, > > Huacai Chen wrote: > > Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and > > CSR (Control and Status Register) extensions. This patch add read/write > > functionalities for them. > > Series applied to mips-next. > > > MIPS: Loongson: Add CFUCFG&CSR support > > commit 6a6f9b7dafd5 > > https://git.kernel.org/mips/c/6a6f9b7dafd5 > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > > > MIPS: Loongson: Add Loongson-3A R4 basic support > > commit 7507445b1993 > > https://git.kernel.org/mips/c/7507445b1993 > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > > > MIPS: Loongson-3: Add CSR IPI support > > commit ffe59ee36aaa > > https://git.kernel.org/mips/c/ffe59ee36aaa > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > Thanks, > Paul > > [ This message was auto-generated; if you believe anything is incorrect > then please email paul.burton@mips.com to report it. ] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support 2019-10-08 7:09 ` Huacai Chen @ 2019-10-08 18:00 ` Paul Burton 2019-10-09 1:10 ` Jiaxun Yang 0 siblings, 1 reply; 13+ messages in thread From: Paul Burton @ 2019-10-08 18:00 UTC (permalink / raw) To: Huacai Chen Cc: Paul Burton, Ralf Baechle, James Hogan, linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu, Jiaxun Yang Hi Huacai, [Quote munged to fix top posting] On Tue, Oct 08, 2019 at 03:09:27PM +0800, Huacai Chen wrote: > Hi, Paul, > > On Tue, Oct 8, 2019 at 1:51 AM Paul Burton <paul.burton@mips.com> wrote: > > > > Hello, > > > > Huacai Chen wrote: > > > Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and > > > CSR (Control and Status Register) extensions. This patch add read/write > > > functionalities for them. > > > > Series applied to mips-next. > > > > > MIPS: Loongson: Add CFUCFG&CSR support > > > commit 6a6f9b7dafd5 > > > https://git.kernel.org/mips/c/6a6f9b7dafd5 > > > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > > > > > MIPS: Loongson: Add Loongson-3A R4 basic support > > > commit 7507445b1993 > > > https://git.kernel.org/mips/c/7507445b1993 > > > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > > > > > MIPS: Loongson-3: Add CSR IPI support > > > commit ffe59ee36aaa > > > https://git.kernel.org/mips/c/ffe59ee36aaa > > > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > > > Thanks, > > Paul > > > > [ This message was auto-generated; if you believe anything is incorrect > > then please email paul.burton@mips.com to report it. ] > > I found that there is a typo in the title, please change CFUCFG to > CPUCFG, thanks. > > Huacai It's too late for that - the email you replied to was telling you that the patches have already been applied to mips-next, and I'm not going to rewrite the mips-next branch for something so minor. Thanks, Paul ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support 2019-10-08 18:00 ` Paul Burton @ 2019-10-09 1:10 ` Jiaxun Yang 2019-10-09 1:37 ` Paul Burton 0 siblings, 1 reply; 13+ messages in thread From: Jiaxun Yang @ 2019-10-09 1:10 UTC (permalink / raw) To: Paul Burton, Huacai Chen Cc: Paul Burton, Ralf Baechle, James Hogan, linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu 于 2019年10月9日 GMT+08:00 上午2:00:26, Paul Burton <paul.burton@mips.com> 写到: >Hi Huacai, > >[Quote munged to fix top posting] > >On Tue, Oct 08, 2019 at 03:09:27PM +0800, Huacai Chen wrote: >> Hi, Paul, >> >> On Tue, Oct 8, 2019 at 1:51 AM Paul Burton <paul.burton@mips.com> >wrote: >> > >> > Hello, >> > >> > Huacai Chen wrote: >> > > Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU >config) and >> > > CSR (Control and Status Register) extensions. This patch add >read/write >> > > functionalities for them. >> > >> > Series applied to mips-next. >> > >> > > MIPS: Loongson: Add CFUCFG&CSR support >> > > commit 6a6f9b7dafd5 >> > > https://git.kernel.org/mips/c/6a6f9b7dafd5 >> > > >> > > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> > > Signed-off-by: Paul Burton <paul.burton@mips.com> >> > > >> > > MIPS: Loongson: Add Loongson-3A R4 basic support >> > > commit 7507445b1993 >> > > https://git.kernel.org/mips/c/7507445b1993 >> > > >> > > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> > > Signed-off-by: Paul Burton <paul.burton@mips.com> >> > > >> > > MIPS: Loongson-3: Add CSR IPI support >> > > commit ffe59ee36aaa >> > > https://git.kernel.org/mips/c/ffe59ee36aaa >> > > >> > > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> > > Signed-off-by: Paul Burton <paul.burton@mips.com> >> > >> > Thanks, >> > Paul >> > >> > [ This message was auto-generated; if you believe anything is >incorrect >> > then please email paul.burton@mips.com to report it. ] >> >> I found that there is a typo in the title, please change CFUCFG to >> CPUCFG, thanks. >> >> Huacai > >It's too late for that - the email you replied to was telling you that >the patches have already been applied to mips-next, and I'm not going >to >rewrite the mips-next branch for something so minor. Hi Paul, I think it is worthy to fix this by rewriting mips-next tree. As it haven't PR to upward next tree and this typo may lead to confusion in future when reviewing git log. > >Thanks, > Paul -- Jiaxun Yang ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support 2019-10-09 1:10 ` Jiaxun Yang @ 2019-10-09 1:37 ` Paul Burton 0 siblings, 0 replies; 13+ messages in thread From: Paul Burton @ 2019-10-09 1:37 UTC (permalink / raw) To: Jiaxun Yang Cc: Huacai Chen, Paul Burton, Ralf Baechle, James Hogan, linux-mips, linux-mips, Fuxin Zhang, Zhangjin Wu Hi Jiaxun, On Wed, Oct 09, 2019 at 09:10:57AM +0800, Jiaxun Yang wrote: > >> I found that there is a typo in the title, please change CFUCFG to > >> CPUCFG, thanks. > >> > >> Huacai > > > >It's too late for that - the email you replied to was telling you that > >the patches have already been applied to mips-next, and I'm not going > >to > >rewrite the mips-next branch for something so minor. > > Hi Paul, > > I think it is worthy to fix this by rewriting mips-next tree. As it > haven't PR to upward next tree and this typo may lead to confusion in > future when reviewing git log. I disagree. It's fairly common good practice to not rewrite history that has been shared. Quoting Documentation/process/7.AdvancedTopics.rst: > Excessive use of this capability can lead to other problems, though, > beyond a simple obsession for the creation of the perfect project > history. Rewriting history will rewrite the changes contained in that > history, turning a tested (hopefully) kernel tree into an untested > one. But, beyond that, developers cannot easily collaborate if they > do not have a shared view of the project history; if you rewrite > history which other developers have pulled into their repositories, > you will make life much more difficult for those developers. So a > simple rule of thumb applies here: history which has been exported to > others should generally be seen as immutable thereafter. > > So, once you push a set of changes to your publicly-available server, > those changes should not be rewritten. Git will attempt to enforce > this rule if you try to push changes which do not result in a > fast-forward merge (i.e. changes which do not share the same history). > It is possible to override this check, and there may be times when it > is necessary to rewrite an exported tree. Moving changesets between > trees to avoid conflicts in linux-next is one example. But such > actions should be rare. This is one of the reasons why development > should be done in private branches (which can be rewritten if > necessary) and only moved into public branches when it's in a > reasonably advanced state. Rewriting history can complicate things for developers working atop mips-next (which is something I want to encourage, not make difficult) and it would mean commit references such as those included in the "applied to mips-next" emails I send out would become incorrect. So when commts to mips-next are pushed to kernel.org, I generally won't change them unless there's something majorly wrong. A single character typo in a commit message doesn't count as majorly wrong, so no - I won't be rewriting history to fix it. Thanks, Paul ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] MIPS: Loongson: Fix GENMASK misuse 2019-09-21 13:50 [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Huacai Chen ` (2 preceding siblings ...) 2019-10-07 17:51 ` [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Paul Burton @ 2019-10-22 19:25 ` Rikard Falkeborn 2019-10-23 1:09 ` Huacai Chen ` (2 more replies) 3 siblings, 3 replies; 13+ messages in thread From: Rikard Falkeborn @ 2019-10-22 19:25 UTC (permalink / raw) To: chenhc Cc: chenhuacai, jhogan, jiaxun.yang, linux-mips, linux-mips, paul.burton, ralf, wuzhangjin, zhangfx, Rikard Falkeborn Arguments are supposed to be ordered high then low. Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> --- arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h index 6e3569ab8936..363a47a5d26e 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg) #define LOONGSON_CFG2_LGFTP BIT(19) #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) #define LOONGSON_CFG2_LLFTP BIT(23) -#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) +#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24) #define LOONGSON_CFG2_LCSRP BIT(27) #define LOONGSON_CFG2_LDISBLIKELY BIT(28) -- 2.23.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS: Loongson: Fix GENMASK misuse 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn @ 2019-10-23 1:09 ` Huacai Chen 2019-10-24 3:57 ` Paul Burton 2019-10-23 6:03 ` rb532, Kernel panic - not syncing: Fatal exception in interrupt Carlo Pisani 2019-10-24 5:02 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Paul Burton 2 siblings, 1 reply; 13+ messages in thread From: Huacai Chen @ 2019-10-23 1:09 UTC (permalink / raw) To: Rikard Falkeborn Cc: James Hogan, Jiaxun Yang, Linux MIPS Mailing List, open list:MIPS, Paul Burton, Ralf Baechle, wu zhangjin, zhangfx Reviewd-by: Huacai Chen <chenhc@lemote.com> Hi, Paul, I remember that the original patch has a typo "CFUCFG", and you said that you don't want to rewrite the history to just fix a typo. But now Rikard has found a real bug, could rewrite be possible? Huacai On Wed, Oct 23, 2019 at 3:26 AM Rikard Falkeborn <rikard.falkeborn@gmail.com> wrote: > > Arguments are supposed to be ordered high then low. > > Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") > Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> > --- > arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > index 6e3569ab8936..363a47a5d26e 100644 > --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h > +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > @@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg) > #define LOONGSON_CFG2_LGFTP BIT(19) > #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) > #define LOONGSON_CFG2_LLFTP BIT(23) > -#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) > +#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24) > #define LOONGSON_CFG2_LCSRP BIT(27) > #define LOONGSON_CFG2_LDISBLIKELY BIT(28) > > -- > 2.23.0 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS: Loongson: Fix GENMASK misuse 2019-10-23 1:09 ` Huacai Chen @ 2019-10-24 3:57 ` Paul Burton 0 siblings, 0 replies; 13+ messages in thread From: Paul Burton @ 2019-10-24 3:57 UTC (permalink / raw) To: Huacai Chen Cc: Rikard Falkeborn, James Hogan, Jiaxun Yang, Linux MIPS Mailing List, open list:MIPS, Paul Burton, Ralf Baechle, wu zhangjin, zhangfx Hi Huacai, On Wed, Oct 23, 2019 at 09:09:01AM +0800, Huacai Chen wrote: > Reviewd-by: Huacai Chen <chenhc@lemote.com> Thanks for the review (and as has been said many times, please stop top posting). > Hi, Paul, > > I remember that the original patch has a typo "CFUCFG", and you said > that you don't want to rewrite the history to just fix a typo. But now > Rikard has found a real bug, could rewrite be possible? No - I'm still not going to rewrite history. Yes, this LLFTPREV macro is wrong but it's also never even used so it's still not a big deal. When I said I'd only consider rewriting history for a major issue I meant it - something would need to be seriously broken for me to consider it, and even then I'm not promising I'd actually do it. Thanks, Paul > Huacai > > On Wed, Oct 23, 2019 at 3:26 AM Rikard Falkeborn > <rikard.falkeborn@gmail.com> wrote: > > > > Arguments are supposed to be ordered high then low. > > > > Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") > > Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> > > --- > > arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > index 6e3569ab8936..363a47a5d26e 100644 > > --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > @@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg) > > #define LOONGSON_CFG2_LGFTP BIT(19) > > #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) > > #define LOONGSON_CFG2_LLFTP BIT(23) > > -#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) > > +#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24) > > #define LOONGSON_CFG2_LCSRP BIT(27) > > #define LOONGSON_CFG2_LDISBLIKELY BIT(28) > > > > -- > > 2.23.0 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* rb532, Kernel panic - not syncing: Fatal exception in interrupt 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn 2019-10-23 1:09 ` Huacai Chen @ 2019-10-23 6:03 ` Carlo Pisani 2019-10-24 5:02 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Paul Burton 2 siblings, 0 replies; 13+ messages in thread From: Carlo Pisani @ 2019-10-23 6:03 UTC (permalink / raw) To: linux-mips, linux-mips hi we have a rb532A router, running kernel 4.4.197. The miniPCI quad uart modules are installed During the test 1) /dev/ttyS5 was attached to Minicom, with a lot of traffic at 115200bps 2) a tftpboot server continuously received requests from clients and, we got this uc-rb532 ~ # CPU 0 Unable to handle kernel paging request at virtual address 425c2100, epc == 8041ecd8, ra == 8041ece0 Oops[#1]: CPU: 0 PID: 1398 Comm: minicom Not tainted 4.4.197-BlurryFishButt-rb532 #2 task: 835bda38 ti: 83768000 task.ti: 83768000 $ 0 : 00000000 1810e800 00000000 00000000 $ 4 : 425c2100 83cbd4f0 837aa9b4 0000b2cd $ 8 : 00000000 00000000 00000000 00000000 $12 : 0000b2cd 00000000 00175c88 00000000 $16 : 83cbd4f0 83cbd4f0 837aafa0 83cbd4f0 $20 : 00040000 836cf020 836cf020 80696cf0 $24 : 00000000 00000000 $28 : 83768000 83c079b0 00000000 8041ece0 Hi : 00000000 Lo : 0000001e epc : 8041ecd8 0x8041ecd8 ra : 8041ece0 0x8041ece0 Status: 1810e803 KERNEL EXL IE Cause : 80800008 (ExcCode 02) BadVA : 425c2100 PrId : 0001800a (MIPS 4Kc) Modules linked in: Process minicom (pid: 1398, threadinfo=83768000, task=835bda38, tls=77726470) Stack : 836cf020 836cf020 80696cf0 80180184 83cbd4f0 8041eb9c 00000000 00000000 83cbd4f0 8041ec00 837c88c4 83cbd4f0 83cbd4f0 837aa9b4 837aa9a0 8041ec3c 0000045a 00000000 00000002 00003833 836cf020 804a93b8 0082e818 00000000 806a0000 80648718 00000000 00000001 00000001 00000000 836cf020 83cbd4f0 837aa9b4 837aa9a0 00040000 836cf020 836cf020 80696cf0 00000000 804aca3c ... Call Trace:[<80180184>] 0x80180184 [<8041eb9c>] 0x8041eb9c [<8041ec00>] 0x8041ec00 [<8041ec3c>] 0x8041ec3c [<804a93b8>] 0x804a93b8 [<804aca3c>] 0x804aca3c [<8014e4dc>] 0x8014e4dc [<804b70c0>] 0x804b70c0 [<804b8c1c>] 0x804b8c1c [<80461c08>] 0x80461c08 [<8049039c>] 0x8049039c [<80490ac8>] 0x80490ac8 [<804902a0>] 0x804902a0 [<80490e70>] 0x80490e70 [<80423bc8>] 0x80423bc8 [<804904dc>] 0x804904dc [<8042c4b0>] 0x8042c4b0 [<805030cc>] 0x805030cc [<80461c08>] 0x80461c08 [<804e4e3c>] 0x804e4e3c [<805030cc>] 0x805030cc [<8042e9a0>] 0x8042e9a0 [<80502dec>] 0x80502dec [<80502bd8>] 0x80502bd8 [<804e34ac>] 0x804e34ac [<805030cc>] 0x805030cc [<805096d0>] 0x805096d0 [<8013cd24>] 0x8013cd24 [<80502c38>] 0x80502c38 [<80509d7c>] 0x80509d7c [<8050b098>] 0x8050b098 [<801686f0>] 0x801686f0 [<80509554>] 0x80509554 [<80461c08>] 0x80461c08 [<80461cac>] 0x80461cac [<8050328c>] 0x8050328c [<80141b8c>] 0x80141b8c [<8013cd24>] 0x8013cd24 [<80502c38>] 0x80502c38 [<8042c2d8>] 0x8042c2d8 [<80421ff0>] 0x80421ff0 [<8042e9a0>] 0x8042e9a0 [<803a16cc>] 0x803a16cc [<80334638>] 0x80334638 [<8042bbb4>] 0x8042bbb4 [<8042edc0>] 0x8042edc0 [<80120670>] 0x80120670 [<8016a868>] 0x8016a868 [<80151728>] 0x80151728 [<80120b08>] 0x80120b08 [<80105b44>] 0x80105b44 Code: 27bdffe8 afbf0014 afb00010 <0c107b14> 8c900000 1600fffd 02002025 8fbf0014 8fb00010 ---[ end trace 4f05eb314ec51065 ]--- Kernel panic - not syncing: Fatal exception in interrupt Rebooting in 2 seconds.. the same problem happened with kernel 4.9.91.running Minicom-v2.3-r2 ---- uc-rb532 ~ # dmesg Kernel command line: console=ttyS0,9600 gpio=16383 mem=64M kmac=00:0C:42:0E:8F:01 board=500r5 boot=1 root=/dev/sda3 initd korina mac = 00:0C:42:0E:8F:01 PID hash table entries: 256 (order: -2, 1024 bytes) Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 57840K/65536K available (4762K kernel code, 175K rwdata, 816K rodata, 188K init, 111K bss, 7696K reserved, 0K cma) NR_IRQS:256 Initializing IRQ's: 168 out of 256 calculating r4koff... 000c34f8(799992) CPU frequency 400.00 MHz clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 9556397797 ns sched_clock: 32 bits at 199MHz, resolution 5ns, wraps every 10737525757ns Calibrating delay loop... 397.82 BogoMIPS (lpj=795648) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns futex hash table entries: 256 (order: -1, 3072 bytes) NET: Registered protocol family 16 PCI: Initializing PCI SCSI subsystem initialized libata version 3.00 loaded. PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff] pci_bus 0000:00: root bus resource [io 0x18800000-0x188fffff] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [111d:0000] type 00 class 0x000000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x07ffffff pref] pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:02.0: [1106:3106] type 00 class 0x020000 pci 0000:00:02.0: reg 0x10: [io 0x0000-0x00ff] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x000000ff] pci 0000:00:02.0: supports D1 D2 pci 0000:00:02.0: PME# supported from D1 D2 D3hot D3cold pci 0000:00:03.0: [1106:3106] type 00 class 0x020000 pci 0000:00:03.0: reg 0x10: [io 0x0000-0x00ff] pci 0000:00:03.0: reg 0x14: [mem 0x00000000-0x000000ff] pci 0000:00:03.0: supports D1 D2 pci 0000:00:03.0: PME# supported from D1 D2 D3hot D3cold pci 0000:00:04.0: [168c:0029] type 00 class 0x028000 pci 0000:00:04.0: reg 0x10: [mem 0x00000000-0x0000ffff] pci 0000:00:04.0: PME# supported from D0 D3hot pci 0000:00:05.0: [1415:9501] type 00 class 0x070006 pci 0000:00:05.0: reg 0x10: [io 0x0000-0x001f] pci 0000:00:05.0: reg 0x14: [mem 0x00000000-0x00000fff] pci 0000:00:05.0: reg 0x18: [io 0x0000-0x001f] pci 0000:00:05.0: reg 0x1c: [mem 0x00000000-0x00000fff] pci 0000:00:05.0: supports D2 pci 0000:00:05.0: PME# supported from D0 D2 D3hot pci 0000:00:05.1: [1415:9500] type 00 class 0x000000 pci 0000:00:05.1: reg 0x10: [io 0x0000-0x0007] pci 0000:00:05.1: reg 0x14: [io 0x0000-0x0007] pci 0000:00:05.1: reg 0x18: [io 0x0000-0x001f] pci 0000:00:05.1: reg 0x1c: [mem 0x00000000-0x00000fff] pci 0000:00:05.1: supports D2 pci 0000:00:05.1: PME# supported from D0 D2 D3hot pci 0000:00:0a.0: [1415:9501] type 00 class 0x070006 pci 0000:00:0a.0: reg 0x10: [io 0x0000-0x001f] pci 0000:00:0a.0: reg 0x14: [mem 0x00000000-0x00000fff] pci 0000:00:0a.0: reg 0x18: [io 0x0000-0x001f] pci 0000:00:0a.0: reg 0x1c: [mem 0x00000000-0x00000fff] pci 0000:00:0a.0: supports D2 pci 0000:00:0a.0: PME# supported from D0 D2 D3hot pci 0000:00:0a.1: [1415:9500] type 00 class 0x000000 pci 0000:00:0a.1: reg 0x10: [io 0x0000-0x0007] pci 0000:00:0a.1: reg 0x14: [io 0x0000-0x0007] pci 0000:00:0a.1: reg 0x18: [io 0x0000-0x001f] pci 0000:00:0a.1: reg 0x1c: [mem 0x00000000-0x00000fff] pci 0000:00:0a.1: supports D2 pci 0000:00:0a.1: PME# supported from D0 D2 D3hot pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00 pci 0000:00:04.0: BAR 0: assigned [mem 0x50000000-0x5000ffff] pci 0000:00:05.0: BAR 1: assigned [mem 0x50010000-0x50010fff] pci 0000:00:05.0: BAR 3: assigned [mem 0x50011000-0x50011fff] pci 0000:00:0a.0: BAR 1: assigned [mem 0x50012000-0x50012fff] pci 0000:00:0a.0: BAR 3: assigned [mem 0x50013000-0x50013fff] pci 0000:00:02.0: BAR 0: assigned [io 0x18800000-0x188000ff] pci 0000:00:02.0: BAR 1: assigned [mem 0x50014000-0x500140ff] pci 0000:00:03.0: BAR 0: assigned [io 0x18800400-0x188004ff] pci 0000:00:03.0: BAR 1: assigned [mem 0x50014100-0x500141ff] pci 0000:00:05.0: BAR 0: assigned [io 0x18800800-0x1880081f] pci 0000:00:05.0: BAR 2: assigned [io 0x18800820-0x1880083f] pci 0000:00:0a.0: BAR 0: assigned [io 0x18800840-0x1880085f] pci 0000:00:0a.0: BAR 2: assigned [io 0x18800860-0x1880087f] clocksource: Switched to clocksource MIPS NET: Registered protocol family 2 TCP established hash table entries: 1024 (order: 0, 4096 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) TCP: Hash tables configured (established 1024 bind 1024) UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) NET: Registered protocol family 1 PCI: CLS 16 bytes, default 16 io scheduler noop registered io scheduler deadline registered (default) Serial: 8250/16550 driver, 9 ports, IRQ sharing disabled serial8250: ttyS0 at MMIO 0x0 (irq = 104, base_baud = 12499875) is a 16550A console [ttyS0] enabled console [ttyS0] disabled serial8250.0: ttyS0 at MMIO 0x0 (irq = 104, base_baud = 12499875) is a 16550A console [ttyS0] enabled PCI: Enabling device 0000:00:05.0 (0000 -> 0003) ttyS1: detected caps 00000700 should be 00000500 0000:00:05.0: ttyS1 at I/O 0x18800800 (irq = 143, base_baud = 115200) is a 16C950/954 ttyS2: detected caps 00000700 should be 00000500 0000:00:05.0: ttyS2 at I/O 0x18800808 (irq = 143, base_baud = 115200) is a 16C950/954 ttyS3: detected caps 00000700 should be 00000500 0000:00:05.0: ttyS3 at I/O 0x18800810 (irq = 143, base_baud = 115200) is a 16C950/954 ttyS4: detected caps 00000700 should be 00000500 0000:00:05.0: ttyS4 at I/O 0x18800818 (irq = 143, base_baud = 115200) is a 16C950/954 PCI: Enabling device 0000:00:0a.0 (0000 -> 0003) ttyS5: detected caps 00000700 should be 00000500 0000:00:0a.0: ttyS5 at I/O 0x18800840 (irq = 140, base_baud = 115200) is a 16C950/954 ttyS6: detected caps 00000700 should be 00000500 0000:00:0a.0: ttyS6 at I/O 0x18800848 (irq = 140, base_baud = 115200) is a 16C950/954 ttyS7: detected caps 00000700 should be 00000500 0000:00:0a.0: ttyS7 at I/O 0x18800850 (irq = 140, base_baud = 115200) is a 16C950/954 ttyS8: detected caps 00000700 should be 00000500 0000:00:0a.0: ttyS8 at I/O 0x18800858 (irq = 140, base_baud = 115200) is a 16C950/954 loop: module loaded nbd: registered device at major 43 null: module loaded scsi host0: pata-rb532-cf ata1: PATA max PIO4 irq 149 Ethernet Channel Bonding Driver: v3.7.1 (April 27, 2011) tun: Universal TUN/TAP device driver, 1.6 tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> ata1.00: CFA: HMS360404D5CF00, DN4OCA2A, max PIO4 ata1.00: 7999488 sectors, multi 0: LBA eth0: korina-0.10 04Mar2008 via_rhine: v1.10-LK1.5.1 2010-10-09 Written by Donald Becker PCI: Enabling device 0000:00:02.0 (0080 -> 0083) via-rhine 0000:00:02.0 eth1: VIA Rhine III at 0xc0012000, 00:0c:42:0e:8f:02, IRQ 142 via-rhine 0000:00:02.0 eth1: MII PHY found at address 1, status 0x786d advertising 05e1 Link 45e1 PCI: Enabling device 0000:00:03.0 (0080 -> 0083) via-rhine 0000:00:03.0 eth2: VIA Rhine III at 0xc0014100, 00:0c:42:0e:8f:03, IRQ 143 via-rhine 0000:00:03.0 eth2: MII PHY found at address 1, status 0x7869 advertising 05e1 Link 41e1 PCI: Enabling device 0000:00:04.0 (0000 -> 0002) ata1.00: configured for PIO4 scsi 0:0:0:0: Direct-Access ATA HMS360404D5CF00 CA2A PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 7999488 512-byte logical blocks: (4.10 GB/3.81 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA ath: EEPROM regdomain: 0x809c ath: EEPROM indicates we should expect a country code ath: doing EEPROM country->regdmn map search ath: country maps to regdmn code: 0x52 ath: Country alpha2 being used: CN ath: Regpair used: 0x52 ieee80211 phy0: Selected rate control algorithm 'minstrel_ht' sda: sda1 sda2 sda3 ieee80211 phy0: Atheros AR9280 Rev:2 mem=0xc0020000, irq=142 sd 0:0:0:0: [sda] Attached SCSI removable disk aoe: AoE v85 initialised. rc32434_wdt: Stopped watchdog timer rc32434_wdt: Watchdog Timer version 1.0, timer margin: 20 sec NET: Registered protocol family 26 Netfilter messages via NETLINK v0.30. nf_conntrack version 0.5.0 (903 buckets, 3612 max) nf_tables: (c) 2007-2009 Patrick McHardy <kaber@trash.net> nf_tables_compat: (c) 2012 Pablo Neira Ayuso <pablo@netfilter.org> xt_time: kernel timezone is -0000 ip_tables: (C) 2000-2006 Netfilter Core Team arp_tables: (C) 2002 David S. Miller NET: Registered protocol family 17 Bridge firewalling registered Ebtables v2.0 registered EXT4-fs (sda3): couldn't mount as ext3 due to feature incompatibilities EXT4-fs (sda3): INFO: recovery required on readonly filesystem EXT4-fs (sda3): write access will be enabled during recovery random: nonblocking pool is initialized EXT4-fs (sda3): recovery complete EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null) VFS: Mounted root (ext4 filesystem) readonly on device 8:3. Freeing unused kernel memory: 188K EXT4-fs (sda3): re-mounted. Opts: (null) EXT4-fs (sda3): re-mounted. Opts: ---- 00:00.0 Non-VGA unclassified device: Integrated Device Technology, Inc. Device 0000 Subsystem: Device 0214:011d Flags: bus master, 66MHz, medium devsel, latency 60, IRQ 140 Memory at <unassigned> (32-bit, prefetchable) I/O ports at <ignored> I/O ports at <ignored> 00:02.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] (rev 86) Subsystem: AST Research Inc Device 086c Flags: bus master, stepping, medium devsel, latency 64, IRQ 142 I/O ports at 18800000 [size=256] Memory at 50014000 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Kernel driver in use: via-rhine 00:03.0 Ethernet controller: VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] (rev 86) Subsystem: AST Research Inc Device 086c Flags: bus master, stepping, medium devsel, latency 64, IRQ 143 I/O ports at 18800400 [size=256] Memory at 50014100 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Kernel driver in use: via-rhine 00:04.0 Network controller: Atheros Communications Inc. Device 0029 (rev 01) Subsystem: Atheros Communications Inc. Device 2091 Flags: bus master, 66MHz, medium devsel, latency 168, IRQ 142 Memory at 50000000 (32-bit, non-prefetchable) [size=64K] Capabilities: [44] Power Management version 2 Kernel driver in use: ath9k 00:05.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) Subsystem: Oxford Semiconductor Ltd Device 0000 Flags: medium devsel, IRQ 143 I/O ports at 18800800 [size=32] Memory at 50010000 (32-bit, non-prefetchable) [size=4K] I/O ports at 18800820 [size=32] Memory at 50011000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Kernel driver in use: serial 00:05.1 Non-VGA unclassified device: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) Subsystem: Oxford Semiconductor Ltd Device 0000 Flags: medium devsel, IRQ 143 I/O ports at <unassigned> [disabled] I/O ports at <unassigned> [disabled] I/O ports at <unassigned> [disabled] Capabilities: [40] Power Management version 2 00:0a.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (rev 01) (prog-if 06 [) Subsystem: Oxford Semiconductor Ltd Device 0000 Flags: medium devsel, IRQ 140 I/O ports at 18800840 [size=32] Memory at 50012000 (32-bit, non-prefetchable) [size=4K] I/O ports at 18800860 [size=32] Memory at 50013000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Kernel driver in use: serial 00:0a.1 Non-VGA unclassified device: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) (rev 01) Subsystem: Oxford Semiconductor Ltd Device 0000 Flags: medium devsel, IRQ 140 I/O ports at <unassigned> [disabled] I/O ports at <unassigned> [disabled] I/O ports at <unassigned> [disabled] Capabilities: [40] Power Management version 2 ---- what do you think? besides, kernels > 4. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] MIPS: Loongson: Fix GENMASK misuse 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn 2019-10-23 1:09 ` Huacai Chen 2019-10-23 6:03 ` rb532, Kernel panic - not syncing: Fatal exception in interrupt Carlo Pisani @ 2019-10-24 5:02 ` Paul Burton 2 siblings, 0 replies; 13+ messages in thread From: Paul Burton @ 2019-10-24 5:02 UTC (permalink / raw) To: Rikard Falkeborn Cc: chenhc, chenhuacai, jhogan, jiaxun.yang, linux-mips, linux-mips, paul.burton, ralf, wuzhangjin, zhangfx, Rikard Falkeborn, linux-mips Hello, Rikard Falkeborn wrote: > Arguments are supposed to be ordered high then low. Applied to mips-next. > commit e02d026f08f1 > https://git.kernel.org/mips/c/e02d026f08f1 > > Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") > Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> > Reviewed-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Paul Burton <paulburton@kernel.org> Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paulburton@kernel.org to report it. ] ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-10-24 5:02 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-09-21 13:50 [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Huacai Chen 2019-09-21 13:50 ` [PATCH V2 2/3] MIPS: Loongson: Add Loongson-3A R4 basic support Huacai Chen 2019-09-21 13:50 ` [PATCH V2 3/3] MIPS: Loongson-3: Add CSR IPI support Huacai Chen 2019-10-07 17:51 ` [PATCH V2 1/3] MIPS: Loongson: Add CFUCFG&CSR support Paul Burton 2019-10-08 7:09 ` Huacai Chen 2019-10-08 18:00 ` Paul Burton 2019-10-09 1:10 ` Jiaxun Yang 2019-10-09 1:37 ` Paul Burton 2019-10-22 19:25 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Rikard Falkeborn 2019-10-23 1:09 ` Huacai Chen 2019-10-24 3:57 ` Paul Burton 2019-10-23 6:03 ` rb532, Kernel panic - not syncing: Fatal exception in interrupt Carlo Pisani 2019-10-24 5:02 ` [PATCH] MIPS: Loongson: Fix GENMASK misuse Paul Burton
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