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From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, manasi.d.navare@intel.com,
	ville.syrjala@linux.intel.com
Subject: [Intel-gfx] [PATCH 15/17] drm/i915/dg2: use 128b/132b transcoder DDI mode
Date: Wed, 18 Aug 2021 21:10:50 +0300	[thread overview]
Message-ID: <5e884a5108fe9897593b6d9a6e7011ddb795958e.1629310010.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1629310010.git.jani.nikula@intel.com>

128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.

Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.

Bspec: 50493
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8b8f5d679b72..1ee817348bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -505,7 +505,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 		temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 		temp |= (crtc_state->fdi_lanes - 1) << 1;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
-		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
+		if (crtc_state->port_clock > 1000000)
+			temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
+		else
+			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
 		if (DISPLAY_VER(dev_priv) >= 12) {
@@ -693,7 +696,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 		break;
 
 	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		ret = type == DRM_MODE_CONNECTOR_VGA;
+		if (IS_DG2(dev_priv))
+			/* 128b/132b */
+			ret = false;
+		else
+			/* FDI */
+			ret = type == DRM_MODE_CONNECTOR_VGA;
 		break;
 
 	default:
@@ -780,8 +788,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 		if ((tmp & port_mask) != ddi_select)
 			continue;
 
-		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
-		    TRANS_DDI_MODE_SELECT_DP_MST)
+		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
+		    (IS_DG2(dev_priv) &&
+		     (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 			mst_pipe_mask |= BIT(p);
 
 		*pipe_mask |= BIT(p);
@@ -3572,9 +3581,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
 		pipe_config->lane_count = 4;
 		break;
-	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-		pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
-		break;
 	case TRANS_DDI_MODE_SELECT_DP_SST:
 		if (encoder->type == INTEL_OUTPUT_EDP)
 			pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3603,6 +3609,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 			pipe_config->infoframes.enable |=
 				intel_hdmi_infoframes_enabled(encoder, pipe_config);
 		break;
+	case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
+		if (!IS_DG2(dev_priv)) {
+			/* FDI */
+			pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
+			break;
+		}
+		fallthrough; /* 128b/132b */
 	case TRANS_DDI_MODE_SELECT_DP_MST:
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
 		pipe_config->lane_count =
-- 
2.20.1


  parent reply	other threads:[~2021-08-18 18:12 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-18 18:10 [Intel-gfx] [PATCH 00/17] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 01/17] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula
2021-08-18 18:10   ` Jani Nikula
2021-08-19 16:51   ` Ville Syrjälä
2021-08-19 16:51     ` [Intel-gfx] " Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 02/17] drm/dp: use more of the extended receiver cap Jani Nikula
2021-08-18 18:10   ` Jani Nikula
2021-08-18 18:10 ` [PATCH 03/17] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula
2021-08-18 18:10   ` [Intel-gfx] " Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 04/17] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula
2021-08-18 18:10   ` Jani Nikula
2021-08-19 17:30   ` Ville Syrjälä
2021-08-19 17:30     ` [Intel-gfx] " Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 05/17] drm/i915/dp: use actual link rate values in struct link_config_limits Jani Nikula
2021-08-19 17:34   ` Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 06/17] drm/i915/dp: read sink UHBR rates Jani Nikula
2021-08-19 17:45   ` Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 07/17] drm/i915/dg2: add TRANS_DP2_CTL register definition Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 08/17] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 09/17] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 10/17] drm/i915/dg2: add DG2 UHBR source rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 11/17] drm/i915/dp: add max data rate calculation for UHBR rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 12/17] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 13/17] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
2021-08-19 17:49   ` Ville Syrjälä
2021-08-20  6:36     ` Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 14/17] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
2021-08-18 18:10 ` Jani Nikula [this message]
2021-08-19 17:54   ` [Intel-gfx] [PATCH 15/17] drm/i915/dg2: use 128b/132b transcoder DDI mode Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 16/17] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 17/17] drm/i915/dg2: update link training " Jani Nikula
2021-08-18 20:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work Patchwork
2021-08-18 20:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-18 20:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork

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