From: "Ville Syrjälä" <ville.syrjala@linux.intel.com> To: Jani Nikula <jani.nikula@intel.com> Cc: intel-gfx@lists.freedesktop.org, manasi.d.navare@intel.com, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 04/17] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Date: Thu, 19 Aug 2021 20:30:30 +0300 [thread overview] Message-ID: <YR6VNnGfUcrYB1gn@intel.com> (raw) In-Reply-To: <b287d95f995cd48143e2e14fa21b431e0cd9ee78.1629310010.git.jani.nikula@intel.com> On Wed, Aug 18, 2021 at 09:10:39PM +0300, Jani Nikula wrote: > The DP 2.0 128b/132b channel coding uses TX FFE presets instead of > vswing and pre-emphasis. > > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++ > include/drm/drm_dp_helper.h | 2 ++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index 9389f92cb944..2843238a78e6 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI > } > EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); > > +/* DP 2.0 128b/132b */ > +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > + int lane) > +{ > + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); > + int s = ((lane & 1) ? > + DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : > + DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); > + u8 l = dp_link_status(link_status, i); > + > + return (l >> s) & 0xf; > +} > +EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); > + > u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > unsigned int lane) > { > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index f3a61341011d..3ee0b3ffb8a5 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane); > u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane); > +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > + int lane); > u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > unsigned int lane); > > -- > 2.20.1 -- Ville Syrjälä Intel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com> To: Jani Nikula <jani.nikula@intel.com> Cc: intel-gfx@lists.freedesktop.org, manasi.d.navare@intel.com, dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 04/17] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Date: Thu, 19 Aug 2021 20:30:30 +0300 [thread overview] Message-ID: <YR6VNnGfUcrYB1gn@intel.com> (raw) In-Reply-To: <b287d95f995cd48143e2e14fa21b431e0cd9ee78.1629310010.git.jani.nikula@intel.com> On Wed, Aug 18, 2021 at 09:10:39PM +0300, Jani Nikula wrote: > The DP 2.0 128b/132b channel coding uses TX FFE presets instead of > vswing and pre-emphasis. > > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++ > include/drm/drm_dp_helper.h | 2 ++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index 9389f92cb944..2843238a78e6 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI > } > EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); > > +/* DP 2.0 128b/132b */ > +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > + int lane) > +{ > + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); > + int s = ((lane & 1) ? > + DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : > + DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); > + u8 l = dp_link_status(link_status, i); > + > + return (l >> s) & 0xf; > +} > +EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); > + > u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > unsigned int lane) > { > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index f3a61341011d..3ee0b3ffb8a5 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane); > u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], > int lane); > +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], > + int lane); > u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], > unsigned int lane); > > -- > 2.20.1 -- Ville Syrjälä Intel
next prev parent reply other threads:[~2021-08-19 17:30 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-18 18:10 [Intel-gfx] [PATCH 00/17] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 01/17] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula 2021-08-18 18:10 ` Jani Nikula 2021-08-19 16:51 ` Ville Syrjälä 2021-08-19 16:51 ` [Intel-gfx] " Ville Syrjälä 2021-08-18 18:10 ` [Intel-gfx] [PATCH 02/17] drm/dp: use more of the extended receiver cap Jani Nikula 2021-08-18 18:10 ` Jani Nikula 2021-08-18 18:10 ` [PATCH 03/17] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] " Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 04/17] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula 2021-08-18 18:10 ` Jani Nikula 2021-08-19 17:30 ` Ville Syrjälä [this message] 2021-08-19 17:30 ` [Intel-gfx] " Ville Syrjälä 2021-08-18 18:10 ` [Intel-gfx] [PATCH 05/17] drm/i915/dp: use actual link rate values in struct link_config_limits Jani Nikula 2021-08-19 17:34 ` Ville Syrjälä 2021-08-18 18:10 ` [Intel-gfx] [PATCH 06/17] drm/i915/dp: read sink UHBR rates Jani Nikula 2021-08-19 17:45 ` Ville Syrjälä 2021-08-18 18:10 ` [Intel-gfx] [PATCH 07/17] drm/i915/dg2: add TRANS_DP2_CTL register definition Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 08/17] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 09/17] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 10/17] drm/i915/dg2: add DG2 UHBR source rates Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 11/17] drm/i915/dp: add max data rate calculation for UHBR rates Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 12/17] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 13/17] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula 2021-08-19 17:49 ` Ville Syrjälä 2021-08-20 6:36 ` Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 14/17] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 15/17] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula 2021-08-19 17:54 ` Ville Syrjälä 2021-08-18 18:10 ` [Intel-gfx] [PATCH 16/17] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula 2021-08-18 18:10 ` [Intel-gfx] [PATCH 17/17] drm/i915/dg2: update link training " Jani Nikula 2021-08-18 20:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work Patchwork 2021-08-18 20:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-08-18 20:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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