From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, manasi.d.navare@intel.com,
ville.syrjala@linux.intel.com
Subject: [Intel-gfx] [PATCH 00/17] drm/i915/dp: dp 2.0 enabling prep work
Date: Wed, 18 Aug 2021 21:10:35 +0300 [thread overview]
Message-ID: <cover.1629310010.git.jani.nikula@intel.com> (raw)
Start enabling DP 2.0 features. It's not complete, but it's a good
start, and should not conflict with anything existing.
Jani Nikula (17):
drm/dp: add DP 2.0 UHBR link rate and bw code conversions
drm/dp: use more of the extended receiver cap
drm/dp: add LTTPR DP 2.0 DPCD addresses
drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
drm/i915/dp: use actual link rate values in struct link_config_limits
drm/i915/dp: read sink UHBR rates
drm/i915/dg2: add TRANS_DP2_CTL register definition
drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
drm/i915/dg2: add DG2 UHBR source rates
drm/i915/dp: add max data rate calculation for UHBR rates
drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
drm/i915/dp: select 128b/132b channel encoding for UHBR rates
drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
drm/i915/dg2: use 128b/132b transcoder DDI mode
drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b
drm/i915/dg2: update link training for 128b/132b
drivers/gpu/drm/drm_dp_helper.c | 42 ++++++-
drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++---
drivers/gpu/drm/i915/display/intel_dp.c | 109 ++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 4 +-
.../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++-----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++-
drivers/gpu/drm/i915/i915_reg.h | 25 +++-
include/drm/drm_dp_helper.h | 6 +
8 files changed, 289 insertions(+), 74 deletions(-)
--
2.20.1
next reply other threads:[~2021-08-18 18:11 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 18:10 Jani Nikula [this message]
2021-08-18 18:10 ` [Intel-gfx] [PATCH 01/17] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula
2021-08-18 18:10 ` Jani Nikula
2021-08-19 16:51 ` Ville Syrjälä
2021-08-19 16:51 ` [Intel-gfx] " Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 02/17] drm/dp: use more of the extended receiver cap Jani Nikula
2021-08-18 18:10 ` Jani Nikula
2021-08-18 18:10 ` [PATCH 03/17] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] " Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 04/17] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula
2021-08-18 18:10 ` Jani Nikula
2021-08-19 17:30 ` Ville Syrjälä
2021-08-19 17:30 ` [Intel-gfx] " Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 05/17] drm/i915/dp: use actual link rate values in struct link_config_limits Jani Nikula
2021-08-19 17:34 ` Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 06/17] drm/i915/dp: read sink UHBR rates Jani Nikula
2021-08-19 17:45 ` Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 07/17] drm/i915/dg2: add TRANS_DP2_CTL register definition Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 08/17] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 09/17] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 10/17] drm/i915/dg2: add DG2 UHBR source rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 11/17] drm/i915/dp: add max data rate calculation for UHBR rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 12/17] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 13/17] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
2021-08-19 17:49 ` Ville Syrjälä
2021-08-20 6:36 ` Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 14/17] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 15/17] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
2021-08-19 17:54 ` Ville Syrjälä
2021-08-18 18:10 ` [Intel-gfx] [PATCH 16/17] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
2021-08-18 18:10 ` [Intel-gfx] [PATCH 17/17] drm/i915/dg2: update link training " Jani Nikula
2021-08-18 20:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work Patchwork
2021-08-18 20:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-18 20:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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