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* [PATCH] drm/amdgpu: always flush the TLB on gfx8
@ 2022-06-03 13:05 Christian König
  2022-06-03 13:44 ` Pierre-Eric Pelloux-Prayer
  2022-06-07 20:27 ` Alex Deucher
  0 siblings, 2 replies; 6+ messages in thread
From: Christian König @ 2022-06-03 13:05 UTC (permalink / raw)
  To: Arunpravin.PaneerSelvam, amd-gfx

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9596c22fded6..b747488c28ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+	/*
+	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+	 */
+	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
 	params.vm = vm;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: always flush the TLB on gfx8
  2022-06-03 13:05 [PATCH] drm/amdgpu: always flush the TLB on gfx8 Christian König
@ 2022-06-03 13:44 ` Pierre-Eric Pelloux-Prayer
  2022-06-07 20:27 ` Alex Deucher
  1 sibling, 0 replies; 6+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2022-06-03 13:44 UTC (permalink / raw)
  To: Christian König, Arunpravin.PaneerSelvam, amd-gfx

Hi Christian,

This patch fixes almost all GPU faults on polaris caused by 86fd5edfbdae "drm/amdgpu: rework TLB flushing".

I still get occasional faults though, about 1 every 3 runs of a subset of piglit tests.

Thanks,
Pierre-Eric



On 03/06/2022 15:05, Christian König wrote:
> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
> are set.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 9596c22fded6..b747488c28ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
>  		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
>  
> +	/*
> +	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
> +	 */
> +	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
> +
>  	memset(&params, 0, sizeof(params));
>  	params.adev = adev;
>  	params.vm = vm;
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: always flush the TLB on gfx8
  2022-06-03 13:05 [PATCH] drm/amdgpu: always flush the TLB on gfx8 Christian König
  2022-06-03 13:44 ` Pierre-Eric Pelloux-Prayer
@ 2022-06-07 20:27 ` Alex Deucher
  2022-06-08 13:58   ` Christian König
  1 sibling, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2022-06-07 20:27 UTC (permalink / raw)
  To: Christian König; +Cc: amd-gfx list, Arunpravin

On Fri, Jun 3, 2022 at 9:05 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
> are set.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 9596c22fded6..b747488c28ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>         flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
>                      adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
>
> +       /*
> +        * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
> +        */
> +       flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
> +
>         memset(&params, 0, sizeof(params));
>         params.adev = adev;
>         params.vm = vm;
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: always flush the TLB on gfx8
  2022-06-07 20:27 ` Alex Deucher
@ 2022-06-08 13:58   ` Christian König
  2022-06-08 14:03     ` Alex Deucher
  0 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2022-06-08 13:58 UTC (permalink / raw)
  To: Alex Deucher; +Cc: amd-gfx list, Arunpravin

Am 07.06.22 um 22:27 schrieb Alex Deucher:
> On Fri, Jun 3, 2022 at 9:05 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
>> are set.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex could you push this? It's an important fix, but I'm seriously not 
feeling well at the moment.

Thanks,
Christian.

>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 9596c22fded6..b747488c28ad 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>          flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
>>                       adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
>>
>> +       /*
>> +        * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
>> +        */
>> +       flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
>> +
>>          memset(&params, 0, sizeof(params));
>>          params.adev = adev;
>>          params.vm = vm;
>> --
>> 2.25.1
>>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: always flush the TLB on gfx8
  2022-06-08 13:58   ` Christian König
@ 2022-06-08 14:03     ` Alex Deucher
  0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2022-06-08 14:03 UTC (permalink / raw)
  To: Christian König; +Cc: amd-gfx list, Arunpravin

yes. will do.

Alex

On Wed, Jun 8, 2022 at 9:58 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 07.06.22 um 22:27 schrieb Alex Deucher:
> > On Fri, Jun 3, 2022 at 9:05 AM Christian König
> > <ckoenig.leichtzumerken@gmail.com> wrote:
> >> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
> >> are set.
> >>
> >> Signed-off-by: Christian König <christian.koenig@amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Alex could you push this? It's an important fix, but I'm seriously not
> feeling well at the moment.
>
> Thanks,
> Christian.
>
> >
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
> >>   1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> index 9596c22fded6..b747488c28ad 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> @@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> >>          flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
> >>                       adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
> >>
> >> +       /*
> >> +        * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
> >> +        */
> >> +       flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
> >> +
> >>          memset(&params, 0, sizeof(params));
> >>          params.adev = adev;
> >>          params.vm = vm;
> >> --
> >> 2.25.1
> >>
>

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] drm/amdgpu: always flush the TLB on gfx8
@ 2022-06-03 13:05 Christian König
  0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2022-06-03 13:05 UTC (permalink / raw)
  To: pierre-eric.pelloux-prayer, amd-gfx

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9596c22fded6..b747488c28ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+	/*
+	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+	 */
+	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
 	params.vm = vm;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-06-08 14:03 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-03 13:05 [PATCH] drm/amdgpu: always flush the TLB on gfx8 Christian König
2022-06-03 13:44 ` Pierre-Eric Pelloux-Prayer
2022-06-07 20:27 ` Alex Deucher
2022-06-08 13:58   ` Christian König
2022-06-08 14:03     ` Alex Deucher
2022-06-03 13:05 Christian König

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