[PATCH v3 00/18] Multiple addition to ipq8064 dtsi

[PATCH v3 00/18] Multiple addition to ipq8064 dtsi

[Ansuel Smith]

This try to complete the ipq8064 dtsi and introduce 2 new dtsi
ipq8064-v2 and ipq8065. While some node are still missing (cpufreq node,
l2 scale node, fab scale node) this would add most of the missing node
to make ipq8064 actually usable.

Some of the changes are the fix for the pci IO that cause any secondary
wifi card with ath10k to fail init.
Adds regulators definition for RPM.
Adds many missing gsbi nodes used by all the devices.
Enable the usb phy by default as they are actually enabled internally by
xlate only if the dwc3 driver is used.
Add opp table and declare idle state for ipq8064.
Fix some dtc warning.

This also add the ipq8064-v2.0 dtsi and the ipq8065 dtsi used by more
recent devices based on this SoC.

v3:
- Fix error in rb3011 dts
- Add tested-by tag on the entire series
v2:
- Added missing patch
- Added additional gsbi6 spi
- Added extra description for L2 cache opp
- Fxied smb208 enabled by default that is problematic for rb3011 devices

Ansuel Smith (18):
  ARM: dts: qcom: add multiple missing pin definition for ipq8064
  ARM: dts: qcom: add gsbi6 missing definition for ipq8064
  ARM: dts: qcom: add missing rpm regulators and cells for ipq8064
  ARM: dts: qcom: disable smb208 regulators for ipq8064-rb3011
  ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
  ARM: dts: qcom: enable usb phy by default for ipq8064
  ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
  ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064
  ARM: dts: qcom: add smem node for ipq8064
  ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064
  ARM: dts: qcom: add sic non secure node for ipq8064
  ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
  ARM: dts: qcom: add opp table for cpu and l2 for ipq8064
  ARM: dts: qcom: add speedbin efuse nvmem binding
  ARM: dts: qcom: add multiple missing binding for cpu and l2 for
    ipq8064
  ARM: dts: qcom: remove redundant binding from ipq8064 rb3011 dts
  ARM: dts: qcom: add ipq8064-v2.0 dtsi
  ARM: dts: qcom: add ipq8065 dtsi

 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts |  21 +-
 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi  |  70 ++++
 arch/arm/boot/dts/qcom-ipq8064.dtsi       | 375 +++++++++++++++++++++-
 arch/arm/boot/dts/qcom-ipq8065.dtsi       | 168 ++++++++++
 4 files changed, 603 insertions(+), 31 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi

-- 
2.34.1

[PATCH v3 01/18] ARM: dts: qcom: add multiple missing pin definition for ipq8064

[Ansuel Smith]

Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
pins and rgmii2 pins for ipq8064.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 11481313bdb6..cc6ca9013ab1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -382,6 +382,15 @@ mux {
 				};
 			};
 
+			i2c4_pins: i2c4_pinmux {
+				mux {
+					pins = "gpio12", "gpio13";
+					function = "gsbi4";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
+
 			spi_pins: spi_pins {
 				mux {
 					pins = "gpio18", "gpio19", "gpio21";
@@ -424,6 +433,8 @@ mux {
 
 				pullups {
 					pins = "gpio39";
+					function = "nand";
+					drive-strength = <10>;
 					bias-pull-up;
 				};
 
@@ -431,9 +442,32 @@ hold {
 					pins = "gpio40", "gpio41", "gpio42",
 					       "gpio43", "gpio44", "gpio45",
 					       "gpio46", "gpio47";
+					function = "nand";
+					drive-strength = <10>;
 					bias-bus-hold;
 				};
 			};
+
+			mdio0_pins: mdio0_pins {
+				mux {
+					pins = "gpio0", "gpio1";
+					function = "mdio";
+					drive-strength = <8>;
+					bias-disable;
+				};
+			};
+
+			rgmii2_pins: rgmii2_pins {
+				mux {
+					pins = "gpio27", "gpio28", "gpio29",
+					       "gpio30", "gpio31", "gpio32",
+					       "gpio51", "gpio52", "gpio59",
+					       "gpio60", "gpio61", "gpio62";
+					function = "rgmii2";
+					drive-strength = <8>;
+					bias-disable;
+				};
+			};
 		};
 
 		intc: interrupt-controller@2000000 {
-- 
2.34.1

[PATCH v3 02/18] ARM: dts: qcom: add gsbi6 missing definition for ipq8064

[Ansuel Smith]

Add gsbi6 missing definition for ipq8064.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 40 +++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cc6ca9013ab1..b309bc0fbbcd 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -665,6 +665,46 @@ spi@1a280000 {
 			};
 		};
 
+		gsbi6: gsbi@16500000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <6>;
+			reg = <0x16500000 0x100>;
+			clocks = <&gcc GSBI6_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi6_i2c: i2c@16580000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x16580000 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			gsbi6_spi: spi@16580000 {
+				compatible = "qcom,spi-qup-v1.1.1";
+				reg = <0x16580000 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gsbi7: gsbi@16600000 {
 			status = "disabled";
 			compatible = "qcom,gsbi-v1.0.0";
-- 
2.34.1

[PATCH v3 03/18] ARM: dts: qcom: add missing rpm regulators and cells for ipq8064

[Ansuel Smith]

Add cells definition for rpm node and add missing regulators for the 4
regulator present on ipq8064. There regulators are controlled by rpm and
to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
reject any regulator change request.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index b309bc0fbbcd..0938838a4af8 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -842,10 +842,46 @@ rpm: rpm@108000 {
 			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 			clock-names = "ram";
 
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			rpmcc: clock-controller {
 				compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 				#clock-cells = <1>;
 			};
+
+			smb208_regulators: regulators {
+				compatible = "qcom,rpm-smb208-regulators";
+				status = "okay";
+
+				smb208_s1a: s1a {
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1150000>;
+
+					qcom,switch-mode-frequency = <1200000>;
+				};
+
+				smb208_s1b: s1b {
+					regulator-min-microvolt = <1050000>;
+					regulator-max-microvolt = <1150000>;
+
+					qcom,switch-mode-frequency = <1200000>;
+				};
+
+				smb208_s2a: s2a {
+					regulator-min-microvolt = < 800000>;
+					regulator-max-microvolt = <1250000>;
+
+					qcom,switch-mode-frequency = <1200000>;
+				};
+
+				smb208_s2b: s2b {
+					regulator-min-microvolt = < 800000>;
+					regulator-max-microvolt = <1250000>;
+
+					qcom,switch-mode-frequency = <1200000>;
+				};
+			};
 		};
 
 		tcsr: syscon@1a400000 {
-- 
2.34.1

[PATCH v3 04/18] ARM: dts: qcom: disable smb208 regulators for ipq8064-rb3011

[Ansuel Smith]

Mikrotik RB3011 have a special configuration where the regulators are
not the common smb208 controlled by RPM but they use a TPS563900
controlled via i2c. Disable the smb208 for this specific device.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Jonathan McDowell <noodles@earth.li>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 596d129d4a95..611a4a19631c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -216,6 +216,10 @@ led@7 {
 	};
 };
 
+&smb208_regulators {
+	status = "disabled";
+};
+
 &adm_dma {
 	status = "okay";
 };
-- 
2.34.1

[PATCH v3 05/18] ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064

[Ansuel Smith]

Add missing snps,dwmac compatible for gmac ipq8064 dtsi.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 0938838a4af8..9d658fcc1f12 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1075,7 +1075,7 @@ stmmac_axi_setup: stmmac-axi-config {
 
 		gmac0: ethernet@37000000 {
 			device_type = "network";
-			compatible = "qcom,ipq806x-gmac";
+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 			reg = <0x37000000 0x200000>;
 			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
@@ -1099,7 +1099,7 @@ gmac0: ethernet@37000000 {
 
 		gmac1: ethernet@37200000 {
 			device_type = "network";
-			compatible = "qcom,ipq806x-gmac";
+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 			reg = <0x37200000 0x200000>;
 			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
@@ -1123,7 +1123,7 @@ gmac1: ethernet@37200000 {
 
 		gmac2: ethernet@37400000 {
 			device_type = "network";
-			compatible = "qcom,ipq806x-gmac";
+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 			reg = <0x37400000 0x200000>;
 			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
@@ -1147,7 +1147,7 @@ gmac2: ethernet@37400000 {
 
 		gmac3: ethernet@37600000 {
 			device_type = "network";
-			compatible = "qcom,ipq806x-gmac";
+			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 			reg = <0x37600000 0x200000>;
 			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
-- 
2.34.1

[PATCH v3 06/18] ARM: dts: qcom: enable usb phy by default for ipq8064

[Ansuel Smith]

Enable usb phy by default. When the usb phy were pushed, half of them
were flagged as disabled by mistake. Fix this to correctly init dwc3
node on any ipq8064 based SoC.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9d658fcc1f12..e247bf51df01 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1175,8 +1175,6 @@ hs_phy_0: phy@100f8800 {
 			clocks = <&gcc USB30_0_UTMI_CLK>;
 			clock-names = "ref";
 			#phy-cells = <0>;
-
-			status = "disabled";
 		};
 
 		ss_phy_0: phy@100f8830 {
@@ -1185,8 +1183,6 @@ ss_phy_0: phy@100f8830 {
 			clocks = <&gcc USB30_0_MASTER_CLK>;
 			clock-names = "ref";
 			#phy-cells = <0>;
-
-			status = "disabled";
 		};
 
 		usb3_0: usb3@100f8800 {
-- 
2.34.1

[PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

[Ansuel Smith]

The current value for pci IO is problematic for ath10k wifi card
commonly connected to ipq8064 SoC.
The current value is probably a typo and is actually uncommon to find
1MB IO space even on a x86 arch. Also with recent changes to the pci
driver, pci1 and pci2 now fails to function as any connected device
fails any reg read/write. Reduce this to 64K as it should be more than
enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
hardcoded for the ARM arch.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e247bf51df01..36bdfc8db3f0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 
-			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
+			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
 				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 
-			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
+			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
 				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 
 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
 			#address-cells = <3>;
 			#size-cells = <2>;
 
-			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
+			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
 				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.34.1

[PATCH v3 08/18] ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064

[Ansuel Smith]

Fix dtc warning for missing #address-cells for ipq8064.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 36bdfc8db3f0..6768f7ba0d04 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -352,6 +352,7 @@ qcom_pinmux: pinmux@800000 {
 			gpio-ranges = <&qcom_pinmux 0 0 69>;
 			#gpio-cells = <2>;
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -473,6 +474,7 @@ mux {
 		intc: interrupt-controller@2000000 {
 			compatible = "qcom,msm-qgic2";
 			interrupt-controller;
+			#address-cells = <0>;
 			#interrupt-cells = <3>;
 			reg = <0x02000000 0x1000>,
 			      <0x02002000 0x1000>;
-- 
2.34.1

[PATCH v3 09/18] ARM: dts: qcom: add smem node for ipq8064

[Ansuel Smith]

Add missing smem node for ipq8064.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 6768f7ba0d04..c579fb09e768 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -906,6 +906,11 @@ lcc: clock-controller@28000000 {
 			#reset-cells = <1>;
 		};
 
+		sfpb_mutex_block: syscon@1200600 {
+			compatible = "syscon";
+			reg = <0x01200600 0x100>;
+		};
+
 		pcie0: pci@1b500000 {
 			compatible = "qcom,pcie-ipq8064";
 			reg = <0x1b500000 0x1000
@@ -1330,4 +1335,17 @@ sdcc3: mmc@12180000 {
 			};
 		};
 	};
+
+	sfpb_mutex: sfpb-mutex {
+		compatible = "qcom,sfpb-mutex";
+		syscon = <&sfpb_mutex_block 4 4>;
+
+		#hwlock-cells = <1>;
+	};
+
+	smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem>;
+		hwlocks = <&sfpb_mutex 3>;
+	};
 };
-- 
2.34.1

[PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

[Ansuel Smith]

Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
for the secondary mux.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index c579fb09e768..7df1c1482220 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -298,6 +298,12 @@ smem: smem@41000000 {
 	};
 
 	clocks {
+		qsb: qsb {
+			compatible = "fixed-clock";
+			clock-frequency = <384000000>;
+			#clock-cells = <0>;
+		};
+
 		cxo_board {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -504,11 +510,19 @@ IRQ_TYPE_EDGE_RISING)>,
 		acc0: clock-controller@2088000 {
 			compatible = "qcom,kpss-acc-v1";
 			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+			clock-output-names = "acpu0_aux";
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			#clock-cells = <0>;
 		};
 
 		acc1: clock-controller@2098000 {
 			compatible = "qcom,kpss-acc-v1";
 			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+			clock-output-names = "acpu1_aux";
+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+			clock-names = "pll8_vote", "pxo";
+			#clock-cells = <0>;
 		};
 
 		adm_dma: dma-controller@18300000 {
@@ -532,17 +546,23 @@ adm_dma: dma-controller@18300000 {
 		};
 
 		saw0: regulator@2089000 {
-			compatible = "qcom,saw2";
+			compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
 		saw1: regulator@2099000 {
-			compatible = "qcom,saw2";
+			compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 			regulator;
 		};
 
+		saw_l2: regulator@02012000 {
+			compatible = "qcom,saw2", "syscon";
+			reg = <0x02012000 0x1000>;
+			regulator;
+		};
+
 		gsbi2: gsbi@12480000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <2>;
@@ -899,6 +919,16 @@ l2cc: clock-controller@2011000 {
 			clock-output-names = "acpu_l2_aux";
 		};
 
+		kraitcc: clock-controller {
+			compatible = "qcom,krait-cc-v1";
+			clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
+				 <&acc0>, <&acc1>, <&l2cc>, <&qsb>;
+			clock-names = "hfpll0", "hfpll1", "hfpll_l2",
+				      "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
+				      "qsb";
+			#clock-cells = <1>;
+		};
+
 		lcc: clock-controller@28000000 {
 			compatible = "qcom,lcc-ipq8064";
 			reg = <0x28000000 0x1000>;
-- 
2.34.1

[PATCH v3 11/18] ARM: dts: qcom: add sic non secure node for ipq8064

[Ansuel Smith]

Add missing sic non secure node for ipq8064.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 7df1c1482220..df2702e6136d 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -563,6 +563,11 @@ saw_l2: regulator@02012000 {
 			regulator;
 		};
 
+		sic_non_secure: sic-non-secure@12100000 {
+			compatible = "syscon";
+			reg = <0x12100000 0x10000>;
+		};
+
 		gsbi2: gsbi@12480000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <2>;
-- 
2.34.1

[PATCH v3 12/18] ARM: dts: qcom: fix and add some missing gsbi node for ipq8064

[Ansuel Smith]

Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
gsbi7 i2c node and gsbi1 node.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 50 ++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index df2702e6136d..7dd0b901cd30 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -568,6 +568,41 @@ sic_non_secure: sic-non-secure@12100000 {
 			reg = <0x12100000 0x10000>;
 		};
 
+		gsbi1: gsbi@12440000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <1>;
+			reg = <0x12440000 0x100>;
+			clocks = <&gcc GSBI1_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi1_serial: serial@12450000 {
+				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+				reg = <0x12450000 0x100>,
+				      <0x12400000 0x03>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+			};
+
+			gsbi1_i2c: i2c@12460000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x12460000 0x1000>;
+				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		gsbi2: gsbi@12480000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <2>;
@@ -591,7 +626,7 @@ gsbi2_serial: serial@12490000 {
 				status = "disabled";
 			};
 
-			i2c@124a0000 {
+			gsbi2_i2c: i2c@124a0000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x124a0000 0x1000>;
 				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -753,6 +788,19 @@ gsbi7_serial: serial@16640000 {
 				clock-names = "core", "iface";
 				status = "disabled";
 			};
+
+			gsbi7_i2c: i2c@16680000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x16680000 0x1000>;
+				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		rng@1a500000 {
-- 
2.34.1

[PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for ipq8064

[Ansuel Smith]

Add opp table for cpu and l2 cache. While the current cpufreq is
the generic one that doesn't scale the L2 cache, we add the l2
cache opp anyway for the sake of completeness. This will be handy in the
future when a dedicated cpufreq driver is introduced for krait cores
that will correctly scale l2 cache with the core freq.

Opp-level is set based on the logic of
0: idle level
1: normal level
2: turbo level

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 7dd0b901cd30..a1079583def9 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -48,6 +48,105 @@ L2: l2-cache {
 		};
 	};
 
+	opp_table_l2: opp_table_l2 {
+		compatible = "operating-points-v2";
+
+		opp-384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <100000>;
+			opp-level = <0>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <100000>;
+			opp-level = <1>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1150000>;
+			clock-latency-ns = <100000>;
+			opp-level = <2>;
+		};
+	};
+
+	opp_table0: opp_table0 {
+		compatible = "operating-points-v2-kryo-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+
+		/*
+		 * Voltage thresholds are <target min max>
+		 */
+		opp-384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
+			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
+			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <0>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <1>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
+			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <1>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <1>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
+			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
+			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
+			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <2>;
+		};
+
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
+			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
+			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <100000>;
+			opp-level = <2>;
+		};
+	};
+
 	thermal-zones {
 		sensor0-thermal {
 			polling-delay-passive = <0>;
-- 
2.34.1

[PATCH v3 14/18] ARM: dts: qcom: add speedbin efuse nvmem binding

[Ansuel Smith]

Add speedbin efuse nvmem binding needed for the opp table for the CPU
freqs.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index a1079583def9..629e22236f5b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -981,6 +981,9 @@ tsens_calib: calib@400 {
 			tsens_calib_backup: calib_backup@410 {
 				reg = <0x410 0xb>;
 			};
+			speedbin_efuse: speedbin@0c0 {
+				reg = <0x0c0 0x4>;
+			};
 		};
 
 		gcc: clock-controller@900000 {
-- 
2.34.1

[PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu and l2 for ipq8064

[Ansuel Smith]

Add multiple binding for cpu node, l2 node and add idle-states
definition for ipq8064 dtsi.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 629e22236f5b..1079572f4f5d 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -30,6 +30,16 @@ cpu0: cpu@0 {
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc0>;
 			qcom,saw = <&saw0>;
+			clocks = <&kraitcc 0>, <&kraitcc 4>;
+			clock-names = "cpu", "l2";
+			clock-latency = <100000>;
+			cpu-supply = <&smb208_s2a>;
+			operating-points-v2 = <&opp_table0>;
+			voltage-tolerance = <5>;
+			cooling-min-state = <0>;
+			cooling-max-state = <10>;
+			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SPC>;
 		};
 
 		cpu1: cpu@1 {
@@ -40,11 +50,37 @@ cpu1: cpu@1 {
 			next-level-cache = <&L2>;
 			qcom,acc = <&acc1>;
 			qcom,saw = <&saw1>;
+			clocks = <&kraitcc 1>, <&kraitcc 4>;
+			clock-names = "cpu", "l2";
+			clock-latency = <100000>;
+			cpu-supply = <&smb208_s2b>;
+			operating-points-v2 = <&opp_table0>;
+			voltage-tolerance = <5>;
+			cooling-min-state = <0>;
+			cooling-max-state = <10>;
+			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SPC>;
+		};
+
+		idle-states {
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc";
+				status = "disabled";
+				entry-latency-us = <400>;
+				exit-latency-us = <900>;
+				min-residency-us = <3000>;
+			};
 		};
 
 		L2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
+			qcom,saw = <&saw_l2>;
+
+			clocks = <&kraitcc 4>;
+			clock-names = "l2";
+			l2-supply = <&smb208_s1a>;
+			operating-points-v2 = <&opp_table_l2>;
 		};
 	};
 
-- 
2.34.1

[PATCH v3 16/18] ARM: dts: qcom: remove redundant binding from ipq8064 rb3011 dts

[Ansuel Smith]

Mdio0_pins are now declared in ipq8064 dtsi. Usb phy are enabled by
default.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 611a4a19631c..22a4fa8b5e2b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -259,10 +259,6 @@ &gsbi7_serial {
 	status = "okay";
 };
 
-&hs_phy_1 {
-	status = "okay";
-};
-
 &nand {
 	status = "okay";
 
@@ -309,15 +305,6 @@ mux {
 		};
 	};
 
-	mdio0_pins: mdio0_pins {
-		mux {
-			pins = "gpio0", "gpio1";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-
 	mdio1_pins: mdio1_pins {
 		mux {
 			pins = "gpio10", "gpio11";
@@ -358,10 +345,6 @@ mux {
 	};
 };
 
-&ss_phy_1 {
-	status = "okay";
-};
-
 &usb3_1 {
 	pinctrl-0 = <&usb1_pwr_en_pins>;
 	pinctrl-names = "default";
-- 
2.34.1

[PATCH v3 17/18] ARM: dts: qcom: add ipq8064-v2.0 dtsi

[Ansuel Smith]

Many devices are based on the v2.0 of the ipq8064 SoC. Main difference
is a change in the pci compatible and different way to configre the usb
phy.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
new file mode 100644
index 000000000000..c082c3cd1a19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+	aliases {
+		serial0 = &gsbi4_serial;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rsvd@41200000 {
+			reg = <0x41200000 0x300000>;
+			no-map;
+		};
+	};
+};
+
+&gsbi4 {
+	qcom,mode = <GSBI_PROT_I2C_UART>;
+	status = "okay";
+
+	serial@16340000 {
+		status = "okay";
+	};
+	/*
+	 * The i2c device on gsbi4 should not be enabled.
+	 * On ipq806x designs gsbi4 i2c is meant for exclusive
+	 * RPM usage. Turning this on in kernel manifests as
+	 * i2c failure for the RPM.
+	 */
+};
+
+&CPU_SPC {
+	status = "okay";
+};
+
+&pcie0 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+	ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+	qcom,rx-eq = <2>;
+	qcom,tx-deamp_3_5db = <32>;
+	qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+	qcom,rx-eq = <2>;
+	qcom,tx-deamp_3_5db = <32>;
+	qcom,mpll = <5>;
+};
-- 
2.34.1

[PATCH v3 18/18] ARM: dts: qcom: add ipq8065 dtsi

[Ansuel Smith]

Many device are based on ipq8065 SoC. Ipq8065 is an evolution of the
ipq8064 SoC (also named ipq8064-v3.0 from qsdk) that has all the
improvement from ipq8064-v2.0 with the addition of a more powerful CPU
that can now be clocked to 1.7Ghz, a quicker L2 cache that can be
clocked to 1.4Ghz. It also shipped with more powerful regulators to
provide the required voltage to the CPUs and L2.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
 arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 ++++++++++++++++++++++++++++
 1 file changed, 168 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi
new file mode 100644
index 000000000000..817d723b0c88
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+	model = "Qualcomm IPQ8065";
+	compatible = "qcom,ipq8065", "qcom,ipq8064";
+
+	aliases {
+		serial0 = &gsbi4_serial;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rsvd@41200000 {
+			reg = <0x41200000 0x300000>;
+			no-map;
+		};
+	};
+};
+
+&gsbi4 {
+	qcom,mode = <GSBI_PROT_I2C_UART>;
+	status = "okay";
+
+	serial@16340000 {
+		status = "okay";
+	};
+	/*
+	 * The i2c device on gsbi4 should not be enabled.
+	 * On ipq806x designs gsbi4 i2c is meant for exclusive
+	 * RPM usage. Turning this on in kernel manifests as
+	 * i2c failure for the RPM.
+	 */
+};
+
+&pcie0 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+	compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+	ports-implemented = <0x1>;
+};
+
+&smb208_s2a {
+	regulator-min-microvolt = <775000>;
+	regulator-max-microvolt = <1275000>;
+};
+
+&smb208_s2b {
+	regulator-min-microvolt = <775000>;
+	regulator-max-microvolt = <1275000>;
+};
+
+&ss_phy_0 {
+	qcom,rx-eq = <2>;
+	qcom,tx-deamp_3_5db = <32>;
+	qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+	qcom,rx-eq = <2>;
+	qcom,tx-deamp_3_5db = <32>;
+	qcom,mpll = <5>;
+};
+
+&opp_table_l2 {
+	/delete-node/opp-1200000000;
+
+	opp-1400000000 {
+		opp-hz = /bits/ 64 <1400000000>;
+		opp-microvolt = <1150000>;
+		clock-latency-ns = <100000>;
+		opp-level = <2>;
+	};
+};
+
+&opp_table0 {
+	/*
+	 * On ipq8065 1.2 ghz freq is not present
+	 * Remove it to make cpufreq work and not
+	 * complain for missing definition
+	 */
+
+	/delete-node/opp-1200000000;
+
+	/*
+	 * Voltage thresholds are <target min max>
+	 */
+	opp-384000000 {
+		opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+		opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+		opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+		opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
+	};
+
+	opp-600000000 {
+		opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+		opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+		opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
+	};
+
+	opp-800000000 {
+		opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+		opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+		opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+		opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
+	};
+
+	opp-1000000000 {
+		opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+		opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+		opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+		opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+		opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
+	};
+
+	opp-1400000000 {
+		opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+		opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+		opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+		opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+		opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+		opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
+		opp-level = <1>;
+	};
+
+	opp-1725000000 {
+		opp-hz = /bits/ 64 <1725000000>;
+		opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+		opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+		opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+		opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+		opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+		opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+		opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
+		opp-supported-hw = <0x1>;
+		clock-latency-ns = <100000>;
+		opp-level = <2>;
+	};
+};
-- 
2.34.1

Re: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

[kernel test robot]

Hi Ansuel,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linux/master linus/master v5.17-rc7 next-20220309]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-defconfig (https://download.01.org/0day-ci/archive/20220310/202203101733.hkbTGp6Y-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 276ca87382b8f16a65bddac700202924228982f6)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # https://github.com/0day-ci/linux/commit/52c3b4af226c7a50772c40012b3789b5348e49b5
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
        git checkout 52c3b4af226c7a50772c40012b3789b5348e49b5
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> ERROR: Input tree has errors, aborting (use -f to force output)

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

[Ansuel Smith]

On Thu, Mar 10, 2022 at 05:46:31PM +0800, kernel test robot wrote:
> Hi Ansuel,
> 
> Thank you for the patch! Yet something to improve:
> 
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on linux/master linus/master v5.17-rc7 next-20220309]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
> 
> url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm-defconfig (https://download.01.org/0day-ci/archive/20220310/202203101733.hkbTGp6Y-lkp@intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 276ca87382b8f16a65bddac700202924228982f6)
> reproduce (this is a W=1 build):
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm cross compiling tool for clang build
>         # apt-get install binutils-arm-linux-gnueabi
>         # https://github.com/0day-ci/linux/commit/52c3b4af226c7a50772c40012b3789b5348e49b5
>         git remote add linux-review https://github.com/0day-ci/linux
>         git fetch --no-tags linux-review Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
>         git checkout 52c3b4af226c7a50772c40012b3789b5348e49b5
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All errors (new ones prefixed by >>):
> 
> >> ERROR: Input tree has errors, aborting (use -f to force output)
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Just as an info this error comes from the fact that we require
pxo_board, introduced by another series already merged in linux-arm-msm.

I didn't find how to propose this series directly to the linux-arm-msm
branch.

-- 
	Ansuel

Re: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

[Ansuel Smith]

[-- Attachment #1: Type: text/plain, Size: 2333 bytes --]

On Thu, Mar 10, 2022 at 05:46:31PM +0800, kernel test robot wrote:
> Hi Ansuel,
> 
> Thank you for the patch! Yet something to improve:
> 
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on linux/master linus/master v5.17-rc7 next-20220309]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
> 
> url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm-defconfig (https://download.01.org/0day-ci/archive/20220310/202203101733.hkbTGp6Y-lkp(a)intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 276ca87382b8f16a65bddac700202924228982f6)
> reproduce (this is a W=1 build):
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm cross compiling tool for clang build
>         # apt-get install binutils-arm-linux-gnueabi
>         # https://github.com/0day-ci/linux/commit/52c3b4af226c7a50772c40012b3789b5348e49b5
>         git remote add linux-review https://github.com/0day-ci/linux
>         git fetch --no-tags linux-review Ansuel-Smith/Multiple-addition-to-ipq8064-dtsi/20220310-031750
>         git checkout 52c3b4af226c7a50772c40012b3789b5348e49b5
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All errors (new ones prefixed by >>):
> 
> >> ERROR: Input tree has errors, aborting (use -f to force output)
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

Just as an info this error comes from the fact that we require
pxo_board, introduced by another series already merged in linux-arm-msm.

I didn't find how to propose this series directly to the linux-arm-msm
branch.

-- 
	Ansuel

Re: [PATCH v3 01/18] ARM: dts: qcom: add multiple missing pin definition for ipq8064

[Ansuel Smith]

On Tue, Apr 12, 2022 at 02:55:04PM -0500, Bjorn Andersson wrote:
> On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:
> 
> > Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
> > pins and rgmii2 pins for ipq8064.
> > 
> 
> I'm probably not looking hard enough, but I don't see where these are
> used. Could they be introduced as they are being wired into their client
> devices?
> 
> Thanks,
> Bjorn
> 

mdio0 pins are used for by the switch connected to the SoC.
i2c4 are used by rpm but in theory should never be used.
rgmii2 i think were added for as some request for some devices that use
them but not present upstream. Is it that bad to declare pin even if
they are not used? They are used by any device downstream. 

> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Tested-by: Jonathan McDowell <noodles@earth.li>
> > ---
> >  arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index 11481313bdb6..cc6ca9013ab1 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -382,6 +382,15 @@ mux {
> >  				};
> >  			};
> >  
> > +			i2c4_pins: i2c4_pinmux {
> > +				mux {
> > +					pins = "gpio12", "gpio13";
> > +					function = "gsbi4";
> > +					drive-strength = <12>;
> > +					bias-disable;
> > +				};
> > +			};
> > +
> >  			spi_pins: spi_pins {
> >  				mux {
> >  					pins = "gpio18", "gpio19", "gpio21";
> > @@ -424,6 +433,8 @@ mux {
> >  
> >  				pullups {
> >  					pins = "gpio39";
> > +					function = "nand";
> > +					drive-strength = <10>;
> >  					bias-pull-up;
> >  				};
> >  
> > @@ -431,9 +442,32 @@ hold {
> >  					pins = "gpio40", "gpio41", "gpio42",
> >  					       "gpio43", "gpio44", "gpio45",
> >  					       "gpio46", "gpio47";
> > +					function = "nand";
> > +					drive-strength = <10>;
> >  					bias-bus-hold;
> >  				};
> >  			};
> > +
> > +			mdio0_pins: mdio0_pins {
> > +				mux {
> > +					pins = "gpio0", "gpio1";
> > +					function = "mdio";
> > +					drive-strength = <8>;
> > +					bias-disable;
> > +				};
> > +			};
> > +
> > +			rgmii2_pins: rgmii2_pins {
> > +				mux {
> > +					pins = "gpio27", "gpio28", "gpio29",
> > +					       "gpio30", "gpio31", "gpio32",
> > +					       "gpio51", "gpio52", "gpio59",
> > +					       "gpio60", "gpio61", "gpio62";
> > +					function = "rgmii2";
> > +					drive-strength = <8>;
> > +					bias-disable;
> > +				};
> > +			};
> >  		};
> >  
> >  		intc: interrupt-controller@2000000 {
> > -- 
> > 2.34.1
> > 

-- 
	Ansuel

Re: [PATCH v3 03/18] ARM: dts: qcom: add missing rpm regulators and cells for ipq8064

[Bjorn Andersson]

On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:

> Add cells definition for rpm node

Why do we need the cells?

> and add missing regulators for the 4
> regulator present on ipq8064. There regulators are controlled by rpm and
> to correctly works gsbi4_i2c require to be NEVER disabled or rpm will

Are you saying "...to correctly work, gsbi4_i2c must NEVER be disabled..."?

If so, that's good information, but how does it relate to this
particular change?

Regards,
Bjorn

> reject any regulator change request.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>  arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index b309bc0fbbcd..0938838a4af8 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -842,10 +842,46 @@ rpm: rpm@108000 {
>  			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
>  			clock-names = "ram";
>  
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
>  			rpmcc: clock-controller {
>  				compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
>  				#clock-cells = <1>;
>  			};
> +
> +			smb208_regulators: regulators {
> +				compatible = "qcom,rpm-smb208-regulators";
> +				status = "okay";
> +
> +				smb208_s1a: s1a {
> +					regulator-min-microvolt = <1050000>;
> +					regulator-max-microvolt = <1150000>;
> +
> +					qcom,switch-mode-frequency = <1200000>;
> +				};
> +
> +				smb208_s1b: s1b {
> +					regulator-min-microvolt = <1050000>;
> +					regulator-max-microvolt = <1150000>;
> +
> +					qcom,switch-mode-frequency = <1200000>;
> +				};
> +
> +				smb208_s2a: s2a {
> +					regulator-min-microvolt = < 800000>;
> +					regulator-max-microvolt = <1250000>;
> +
> +					qcom,switch-mode-frequency = <1200000>;
> +				};
> +
> +				smb208_s2b: s2b {
> +					regulator-min-microvolt = < 800000>;
> +					regulator-max-microvolt = <1250000>;
> +
> +					qcom,switch-mode-frequency = <1200000>;
> +				};
> +			};
>  		};
>  
>  		tcsr: syscon@1a400000 {
> -- 
> 2.34.1
> 

Re: [PATCH v3 01/18] ARM: dts: qcom: add multiple missing pin definition for ipq8064

[Bjorn Andersson]

On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:

> Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
> pins and rgmii2 pins for ipq8064.
> 

I'm probably not looking hard enough, but I don't see where these are
used. Could they be introduced as they are being wired into their client
devices?

Thanks,
Bjorn

> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>  arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 11481313bdb6..cc6ca9013ab1 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -382,6 +382,15 @@ mux {
>  				};
>  			};
>  
> +			i2c4_pins: i2c4_pinmux {
> +				mux {
> +					pins = "gpio12", "gpio13";
> +					function = "gsbi4";
> +					drive-strength = <12>;
> +					bias-disable;
> +				};
> +			};
> +
>  			spi_pins: spi_pins {
>  				mux {
>  					pins = "gpio18", "gpio19", "gpio21";
> @@ -424,6 +433,8 @@ mux {
>  
>  				pullups {
>  					pins = "gpio39";
> +					function = "nand";
> +					drive-strength = <10>;
>  					bias-pull-up;
>  				};
>  
> @@ -431,9 +442,32 @@ hold {
>  					pins = "gpio40", "gpio41", "gpio42",
>  					       "gpio43", "gpio44", "gpio45",
>  					       "gpio46", "gpio47";
> +					function = "nand";
> +					drive-strength = <10>;
>  					bias-bus-hold;
>  				};
>  			};
> +
> +			mdio0_pins: mdio0_pins {
> +				mux {
> +					pins = "gpio0", "gpio1";
> +					function = "mdio";
> +					drive-strength = <8>;
> +					bias-disable;
> +				};
> +			};
> +
> +			rgmii2_pins: rgmii2_pins {
> +				mux {
> +					pins = "gpio27", "gpio28", "gpio29",
> +					       "gpio30", "gpio31", "gpio32",
> +					       "gpio51", "gpio52", "gpio59",
> +					       "gpio60", "gpio61", "gpio62";
> +					function = "rgmii2";
> +					drive-strength = <8>;
> +					bias-disable;
> +				};
> +			};
>  		};
>  
>  		intc: interrupt-controller@2000000 {
> -- 
> 2.34.1
> 

Re: [PATCH v3 03/18] ARM: dts: qcom: add missing rpm regulators and cells for ipq8064

[Ansuel Smith]

On Tue, Apr 12, 2022 at 02:46:39PM -0500, Bjorn Andersson wrote:
> On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:
> 
> > Add cells definition for rpm node
> 
> Why do we need the cells?
>

Mh I'm referring to address-cells and size-cells required for reg or dtb
will give warnings.

> > and add missing regulators for the 4
> > regulator present on ipq8064. There regulators are controlled by rpm and
> > to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
> 
> Are you saying "...to correctly work, gsbi4_i2c must NEVER be disabled..."?
> 
> If so, that's good information, but how does it relate to this
> particular change?
> 

It doesn't but since it I had many days trying to debug the regulators
not working only to discover that the problem was with the pin, I thought
it was a good idea to add this info. Should I just drop it or should i
add some comments in the dts?

> Regards,
> Bjorn
> 
> > reject any regulator change request.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Tested-by: Jonathan McDowell <noodles@earth.li>
> > ---
> >  arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index b309bc0fbbcd..0938838a4af8 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -842,10 +842,46 @@ rpm: rpm@108000 {
> >  			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
> >  			clock-names = "ram";
> >  
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +
> >  			rpmcc: clock-controller {
> >  				compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
> >  				#clock-cells = <1>;
> >  			};
> > +
> > +			smb208_regulators: regulators {
> > +				compatible = "qcom,rpm-smb208-regulators";
> > +				status = "okay";
> > +
> > +				smb208_s1a: s1a {
> > +					regulator-min-microvolt = <1050000>;
> > +					regulator-max-microvolt = <1150000>;
> > +
> > +					qcom,switch-mode-frequency = <1200000>;
> > +				};
> > +
> > +				smb208_s1b: s1b {
> > +					regulator-min-microvolt = <1050000>;
> > +					regulator-max-microvolt = <1150000>;
> > +
> > +					qcom,switch-mode-frequency = <1200000>;
> > +				};
> > +
> > +				smb208_s2a: s2a {
> > +					regulator-min-microvolt = < 800000>;
> > +					regulator-max-microvolt = <1250000>;
> > +
> > +					qcom,switch-mode-frequency = <1200000>;
> > +				};
> > +
> > +				smb208_s2b: s2b {
> > +					regulator-min-microvolt = < 800000>;
> > +					regulator-max-microvolt = <1250000>;
> > +
> > +					qcom,switch-mode-frequency = <1200000>;
> > +				};
> > +			};
> >  		};
> >  
> >  		tcsr: syscon@1a400000 {
> > -- 
> > 2.34.1
> > 

-- 
	Ansuel

Re: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for ipq8064

[Bjorn Andersson]

On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:

> Add opp table for cpu and l2 cache. While the current cpufreq is
> the generic one that doesn't scale the L2 cache, we add the l2
> cache opp anyway for the sake of completeness. This will be handy in the
> future when a dedicated cpufreq driver is introduced for krait cores
> that will correctly scale l2 cache with the core freq.
> 
> Opp-level is set based on the logic of
> 0: idle level
> 1: normal level
> 2: turbo level
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>  arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 7dd0b901cd30..a1079583def9 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -48,6 +48,105 @@ L2: l2-cache {
>  		};
>  	};
>  
> +	opp_table_l2: opp_table_l2 {

Please don't use '_' in the node names.

> +		compatible = "operating-points-v2";
> +
> +		opp-384000000 {
> +			opp-hz = /bits/ 64 <384000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <0>;
> +		};
> +
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <1>;
> +		};
> +
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1150000>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <2>;
> +		};
> +	};
> +
> +	opp_table0: opp_table0 {

Perhaps you can name this opp-table-kryo, to make it consistent with
opp-table-l2 above?

Regards,
Bjorn

> +		compatible = "operating-points-v2-kryo-cpu";
> +		nvmem-cells = <&speedbin_efuse>;
> +
> +		/*
> +		 * Voltage thresholds are <target min max>
> +		 */
> +		opp-384000000 {
> +			opp-hz = /bits/ 64 <384000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
> +			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
> +			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
> +			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <0>;
> +		};
> +
> +		opp-600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
> +			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
> +			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
> +			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <1>;
> +		};
> +
> +		opp-800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
> +			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
> +			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
> +			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <1>;
> +		};
> +
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
> +			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
> +			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
> +			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <1>;
> +		};
> +
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
> +			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
> +			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
> +			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <2>;
> +		};
> +
> +		opp-1400000000 {
> +			opp-hz = /bits/ 64 <1400000000>;
> +			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
> +			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
> +			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
> +			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <100000>;
> +			opp-level = <2>;
> +		};
> +	};
> +
>  	thermal-zones {
>  		sensor0-thermal {
>  			polling-delay-passive = <0>;
> -- 
> 2.34.1
> 

Re: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for ipq8064

[Ansuel Smith]

On Tue, Apr 12, 2022 at 03:07:56PM -0500, Bjorn Andersson wrote:
> On Wed 09 Mar 13:01 CST 2022, Ansuel Smith wrote:
> 
> > Add opp table for cpu and l2 cache. While the current cpufreq is
> > the generic one that doesn't scale the L2 cache, we add the l2
> > cache opp anyway for the sake of completeness. This will be handy in the
> > future when a dedicated cpufreq driver is introduced for krait cores
> > that will correctly scale l2 cache with the core freq.
> > 
> > Opp-level is set based on the logic of
> > 0: idle level
> > 1: normal level
> > 2: turbo level
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Tested-by: Jonathan McDowell <noodles@earth.li>
> > ---
> >  arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
> >  1 file changed, 99 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index 7dd0b901cd30..a1079583def9 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -48,6 +48,105 @@ L2: l2-cache {
> >  		};
> >  	};
> >  
> > +	opp_table_l2: opp_table_l2 {
> 
> Please don't use '_' in the node names.
> 
> > +		compatible = "operating-points-v2";
> > +
> > +		opp-384000000 {
> > +			opp-hz = /bits/ 64 <384000000>;
> > +			opp-microvolt = <1100000>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <0>;
> > +		};
> > +
> > +		opp-1000000000 {
> > +			opp-hz = /bits/ 64 <1000000000>;
> > +			opp-microvolt = <1100000>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <1>;
> > +		};
> > +
> > +		opp-1200000000 {
> > +			opp-hz = /bits/ 64 <1200000000>;
> > +			opp-microvolt = <1150000>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <2>;
> > +		};
> > +	};
> > +
> > +	opp_table0: opp_table0 {
> 
> Perhaps you can name this opp-table-kryo, to make it consistent with
> opp-table-l2 above?
> 
> Regards,
> Bjorn
>

Considering this is krait, I think I should use krait. Also about this
we have from ages the wrong compatible but we had too keep kryo to not
break compatibility with old dt. Can I fix this for once and just add
this additional compatible?

> > +		compatible = "operating-points-v2-kryo-cpu";
> > +		nvmem-cells = <&speedbin_efuse>;
> > +
> > +		/*
> > +		 * Voltage thresholds are <target min max>
> > +		 */
> > +		opp-384000000 {
> > +			opp-hz = /bits/ 64 <384000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
> > +			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
> > +			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
> > +			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <0>;
> > +		};
> > +
> > +		opp-600000000 {
> > +			opp-hz = /bits/ 64 <600000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
> > +			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
> > +			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
> > +			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <1>;
> > +		};
> > +
> > +		opp-800000000 {
> > +			opp-hz = /bits/ 64 <800000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
> > +			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
> > +			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
> > +			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <1>;
> > +		};
> > +
> > +		opp-1000000000 {
> > +			opp-hz = /bits/ 64 <1000000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
> > +			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
> > +			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
> > +			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <1>;
> > +		};
> > +
> > +		opp-1200000000 {
> > +			opp-hz = /bits/ 64 <1200000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
> > +			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
> > +			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
> > +			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <2>;
> > +		};
> > +
> > +		opp-1400000000 {
> > +			opp-hz = /bits/ 64 <1400000000>;
> > +			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
> > +			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
> > +			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
> > +			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <100000>;
> > +			opp-level = <2>;
> > +		};
> > +	};
> > +
> >  	thermal-zones {
> >  		sensor0-thermal {
> >  			polling-delay-passive = <0>;
> > -- 
> > 2.34.1
> > 

-- 
	Ansuel

Re: [PATCH v3 06/18] ARM: dts: qcom: enable usb phy by default for ipq8064

[Dmitry Baryshkov]

On 09/03/2022 22:01, Ansuel Smith wrote:
> Enable usb phy by default. When the usb phy were pushed, half of them
> were flagged as disabled by mistake. Fix this to correctly init dwc3
> node on any ipq8064 based SoC.

Typically they would be disabled in the platform dtsi file and would be 
enabled one-by-one in the board dts file. So, if half of usb phys are 
enabled by default, I'd kindly ask to perform the opposite change: 
disable all of them by default and enable in board dts files.

> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>   arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ----
>   1 file changed, 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 9d658fcc1f12..e247bf51df01 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -1175,8 +1175,6 @@ hs_phy_0: phy@100f8800 {
>   			clocks = <&gcc USB30_0_UTMI_CLK>;
>   			clock-names = "ref";
>   			#phy-cells = <0>;
> -
> -			status = "disabled";
>   		};
>   
>   		ss_phy_0: phy@100f8830 {
> @@ -1185,8 +1183,6 @@ ss_phy_0: phy@100f8830 {
>   			clocks = <&gcc USB30_0_MASTER_CLK>;
>   			clock-names = "ref";
>   			#phy-cells = <0>;
> -
> -			status = "disabled";
>   		};
>   
>   		usb3_0: usb3@100f8800 {


-- 
With best wishes
Dmitry

Re: [PATCH v3 17/18] ARM: dts: qcom: add ipq8064-v2.0 dtsi

[Dmitry Baryshkov]

On 09/03/2022 22:01, Ansuel Smith wrote:
> Many devices are based on the v2.0 of the ipq8064 SoC. Main difference
> is a change in the pci compatible and different way to configre the usb
> phy.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>   arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++++++++++++++++++++++
>   1 file changed, 70 insertions(+)
>   create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
> new file mode 100644
> index 000000000000..c082c3cd1a19
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "qcom-ipq8064.dtsi"
> +
> +/ {
> +	aliases {
> +		serial0 = &gsbi4_serial;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};

I'd expect that /aliases and /chosen should go to the board dts files.
I see that ipq8064-v1.0.dtsi also is a mixture of SoC-specific nodes and 
board details (gpio, leds, aliases, etc.). I think it should be split 
into ipq8064-v1.0.dtsi and ipq8064-common.dtsi (or 
ipq8064-v1.0-common.dtsi). This file also should contain just SoC 
specifics, not the enablement of individual devices.

> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		rsvd@41200000 {
> +			reg = <0x41200000 0x300000>;
> +			no-map;
> +		};
> +	};
> +};
> +
> +&gsbi4 {
> +	qcom,mode = <GSBI_PROT_I2C_UART>;
> +	status = "okay";
> +
> +	serial@16340000 {
> +		status = "okay";
> +	};
> +	/*
> +	 * The i2c device on gsbi4 should not be enabled.
> +	 * On ipq806x designs gsbi4 i2c is meant for exclusive
> +	 * RPM usage. Turning this on in kernel manifests as
> +	 * i2c failure for the RPM.
> +	 */
> +};
> +
> +&CPU_SPC {
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	compatible = "qcom,pcie-ipq8064-v2";
> +};
> +
> +&pcie1 {
> +	compatible = "qcom,pcie-ipq8064-v2";
> +};
> +
> +&pcie2 {
> +	compatible = "qcom,pcie-ipq8064-v2";
> +};
> +
> +&sata {
> +	ports-implemented = <0x1>;
> +};
> +
> +&ss_phy_0 {
> +	qcom,rx-eq = <2>;
> +	qcom,tx-deamp_3_5db = <32>;
> +	qcom,mpll = <5>;
> +};
> +
> +&ss_phy_1 {
> +	qcom,rx-eq = <2>;
> +	qcom,tx-deamp_3_5db = <32>;
> +	qcom,mpll = <5>;
> +};


-- 
With best wishes
Dmitry

Re: [PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

[Dmitry Baryshkov]

On 09/03/2022 22:01, Ansuel Smith wrote:
> The current value for pci IO is problematic for ath10k wifi card
> commonly connected to ipq8064 SoC.
> The current value is probably a typo and is actually uncommon to find
> 1MB IO space even on a x86 arch.

I checked other Qualcomm platforms (including downstream apq8084.dtsi). 
All of them list 1MB region as IO space.

Interesting enough I couldn't get PCI to work on my IFC6410 (apq8064). 
It has an ethernet adapter AR8151 sitting on the PCIe bus. The driver 
probes, transmits packets successfully, but receives only garbage. I'm 
not sure if it is the hardware or a software problem. Same adapter works 
fine on db820c.

> Also with recent changes to the pci
> driver, pci1 and pci2 now fails to function as any connected device
> fails any reg read/write. Reduce this to 64K as it should be more than
> enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
> hardcoded for the ARM arch.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> Tested-by: Jonathan McDowell <noodles@earth.li>
> ---
>   arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index e247bf51df01..36bdfc8db3f0 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
>   			#address-cells = <3>;
>   			#size-cells = <2>;
>   
> -			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
> +			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
>   				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
>   
>   			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> @@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
>   			#address-cells = <3>;
>   			#size-cells = <2>;
>   
> -			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
> +			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
>   				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
>   
>   			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
>   			#address-cells = <3>;
>   			#size-cells = <2>;
>   
> -			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
> +			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
>   				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
>   
>   			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;


-- 
With best wishes
Dmitry

Re: [PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

[Ansuel Smith]

On Wed, Apr 13, 2022 at 04:19:42PM +0300, Dmitry Baryshkov wrote:
> On 09/03/2022 22:01, Ansuel Smith wrote:
> > The current value for pci IO is problematic for ath10k wifi card
> > commonly connected to ipq8064 SoC.
> > The current value is probably a typo and is actually uncommon to find
> > 1MB IO space even on a x86 arch.
> 
> I checked other Qualcomm platforms (including downstream apq8084.dtsi). All
> of them list 1MB region as IO space.
> 
> Interesting enough I couldn't get PCI to work on my IFC6410 (apq8064). It
> has an ethernet adapter AR8151 sitting on the PCIe bus. The driver probes,
> transmits packets successfully, but receives only garbage. I'm not sure if
> it is the hardware or a software problem. Same adapter works fine on db820c.
>

I didn't understand if device works correctly without this change. 
The alternative to this, is to change the io space globally for every arm
target and it was pointed out that it was a strange change to do. 99%
the 1mb region present on every qcom platform is a copy past error but
still a region that big worked before some kernel version just because
the kernel didn't check them.
So it's both reduce IO in dtsi or extend IO_SPACE_LIMIT for every arm
target.

> > Also with recent changes to the pci
> > driver, pci1 and pci2 now fails to function as any connected device
> > fails any reg read/write. Reduce this to 64K as it should be more than
> > enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
> > hardcoded for the ARM arch.
> > 
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > Tested-by: Jonathan McDowell <noodles@earth.li>
> > ---
> >   arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
> >   1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index e247bf51df01..36bdfc8db3f0 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
> >   			#address-cells = <3>;
> >   			#size-cells = <2>;
> > -			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
> > +			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
> >   				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
> >   			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > @@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
> >   			#address-cells = <3>;
> >   			#size-cells = <2>;
> > -			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
> > +			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
> >   				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
> >   			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> > @@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
> >   			#address-cells = <3>;
> >   			#size-cells = <2>;
> > -			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
> > +			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
> >   				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
> >   			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 
> 
> -- 
> With best wishes
> Dmitry

-- 
	Ansuel

Re: [PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

[Dmitry Baryshkov]

On 13/04/2022 16:19, Dmitry Baryshkov wrote:
> On 09/03/2022 22:01, Ansuel Smith wrote:
>> The current value for pci IO is problematic for ath10k wifi card
>> commonly connected to ipq8064 SoC.
>> The current value is probably a typo and is actually uncommon to find
>> 1MB IO space even on a x86 arch.
> 
> I checked other Qualcomm platforms (including downstream apq8084.dtsi). 
> All of them list 1MB region as IO space.
> 
> Interesting enough I couldn't get PCI to work on my IFC6410 (apq8064). 
> It has an ethernet adapter AR8151 sitting on the PCIe bus. The driver 
> probes, transmits packets successfully, but receives only garbage. I'm 
> not sure if it is the hardware or a software problem. Same adapter works 
> fine on db820c.

I noticed that it looks like the packet is shifted by two bytes. Maybe 
it's some weird maths somewhere. Maybe it's the lack of iommu on 
apq8064. Anyway, it seems to be unrelated to the issue being discussed.

> 
>> Also with recent changes to the pci
>> driver, pci1 and pci2 now fails to function as any connected device
>> fails any reg read/write. Reduce this to 64K as it should be more than
>> enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
>> hardcoded for the ARM arch.
>>
>> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
>> Tested-by: Jonathan McDowell <noodles@earth.li>
>> ---
>>   arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi 
>> b/arch/arm/boot/dts/qcom-ipq8064.dtsi
>> index e247bf51df01..36bdfc8db3f0 100644
>> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
>> @@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
>>               #address-cells = <3>;
>>               #size-cells = <2>;
>> -            ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 
>> 0x00100000   /* downstream I/O */
>> +            ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 
>> 0x00010000   /* downstream I/O */
>>                     0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; 
>> /* non-prefetchable memory */
>>               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
>>               #address-cells = <3>;
>>               #size-cells = <2>;
>> -            ranges = <0x81000000 0 0x31e00000 0x31e00000 0 
>> 0x00100000   /* downstream I/O */
>> +            ranges = <0x81000000 0 0x31e00000 0x31e00000 0 
>> 0x00010000   /* downstream I/O */
>>                     0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; 
>> /* non-prefetchable memory */
>>               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
>>               #address-cells = <3>;
>>               #size-cells = <2>;
>> -            ranges = <0x81000000 0 0x35e00000 0x35e00000 0 
>> 0x00100000   /* downstream I/O */
>> +            ranges = <0x81000000 0 0x35e00000 0x35e00000 0 
>> 0x00010000   /* downstream I/O */
>>                     0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; 
>> /* non-prefetchable memory */
>>               interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> 
> 


-- 
With best wishes
Dmitry

Re: [PATCH v3 07/18] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064

[Dmitry Baryshkov]

On 13/04/2022 16:21, Ansuel Smith wrote:
> On Wed, Apr 13, 2022 at 04:19:42PM +0300, Dmitry Baryshkov wrote:
>> On 09/03/2022 22:01, Ansuel Smith wrote:
>>> The current value for pci IO is problematic for ath10k wifi card
>>> commonly connected to ipq8064 SoC.
>>> The current value is probably a typo and is actually uncommon to find
>>> 1MB IO space even on a x86 arch.
>>
>> I checked other Qualcomm platforms (including downstream apq8084.dtsi). All
>> of them list 1MB region as IO space.
>>
>> Interesting enough I couldn't get PCI to work on my IFC6410 (apq8064). It
>> has an ethernet adapter AR8151 sitting on the PCIe bus. The driver probes,
>> transmits packets successfully, but receives only garbage. I'm not sure if
>> it is the hardware or a software problem. Same adapter works fine on db820c.
>>
> 
> I didn't understand if device works correctly without this change.
> The alternative to this, is to change the io space globally for every arm
> target and it was pointed out that it was a strange change to do. 99%
> the 1mb region present on every qcom platform is a copy past error but
> still a region that big worked before some kernel version just because
> the kernel didn't check them.
> So it's both reduce IO in dtsi or extend IO_SPACE_LIMIT for every arm
> target.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> 
>>> Also with recent changes to the pci
>>> driver, pci1 and pci2 now fails to function as any connected device
>>> fails any reg read/write. Reduce this to 64K as it should be more than
>>> enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
>>> hardcoded for the ARM arch.
>>>
>>> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
>>> Tested-by: Jonathan McDowell <noodles@earth.li>
>>> ---
>>>    arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
>>>    1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
>>> index e247bf51df01..36bdfc8db3f0 100644
>>> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
>>> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
>>> @@ -918,7 +918,7 @@ pcie0: pci@1b500000 {
>>>    			#address-cells = <3>;
>>>    			#size-cells = <2>;
>>> -			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
>>> +			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
>>>    				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
>>>    			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>>> @@ -969,7 +969,7 @@ pcie1: pci@1b700000 {
>>>    			#address-cells = <3>;
>>>    			#size-cells = <2>;
>>> -			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
>>> +			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
>>>    				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
>>>    			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>>> @@ -1020,7 +1020,7 @@ pcie2: pci@1b900000 {
>>>    			#address-cells = <3>;
>>>    			#size-cells = <2>;
>>> -			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
>>> +			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
>>>    				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
>>>    			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>>
>>
>> -- 
>> With best wishes
>> Dmitry
> 


-- 
With best wishes
Dmitry