From: "Chalamarla, Tirumalesh" <Tirumalesh.Chalamarla@caviumnetworks.com> To: Andre Przywara <andre.przywara@arm.com>, Christoffer Dall <christoffer.dall@linaro.org>, Marc Zyngier <marc.zyngier@arm.com>, "Eric Auger" <eric.auger@linaro.org> Cc: "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org> Subject: Re: [PATCH v4 03/12] KVM: arm64: Introduce new MMIO region for the ITS base address Date: Thu, 5 May 2016 18:08:51 +0000 [thread overview] Message-ID: <651B7BE4-D1C9-44B2-84BE-19103C1D8CE0@caviumnetworks.com> (raw) In-Reply-To: <1458958450-19662-4-git-send-email-andre.przywara@arm.com> On 3/25/16, 7:14 PM, "kvmarm-bounces@lists.cs.columbia.edu on behalf of Andre Przywara" <kvmarm-bounces@lists.cs.columbia.edu on behalf of andre.przywara@arm.com> wrote: >The ARM GICv3 ITS controller requires a separate register frame to >cover ITS specific registers. Add a new VGIC address type and store >the address in a field in the vgic_dist structure. >Provide a function to check whether userland has provided the address, >so ITS functionality can be guarded by that check. > >Signed-off-by: Andre Przywara <andre.przywara@arm.com> >--- > Documentation/virtual/kvm/devices/arm-vgic.txt | 9 +++++++++ > arch/arm64/include/uapi/asm/kvm.h | 2 ++ > include/kvm/vgic/vgic.h | 5 +++++ > virt/kvm/arm/vgic/vgic.c | 10 ++++++++++ > virt/kvm/arm/vgic/vgic_init.c | 1 + > virt/kvm/arm/vgic/vgic_kvm_device.c | 7 +++++++ > 6 files changed, 34 insertions(+) > >diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt >index 59541d4..087e2d9 100644 >--- a/Documentation/virtual/kvm/devices/arm-vgic.txt >+++ b/Documentation/virtual/kvm/devices/arm-vgic.txt >@@ -39,6 +39,15 @@ Groups: > Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. > This address needs to be 64K aligned. > >+ KVM_VGIC_V3_ADDR_TYPE_ITS (rw, 64-bit) >+ Base address in the guest physical address space of the GICv3 ITS >+ control register frame. The ITS allows MSI(-X) interrupts to be >+ injected into guests. This extension is optional, if the kernel >+ does not support the ITS, the call returns -ENODEV. >+ This memory is solely for the guest to access the ITS control >+ registers and does not cover the ITS translation register. >+ Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. >+ This address needs to be 64K aligned and the region covers 64 KByte. > > KVM_DEV_ARM_VGIC_GRP_DIST_REGS > Attributes: >diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h >index f209ea1..c2b257d 100644 >--- a/arch/arm64/include/uapi/asm/kvm.h >+++ b/arch/arm64/include/uapi/asm/kvm.h >@@ -87,9 +87,11 @@ struct kvm_regs { > /* Supported VGICv3 address types */ > #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 > #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 >+#define KVM_VGIC_V3_ADDR_TYPE_ITS 4 > > #define KVM_VGIC_V3_DIST_SIZE SZ_64K > #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) >+#define KVM_VGIC_V3_ITS_SIZE SZ_64K > > #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ > #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ >diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h >index 7c1d145..11344e6 100644 >--- a/include/kvm/vgic/vgic.h >+++ b/include/kvm/vgic/vgic.h >@@ -135,6 +135,9 @@ struct vgic_dist { > gpa_t vgic_redist_base; > }; > >+ /* The base address of the ITS control register frame */ >+ gpa_t vgic_its_base; >+ > /* distributor enabled */ > u32 enabled; > >@@ -253,4 +256,6 @@ static inline int kvm_vgic_get_max_vcpus(void) > return kvm_vgic_global_state.max_gic_vcpus; > } > >+bool vgic_has_its(struct kvm *kvm); >+ > #endif /* __ASM_ARM_KVM_VGIC_VGIC_H */ >diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c >index 65395af..1de2478 100644 >--- a/virt/kvm/arm/vgic/vgic.c >+++ b/virt/kvm/arm/vgic/vgic.c >@@ -612,3 +612,13 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, u32 intid) > > return map_is_active; > } >+ >+bool vgic_has_its(struct kvm *kvm) >+{ >+ struct vgic_dist *dist = &kvm->arch.vgic; >+ >+ if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) >+ return false; >+ >+ return !IS_VGIC_ADDR_UNDEF(dist->vgic_its_base); >+} >diff --git a/virt/kvm/arm/vgic/vgic_init.c b/virt/kvm/arm/vgic/vgic_init.c >index ac655b5..2301e03 100644 >--- a/virt/kvm/arm/vgic/vgic_init.c >+++ b/virt/kvm/arm/vgic/vgic_init.c >@@ -132,6 +132,7 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) > kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; > kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; > kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; >+ kvm->arch.vgic.vgic_its_base = VGIC_ADDR_UNDEF; > > out_unlock: > for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { >diff --git a/virt/kvm/arm/vgic/vgic_kvm_device.c b/virt/kvm/arm/vgic/vgic_kvm_device.c >index 7f78a16..3ec2ac3 100644 >--- a/virt/kvm/arm/vgic/vgic_kvm_device.c >+++ b/virt/kvm/arm/vgic/vgic_kvm_device.c >@@ -109,6 +109,12 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) > block_size = KVM_VGIC_V3_REDIST_SIZE; > alignment = SZ_64K; > break; >+ case KVM_VGIC_V3_ADDR_TYPE_ITS: >+ type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; >+ addr_ptr = &vgic->vgic_its_base; >+ block_size = KVM_VGIC_V3_ITS_SIZE; >+ alignment = SZ_64K; >+ break; Should there be a check based on number of vcpus? > #endif > default: > r = -ENODEV; >@@ -495,6 +501,7 @@ static int vgic_v3_has_attr(struct kvm_device *dev, > switch (attr->attr) { > case KVM_VGIC_V3_ADDR_TYPE_DIST: > case KVM_VGIC_V3_ADDR_TYPE_REDIST: >+ case KVM_VGIC_V3_ADDR_TYPE_ITS: > return 0; > } > break; >-- >2.7.3 > >_______________________________________________ >kvmarm mailing list >kvmarm@lists.cs.columbia.edu >https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Tirumalesh.Chalamarla@caviumnetworks.com (Chalamarla, Tirumalesh) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 03/12] KVM: arm64: Introduce new MMIO region for the ITS base address Date: Thu, 5 May 2016 18:08:51 +0000 [thread overview] Message-ID: <651B7BE4-D1C9-44B2-84BE-19103C1D8CE0@caviumnetworks.com> (raw) In-Reply-To: <1458958450-19662-4-git-send-email-andre.przywara@arm.com> On 3/25/16, 7:14 PM, "kvmarm-bounces at lists.cs.columbia.edu on behalf of Andre Przywara" <kvmarm-bounces at lists.cs.columbia.edu on behalf of andre.przywara@arm.com> wrote: >The ARM GICv3 ITS controller requires a separate register frame to >cover ITS specific registers. Add a new VGIC address type and store >the address in a field in the vgic_dist structure. >Provide a function to check whether userland has provided the address, >so ITS functionality can be guarded by that check. > >Signed-off-by: Andre Przywara <andre.przywara@arm.com> >--- > Documentation/virtual/kvm/devices/arm-vgic.txt | 9 +++++++++ > arch/arm64/include/uapi/asm/kvm.h | 2 ++ > include/kvm/vgic/vgic.h | 5 +++++ > virt/kvm/arm/vgic/vgic.c | 10 ++++++++++ > virt/kvm/arm/vgic/vgic_init.c | 1 + > virt/kvm/arm/vgic/vgic_kvm_device.c | 7 +++++++ > 6 files changed, 34 insertions(+) > >diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt >index 59541d4..087e2d9 100644 >--- a/Documentation/virtual/kvm/devices/arm-vgic.txt >+++ b/Documentation/virtual/kvm/devices/arm-vgic.txt >@@ -39,6 +39,15 @@ Groups: > Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. > This address needs to be 64K aligned. > >+ KVM_VGIC_V3_ADDR_TYPE_ITS (rw, 64-bit) >+ Base address in the guest physical address space of the GICv3 ITS >+ control register frame. The ITS allows MSI(-X) interrupts to be >+ injected into guests. This extension is optional, if the kernel >+ does not support the ITS, the call returns -ENODEV. >+ This memory is solely for the guest to access the ITS control >+ registers and does not cover the ITS translation register. >+ Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. >+ This address needs to be 64K aligned and the region covers 64 KByte. > > KVM_DEV_ARM_VGIC_GRP_DIST_REGS > Attributes: >diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h >index f209ea1..c2b257d 100644 >--- a/arch/arm64/include/uapi/asm/kvm.h >+++ b/arch/arm64/include/uapi/asm/kvm.h >@@ -87,9 +87,11 @@ struct kvm_regs { > /* Supported VGICv3 address types */ > #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 > #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 >+#define KVM_VGIC_V3_ADDR_TYPE_ITS 4 > > #define KVM_VGIC_V3_DIST_SIZE SZ_64K > #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) >+#define KVM_VGIC_V3_ITS_SIZE SZ_64K > > #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ > #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ >diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h >index 7c1d145..11344e6 100644 >--- a/include/kvm/vgic/vgic.h >+++ b/include/kvm/vgic/vgic.h >@@ -135,6 +135,9 @@ struct vgic_dist { > gpa_t vgic_redist_base; > }; > >+ /* The base address of the ITS control register frame */ >+ gpa_t vgic_its_base; >+ > /* distributor enabled */ > u32 enabled; > >@@ -253,4 +256,6 @@ static inline int kvm_vgic_get_max_vcpus(void) > return kvm_vgic_global_state.max_gic_vcpus; > } > >+bool vgic_has_its(struct kvm *kvm); >+ > #endif /* __ASM_ARM_KVM_VGIC_VGIC_H */ >diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c >index 65395af..1de2478 100644 >--- a/virt/kvm/arm/vgic/vgic.c >+++ b/virt/kvm/arm/vgic/vgic.c >@@ -612,3 +612,13 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, u32 intid) > > return map_is_active; > } >+ >+bool vgic_has_its(struct kvm *kvm) >+{ >+ struct vgic_dist *dist = &kvm->arch.vgic; >+ >+ if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) >+ return false; >+ >+ return !IS_VGIC_ADDR_UNDEF(dist->vgic_its_base); >+} >diff --git a/virt/kvm/arm/vgic/vgic_init.c b/virt/kvm/arm/vgic/vgic_init.c >index ac655b5..2301e03 100644 >--- a/virt/kvm/arm/vgic/vgic_init.c >+++ b/virt/kvm/arm/vgic/vgic_init.c >@@ -132,6 +132,7 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) > kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; > kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; > kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; >+ kvm->arch.vgic.vgic_its_base = VGIC_ADDR_UNDEF; > > out_unlock: > for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { >diff --git a/virt/kvm/arm/vgic/vgic_kvm_device.c b/virt/kvm/arm/vgic/vgic_kvm_device.c >index 7f78a16..3ec2ac3 100644 >--- a/virt/kvm/arm/vgic/vgic_kvm_device.c >+++ b/virt/kvm/arm/vgic/vgic_kvm_device.c >@@ -109,6 +109,12 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) > block_size = KVM_VGIC_V3_REDIST_SIZE; > alignment = SZ_64K; > break; >+ case KVM_VGIC_V3_ADDR_TYPE_ITS: >+ type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; >+ addr_ptr = &vgic->vgic_its_base; >+ block_size = KVM_VGIC_V3_ITS_SIZE; >+ alignment = SZ_64K; >+ break; Should there be a check based on number of vcpus? > #endif > default: > r = -ENODEV; >@@ -495,6 +501,7 @@ static int vgic_v3_has_attr(struct kvm_device *dev, > switch (attr->attr) { > case KVM_VGIC_V3_ADDR_TYPE_DIST: > case KVM_VGIC_V3_ADDR_TYPE_REDIST: >+ case KVM_VGIC_V3_ADDR_TYPE_ITS: > return 0; > } > break; >-- >2.7.3 > >_______________________________________________ >kvmarm mailing list >kvmarm at lists.cs.columbia.edu >https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2016-05-05 18:08 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-03-26 2:13 [PATCH v4 00/12] KVM: arm64: GICv3 ITS emulation Andre Przywara 2016-03-26 2:13 ` Andre Przywara 2016-03-26 2:13 ` [PATCH v4 01/12] KVM: extend struct kvm_msi to hold a 32-bit device ID Andre Przywara 2016-03-26 2:13 ` Andre Przywara 2016-04-03 9:15 ` Christoffer Dall 2016-04-03 9:15 ` Christoffer Dall 2016-05-25 15:55 ` Andre Przywara 2016-05-25 15:55 ` Andre Przywara 2016-05-25 16:16 ` Marc Zyngier 2016-05-25 16:16 ` Marc Zyngier 2016-05-31 13:05 ` Christoffer Dall 2016-05-31 13:05 ` Christoffer Dall 2016-05-05 17:55 ` Chalamarla, Tirumalesh 2016-05-05 17:55 ` Chalamarla, Tirumalesh 2016-03-26 2:14 ` [PATCH v4 02/12] KVM: arm/arm64: extend arch CAP checks to allow per-VM capabilities Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-03 10:08 ` Christoffer Dall 2016-04-03 10:08 ` Christoffer Dall 2016-04-05 12:48 ` Eric Auger 2016-04-05 12:48 ` Eric Auger 2016-05-05 18:00 ` Chalamarla, Tirumalesh 2016-05-05 18:00 ` Chalamarla, Tirumalesh 2016-03-26 2:14 ` [PATCH v4 03/12] KVM: arm64: Introduce new MMIO region for the ITS base address Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-03 10:08 ` Christoffer Dall 2016-04-03 10:08 ` Christoffer Dall 2016-04-05 12:47 ` Eric Auger 2016-04-05 12:47 ` Eric Auger 2016-04-07 13:44 ` Marc Zyngier 2016-04-07 13:44 ` Marc Zyngier 2016-05-05 18:08 ` Chalamarla, Tirumalesh [this message] 2016-05-05 18:08 ` Chalamarla, Tirumalesh 2016-05-09 15:47 ` Marc Zyngier 2016-05-09 15:47 ` Marc Zyngier 2016-05-09 16:53 ` Chalamarla, Tirumalesh 2016-05-09 16:53 ` Chalamarla, Tirumalesh 2016-05-09 17:09 ` Marc Zyngier 2016-05-09 17:09 ` Marc Zyngier 2016-03-26 2:14 ` [PATCH v4 04/12] KVM: arm64: handle ITS related GICv3 redistributor registers Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-03 10:08 ` Christoffer Dall 2016-04-03 10:08 ` Christoffer Dall 2016-04-05 12:55 ` Eric Auger 2016-04-05 12:55 ` Eric Auger 2016-04-05 15:17 ` Eric Auger 2016-04-05 15:17 ` Eric Auger 2016-04-07 13:54 ` Marc Zyngier 2016-04-07 13:54 ` Marc Zyngier 2016-04-07 13:58 ` Marc Zyngier 2016-04-07 13:58 ` Marc Zyngier 2016-05-05 18:06 ` Chalamarla, Tirumalesh 2016-05-05 18:06 ` Chalamarla, Tirumalesh 2016-03-26 2:14 ` [PATCH v4 05/12] KVM: arm64: introduce ITS emulation file with stub functions Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-05 16:03 ` Eric Auger 2016-04-05 16:03 ` Eric Auger 2016-04-07 14:04 ` Marc Zyngier 2016-04-07 14:04 ` Marc Zyngier 2016-04-07 14:08 ` Eric Auger 2016-04-07 14:08 ` Eric Auger 2016-04-07 14:48 ` Marc Zyngier 2016-04-07 14:48 ` Marc Zyngier 2016-04-07 15:09 ` Eric Auger 2016-04-07 15:09 ` Eric Auger 2016-04-07 15:19 ` Marc Zyngier 2016-04-07 15:19 ` Marc Zyngier 2016-03-26 2:14 ` [PATCH v4 06/12] KVM: arm64: implement basic ITS register handlers Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-03 10:08 ` Christoffer Dall 2016-04-03 10:08 ` Christoffer Dall 2016-04-06 9:36 ` Eric Auger 2016-04-06 9:36 ` Eric Auger 2016-05-25 13:49 ` Andre Przywara 2016-05-25 13:49 ` Andre Przywara 2016-04-07 14:35 ` Marc Zyngier 2016-04-07 14:35 ` Marc Zyngier 2016-05-25 11:37 ` Andre Przywara 2016-05-25 11:37 ` Andre Przywara 2016-05-26 9:10 ` Marc Zyngier 2016-05-26 9:10 ` Marc Zyngier 2016-06-03 15:42 ` Andre Przywara 2016-06-03 15:42 ` Andre Przywara 2016-06-03 16:54 ` Marc Zyngier 2016-06-03 16:54 ` Marc Zyngier 2016-05-05 18:51 ` Chalamarla, Tirumalesh 2016-05-05 18:51 ` Chalamarla, Tirumalesh 2016-03-26 2:14 ` [PATCH v4 07/12] KVM: arm64: add data structures to model ITS interrupt translation Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-06 9:53 ` Eric Auger 2016-04-06 9:53 ` Eric Auger 2016-03-26 2:14 ` [PATCH v4 08/12] KVM: arm64: connect LPIs to the VGIC emulation Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-06 12:00 ` Eric Auger 2016-04-06 12:00 ` Eric Auger 2016-05-05 18:59 ` Chalamarla, Tirumalesh 2016-05-05 18:59 ` Chalamarla, Tirumalesh 2016-03-26 2:14 ` [PATCH v4 09/12] KVM: arm64: sync LPI configuration and pending tables Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-04-06 13:41 ` Eric Auger 2016-04-06 13:41 ` Eric Auger 2016-06-03 14:17 ` Andre Przywara 2016-06-03 14:17 ` Andre Przywara 2016-03-26 2:14 ` [PATCH v4 10/12] KVM: arm64: implement ITS command queue command handlers Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-05-05 19:12 ` Chalamarla, Tirumalesh 2016-05-05 19:12 ` Chalamarla, Tirumalesh 2016-05-25 14:34 ` Andre Przywara 2016-05-25 14:34 ` Andre Przywara 2016-03-26 2:14 ` [PATCH v4 11/12] KVM: arm64: implement MSI injection in ITS emulation Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-03-26 2:14 ` [PATCH v4 12/12] KVM: arm64: enable ITS emulation as a virtual MSI controller Andre Przywara 2016-03-26 2:14 ` Andre Przywara 2016-06-03 4:26 ` [PATCH v4 00/12] KVM: arm64: GICv3 ITS emulation Bharat Bhushan 2016-06-03 4:26 ` Bharat Bhushan 2016-06-03 14:32 ` Andre Przywara 2016-06-03 14:32 ` Andre Przywara 2016-06-06 5:29 ` Bharat Bhushan 2016-06-06 5:29 ` Bharat Bhushan 2016-06-07 8:02 ` Christoffer Dall 2016-06-07 8:02 ` Christoffer Dall
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